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Sender: Richard Henderson <rth7680@gmail.com>
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From: Richard Henderson <rth@twiddle.net>
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Date: Mon, 28 Nov 2016 00:11:11 -0800
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Subject: Re: [Qemu-devel] [PATCH v3 11/11] tcg-mips: Adjust condition
 functions for mips64
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To: Jin Guojie <jinguojie@loongson.cn>, Aurelien Jarno <aurelien@aurel32.net>
Cc: qemu-devel <qemu-devel@nongnu.org>, James Hogan <james.hogan@imgtec.com>

On 11/27/2016 11:42 PM, Jin Guojie wrote:
> By reading Richard and Aurelien's comment, I realized now the best way to solve this problem
> is not to add ext32s in brcond_32i, but to fix the helper function. In another word,
> the register value should be 32-bit sign-extened at where it's being *created*, not where
> it's being *utilized*. Maybe I can do this ext32s after helper_le_ld_name() is call back to ensure
>  V0 to be sign-extended.

It's not necessarily V0 that needs to be extended, but the destination register 
(S1 in this case).  So perhaps

      tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
      /* delay slot */
-    tcg_out_mov(s, TCG_TYPE_REG, v0, TCG_REG_V0);
+    if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) {
+        tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0);
+    } else {
+        tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
+    }

so that we always sign-extend 32-bit loads.


r~