From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0C2BC43334 for ; Thu, 2 Jun 2022 16:24:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236976AbiFBQYf (ORCPT ); Thu, 2 Jun 2022 12:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235060AbiFBQYb (ORCPT ); Thu, 2 Jun 2022 12:24:31 -0400 Received: from desiato.infradead.org (desiato.infradead.org [IPv6:2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89B99183B8 for ; Thu, 2 Jun 2022 09:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :In-Reply-To:From:References:To:Subject:MIME-Version:Date:Message-ID:Sender: Reply-To:Cc:Content-ID:Content-Description; bh=ULsaBdzIjNY9UlBzRBFJHpbCyKR8X0rIBrR1eB+c08A=; b=G6WU1GUIS0iwi/bybRPUvGMkH8 g5GmOalwZYTCL+uEuOPOL9Ux89HvrMgvXjEABpyhgivSYhw2lmEqEd5fgmT4jIzeJy1y9OTySFgqH JqkRLzW4neHF3cgs7JU6gqJ3qbJnJ0lNq6AT1HRkfZdt/+hVFyOWz7M1NlhyVNVpwJt6U+NEW29p4 9CMUlbrXpWW7ZUlbyDy2I4FeRH9xhs0Z9CxbuvD+ZsDbKRJY0J36SeQ5xYfaVSHOtjf1juPwo1qm7 n+jgwxOlHf9PE/dBVocOILMAQ8dE3mmmr5QG+6XEhh0kua1y2A1OU0lBI3G/zvbTaE2ukgLP8ASgf yTvVv60g==; Received: from [2601:1c0:6280:3f0::aa0b] by desiato.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwncQ-0049hG-9P; Thu, 02 Jun 2022 16:24:18 +0000 Message-ID: Date: Thu, 2 Jun 2022 09:24:12 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [RFC PATCH] riscv: Add Zawrs support for spinlocks Content-Language: en-US To: Christoph Muellner , Palmer Dabbelt , Paul Walmsley , Albert Ou , Christoph Muellner , Heiko Stuebner , Philipp Tomsich , Aaron Durbin , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220602141032.169907-1-christoph.muellner@vrull.io> From: Randy Dunlap In-Reply-To: <20220602141032.169907-1-christoph.muellner@vrull.io> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi-- On 6/2/22 07:10, Christoph Muellner wrote: > The current RISC-V code uses the generic ticket lock implementation, > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > Currently, RISC-V uses the generic implementation of these macros. > This patch introduces a RISC-V specific implementation, of these > macros, that peels off the first loop iteration and modifies the waiting > loop such, that it is possible to use the WRS instruction of the Zawrs > ISA extension to stall the CPU. > > The resulting implementation of smp_cond_load_*() will only work for > 32-bit or 64-bit types for RV64 and 32-bit types for RV32. > This is caused by the restrictions of the LR instruction (RISC-V only > has LR.W and LR.D). Compiler assertions guard this new restriction. > > This patch uses the existing RISC-V ISA extension framework > to detect the presents of Zawrs at run-time. > If available a NOP instruction will be replaced by WRS. > A similar patch could add support for the PAUSE instruction of > the Zihintpause ISA extension. > > The whole mechanism is gated by Kconfig setting, which defaults to Y. > > The Zawrs specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is not frozen or ratified yet. > Therefore this patch is an RFC and not intended to get merged. > > Signed-off-by: Christoph Muellner > --- > arch/riscv/Kconfig | 10 +++ > arch/riscv/include/asm/barrier.h | 97 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/errata_list.h | 12 +++- > arch/riscv/include/asm/hwcap.h | 3 +- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 13 ++++ > 6 files changed, 133 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 905e550e0fd3..054872317d4a 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -358,6 +358,16 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZAWRS > + bool "Zawrs extension support" > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Zawrs extension > + (wait for reservation set) and enable its usage. > + > + If you don't know what to do here, say Y. > + With this patch, it is possible to enable XIP_KERNEL and RISCV_ISA_ZAWRS at the same time. That causes a kconfig warning: WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE Depends on [n]: !XIP_KERNEL [=y] Selected by [y]: - RISCV_ISA_ZAWRS [=y] - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] because RISCV_ALTERNATIVE depends on !XIP_KERNEL: config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL > config RISCV_ISA_SVPBMT > bool "SVPBMT extension support" > depends on 64BIT && MMU -- ~Randy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B063CC433EF for ; Thu, 2 Jun 2022 16:24:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=F0CFASwcKpp+GDGKCkdOsHlOWGN2s7jD8Za40SLyULY=; b=m4etogZ7P8+UjA rdeII+KnPmwu1bQjFXNAbNHrPUwMWzOgII31iQ3LQsjIQVjSycxv6tXzC8zWwqTXotapwKtRnF1FZ 4+6fIUUIHBkWrSireAAIK9o2U1aqyGW8QrTuwGzdp8PxvoywgF66OziBb58phXAfQ/cfqfn8RPYYE Ph8VD4E4nLqz6MUW0IEuXOfhpCIl57jrgD2TC73tsWO7JHyZGYPiBQEEGbrx4fjoHMMYulEpiXFRE kvv9sfsz/hsHUAl5XrvQcPGvqu7DYfHkU4TbeO4oAztbCbWqzsY1JOaigmJ9WIG7IxVrAHg02UJO5 XM6/F29zAz+GeOG781jg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwncW-003lrY-2U; Thu, 02 Jun 2022 16:24:24 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwncV-003lrO-7g for linux-riscv@bombadil.infradead.org; Thu, 02 Jun 2022 16:24:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :In-Reply-To:From:References:To:Subject:MIME-Version:Date:Message-ID:Sender: Reply-To:Cc:Content-ID:Content-Description; bh=ULsaBdzIjNY9UlBzRBFJHpbCyKR8X0rIBrR1eB+c08A=; b=G6WU1GUIS0iwi/bybRPUvGMkH8 g5GmOalwZYTCL+uEuOPOL9Ux89HvrMgvXjEABpyhgivSYhw2lmEqEd5fgmT4jIzeJy1y9OTySFgqH JqkRLzW4neHF3cgs7JU6gqJ3qbJnJ0lNq6AT1HRkfZdt/+hVFyOWz7M1NlhyVNVpwJt6U+NEW29p4 9CMUlbrXpWW7ZUlbyDy2I4FeRH9xhs0Z9CxbuvD+ZsDbKRJY0J36SeQ5xYfaVSHOtjf1juPwo1qm7 n+jgwxOlHf9PE/dBVocOILMAQ8dE3mmmr5QG+6XEhh0kua1y2A1OU0lBI3G/zvbTaE2ukgLP8ASgf yTvVv60g==; Received: from [2601:1c0:6280:3f0::aa0b] by desiato.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwncQ-0049hG-9P; Thu, 02 Jun 2022 16:24:18 +0000 Message-ID: Date: Thu, 2 Jun 2022 09:24:12 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [RFC PATCH] riscv: Add Zawrs support for spinlocks Content-Language: en-US To: Christoph Muellner , Palmer Dabbelt , Paul Walmsley , Albert Ou , Christoph Muellner , Heiko Stuebner , Philipp Tomsich , Aaron Durbin , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20220602141032.169907-1-christoph.muellner@vrull.io> From: Randy Dunlap In-Reply-To: <20220602141032.169907-1-christoph.muellner@vrull.io> X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi-- On 6/2/22 07:10, Christoph Muellner wrote: > The current RISC-V code uses the generic ticket lock implementation, > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > Currently, RISC-V uses the generic implementation of these macros. > This patch introduces a RISC-V specific implementation, of these > macros, that peels off the first loop iteration and modifies the waiting > loop such, that it is possible to use the WRS instruction of the Zawrs > ISA extension to stall the CPU. > > The resulting implementation of smp_cond_load_*() will only work for > 32-bit or 64-bit types for RV64 and 32-bit types for RV32. > This is caused by the restrictions of the LR instruction (RISC-V only > has LR.W and LR.D). Compiler assertions guard this new restriction. > > This patch uses the existing RISC-V ISA extension framework > to detect the presents of Zawrs at run-time. > If available a NOP instruction will be replaced by WRS. > A similar patch could add support for the PAUSE instruction of > the Zihintpause ISA extension. > > The whole mechanism is gated by Kconfig setting, which defaults to Y. > > The Zawrs specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is not frozen or ratified yet. > Therefore this patch is an RFC and not intended to get merged. > > Signed-off-by: Christoph Muellner > --- > arch/riscv/Kconfig | 10 +++ > arch/riscv/include/asm/barrier.h | 97 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/errata_list.h | 12 +++- > arch/riscv/include/asm/hwcap.h | 3 +- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 13 ++++ > 6 files changed, 133 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 905e550e0fd3..054872317d4a 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -358,6 +358,16 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZAWRS > + bool "Zawrs extension support" > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Zawrs extension > + (wait for reservation set) and enable its usage. > + > + If you don't know what to do here, say Y. > + With this patch, it is possible to enable XIP_KERNEL and RISCV_ISA_ZAWRS at the same time. That causes a kconfig warning: WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE Depends on [n]: !XIP_KERNEL [=y] Selected by [y]: - RISCV_ISA_ZAWRS [=y] - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] because RISCV_ALTERNATIVE depends on !XIP_KERNEL: config RISCV_ALTERNATIVE bool depends on !XIP_KERNEL > config RISCV_ISA_SVPBMT > bool "SVPBMT extension support" > depends on 64BIT && MMU -- ~Randy _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv