From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: [PATCH 1/2] drm/amdgpu/gfx7: enable cp/rlc ints after we disable clockgating Date: Tue, 11 Apr 2017 08:44:15 +0200 Message-ID: References: <1491860758-22182-1-git-send-email-alexander.deucher@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1491860758-22182-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Alex Deucher , amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Alex Deucher QW0gMTAuMDQuMjAxNyB1bSAyMzo0NSBzY2hyaWViIEFsZXggRGV1Y2hlcjoKPiBFdmVuIGlmIHdl IGRpc2FibGUgY2xvY2tnYXRpbmcsIHdlIHN0aWxsIG5lZWQgdG8gbWFrZSBzdXJlIHRoZQo+IGNw L3JsYyBpbnRlcnJ1cHRzIGFyZSBlbmFibGVkIGZvciBwb3dlcmdhdGluZyB3aGljaCBtaWdodCBz dGlsbAo+IGJlIGVuYWJsZWQuCj4KPiBTaWduZWQtb2ZmLWJ5OiBBbGV4IERldWNoZXIgPGFsZXhh bmRlci5kZXVjaGVyQGFtZC5jb20+CgpBY2tlZC1ieTogQ2hyaXN0aWFuIEvDtm5pZyA8Y2hyaXN0 aWFuLmtvZW5pZ0BhbWQuY29tPiBmb3IgYm90aC4KCj4gLS0tCj4gICBkcml2ZXJzL2dwdS9kcm0v YW1kL2FtZGdwdS9nZnhfdjdfMC5jIHwgMTEgKysrKysrKy0tLS0KPiAgIDEgZmlsZSBjaGFuZ2Vk LCA3IGluc2VydGlvbnMoKyksIDQgZGVsZXRpb25zKC0pCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVy cy9ncHUvZHJtL2FtZC9hbWRncHUvZ2Z4X3Y3XzAuYyBiL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1k Z3B1L2dmeF92N18wLmMKPiBpbmRleCA4YThiYzJmLi4xODVjYjMxIDEwMDY0NAo+IC0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2dmeF92N18wLmMKPiArKysgYi9kcml2ZXJzL2dwdS9k cm0vYW1kL2FtZGdwdS9nZnhfdjdfMC5jCj4gQEAgLTM3OTcsNiArMzc5Nyw5IEBAIHN0YXRpYyB2 b2lkIGdmeF92N18wX2VuYWJsZV9jZ2NnKHN0cnVjdCBhbWRncHVfZGV2aWNlICphZGV2LCBib29s IGVuYWJsZSkKPiAgIAkJZ2Z4X3Y3XzBfdXBkYXRlX3JsYyhhZGV2LCB0bXApOwo+ICAgCj4gICAJ CWRhdGEgfD0gUkxDX0NHQ0dfQ0dMU19DVFJMX19DR0NHX0VOX01BU0sgfCBSTENfQ0dDR19DR0xT X0NUUkxfX0NHTFNfRU5fTUFTSzsKPiArCQlpZiAob3JpZyAhPSBkYXRhKQo+ICsJCQlXUkVHMzIo bW1STENfQ0dDR19DR0xTX0NUUkwsIGRhdGEpOwo+ICsKPiAgIAl9IGVsc2Ugewo+ICAgCQlnZnhf djdfMF9lbmFibGVfZ3VpX2lkbGVfaW50ZXJydXB0KGFkZXYsIGZhbHNlKTsKPiAgIAo+IEBAIC0z ODA2LDExICszODA5LDExIEBAIHN0YXRpYyB2b2lkIGdmeF92N18wX2VuYWJsZV9jZ2NnKHN0cnVj dCBhbWRncHVfZGV2aWNlICphZGV2LCBib29sIGVuYWJsZSkKPiAgIAkJUlJFRzMyKG1tQ0JfQ0dU VF9TQ0xLX0NUUkwpOwo+ICAgCj4gICAJCWRhdGEgJj0gfihSTENfQ0dDR19DR0xTX0NUUkxfX0NH Q0dfRU5fTUFTSyB8IFJMQ19DR0NHX0NHTFNfQ1RSTF9fQ0dMU19FTl9NQVNLKTsKPiAtCX0KPiAt Cj4gLQlpZiAob3JpZyAhPSBkYXRhKQo+IC0JCVdSRUczMihtbVJMQ19DR0NHX0NHTFNfQ1RSTCwg ZGF0YSk7Cj4gKwkJaWYgKG9yaWcgIT0gZGF0YSkKPiArCQkJV1JFRzMyKG1tUkxDX0NHQ0dfQ0dM U19DVFJMLCBkYXRhKTsKPiAgIAo+ICsJCWdmeF92N18wX2VuYWJsZV9ndWlfaWRsZV9pbnRlcnJ1 cHQoYWRldiwgdHJ1ZSk7Cj4gKwl9Cj4gICB9Cj4gICAKPiAgIHN0YXRpYyB2b2lkIGdmeF92N18w X2VuYWJsZV9tZ2NnKHN0cnVjdCBhbWRncHVfZGV2aWNlICphZGV2LCBib29sIGVuYWJsZSkKCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwphbWQtZ2Z4IG1h aWxpbmcgbGlzdAphbWQtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK