From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E977AC433ED for ; Thu, 1 Apr 2021 21:01:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C23786105A for ; Thu, 1 Apr 2021 21:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234062AbhDAVBT (ORCPT ); Thu, 1 Apr 2021 17:01:19 -0400 Received: from mga12.intel.com ([192.55.52.136]:34410 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234316AbhDAVBR (ORCPT ); Thu, 1 Apr 2021 17:01:17 -0400 IronPort-SDR: sTIh6oi+NaPG0lgfRl0AV5zusrNKfB85Z7aKXqTFoayc+zowDqoAFDV0sVrpOUVhVtOyGdClhG DWNiJfT2qbrg== X-IronPort-AV: E=McAfee;i="6000,8403,9941"; a="171747483" X-IronPort-AV: E=Sophos;i="5.81,296,1610438400"; d="scan'208";a="171747483" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 14:01:16 -0700 IronPort-SDR: oPbzk+Agwy3s+gVLNHQHOTEhmS7fFewdVMOo1LWxz59k+t9JdZ2WmDQRrxW0f0BN6YGVjvs0vk iZJ4aus6HOTg== X-IronPort-AV: E=Sophos;i="5.81,296,1610438400"; d="scan'208";a="611061513" Received: from pzlai-mobl.amr.corp.intel.com (HELO [10.213.169.242]) ([10.213.169.242]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2021 14:01:16 -0700 Subject: Re: [RFC v1 25/26] x86/tdx: Make DMA pages shared To: Kuppuswamy Sathyanarayanan , Peter Zijlstra , Andy Lutomirski Cc: Andi Kleen , Kirill Shutemov , Kuppuswamy Sathyanarayanan , Dan Williams , Raj Ashok , Sean Christopherson , linux-kernel@vger.kernel.org, Kai Huang , Sean Christopherson References: <0bc9209a36760ee7c8591322327ddbfe87351b09.1612563142.git.sathyanarayanan.kuppuswamy@linux.intel.com> From: Dave Hansen Autocrypt: addr=dave.hansen@intel.com; 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Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <0bc9209a36760ee7c8591322327ddbfe87351b09.1612563142.git.sathyanarayanan.kuppuswamy@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > +int tdx_map_gpa(phys_addr_t gpa, int numpages, bool private) > +{ > + int ret, i; > + > + ret = __tdx_map_gpa(gpa, numpages, private); > + if (ret || !private) > + return ret; > + > + for (i = 0; i < numpages; i++) > + tdx_accept_page(gpa + i*PAGE_SIZE); > + > + return 0; > +} Please do something like this: enum tdx_max_type { TDX_MAP_PRIVATE, TDX_MAP_SHARED } Then, your calls will look like: tdx_map_gpa(gpa, nr, TDX_MAP_SHARED); instead of: tdx_map_gpa(gpa, nr, false); > static __cpuidle void tdx_halt(void) > { > register long r10 asm("r10") = TDVMCALL_STANDARD; > diff --git a/arch/x86/mm/mem_encrypt_common.c b/arch/x86/mm/mem_encrypt_common.c > index 964e04152417..b6d93b0c5dcf 100644 > --- a/arch/x86/mm/mem_encrypt_common.c > +++ b/arch/x86/mm/mem_encrypt_common.c > @@ -15,9 +15,9 @@ > bool force_dma_unencrypted(struct device *dev) > { > /* > - * For SEV, all DMA must be to unencrypted/shared addresses. > + * For SEV and TDX, all DMA must be to unencrypted/shared addresses. > */ > - if (sev_active()) > + if (sev_active() || is_tdx_guest()) > return true; > > /* > diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c > index 16f878c26667..6f23a9816ef0 100644 > --- a/arch/x86/mm/pat/set_memory.c > +++ b/arch/x86/mm/pat/set_memory.c > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include > > #include "../mm_internal.h" > > @@ -1977,8 +1978,8 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) > struct cpa_data cpa; > int ret; > > - /* Nothing to do if memory encryption is not active */ > - if (!mem_encrypt_active()) > + /* Nothing to do if memory encryption and TDX are not active */ > + if (!mem_encrypt_active() && !is_tdx_guest()) > return 0; So, this is starting to look like the "enc" naming is wrong, or at least a little misleading. Should we be talking about "protection" or "guards" or something? > /* Should not be working on unaligned addresses */ > @@ -1988,8 +1989,14 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) > memset(&cpa, 0, sizeof(cpa)); > cpa.vaddr = &addr; > cpa.numpages = numpages; > - cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0); > - cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC); > + if (is_tdx_guest()) { > + cpa.mask_set = __pgprot(enc ? 0 : tdx_shared_mask()); > + cpa.mask_clr = __pgprot(enc ? tdx_shared_mask() : 0); > + } else { > + cpa.mask_set = __pgprot(enc ? _PAGE_ENC : 0); > + cpa.mask_clr = __pgprot(enc ? 0 : _PAGE_ENC); > + } OK, this is too hideous to live. It sucks that the TDX and SEV/SME bits are opposite polarity, but oh well. To me, this gets a lot clearer, and opens up room for commenting if you do something like: if (is_tdx_guest()) { mem_enc_bits = 0; mem_plain_bits = tdx_shared_mask(); } else { mem_enc_bits = _PAGE_ENC; mem_plain_bits = 0 } if (enc) { cpa.mask_set = mem_enc_bits; cpa.mask_clr = mem_plain_bits; // clear "plain" bits } else { cpa.mask_set = mem_plain_bits; cpa.mask_clr = mem_enc_bits; // clear encryption bits } > cpa.pgd = init_mm.pgd; > > /* Must avoid aliasing mappings in the highmem code */ > @@ -1999,7 +2006,8 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) > /* > * Before changing the encryption attribute, we need to flush caches. > */ > - cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); > + if (!enc || !is_tdx_guest()) > + cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); That "!enc" looks wrong to me. Caches would need to be flushed whenever encryption attributes *change*, not just when they are set. Also, cpa_flush() flushes caches *AND* the TLB. How does TDX manage to not need TLB flushes? > ret = __change_page_attr_set_clr(&cpa, 1); > > @@ -2012,6 +2020,11 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) > */ > cpa_flush(&cpa, 0); > > + if (!ret && is_tdx_guest()) { > + ret = tdx_map_gpa(__pa(addr), numpages, enc); > + // XXX: need to undo on error? > + } Time to fix this stuff up if you want folks to take this series more seriously.