From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Date: Mon, 9 Dec 2019 23:12:35 +0300 Message-ID: References: <1575600535-26877-1-git-send-email-skomatineni@nvidia.com> <1575600535-26877-4-git-send-email-skomatineni@nvidia.com> <7cf4ff77-2f33-4ee5-0e09-5aa6aef3e8be@gmail.com> <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: allison@lohutok.net, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alexios.zavras@intel.com, alsa-devel@alsa-project.org List-Id: linux-tegra@vger.kernel.org 08.12.2019 00:36, Sowjanya Komatineni пишет: > > On 12/7/19 11:59 AM, Sowjanya Komatineni wrote: >> >> On 12/7/19 8:00 AM, Dmitry Osipenko wrote: >>> 07.12.2019 18:53, Dmitry Osipenko пишет: >>>> 07.12.2019 18:47, Dmitry Osipenko пишет: >>>>> 07.12.2019 17:28, Dmitry Osipenko пишет: >>>>>> 06.12.2019 05:48, Sowjanya Komatineni пишет: >>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3 >>>>>>> with >>>>>>> mux and gate for each of these clocks. >>>>>>> >>>>>>> Currently these PMC clocks are registered by Tegra clock driver >>>>>>> using >>>>>>> clk_register_mux and clk_register_gate by passing PMC base address >>>>>>> and register offsets and PMC programming for these clocks happens >>>>>>> through direct PMC access by the clock driver. >>>>>>> >>>>>>> With this, when PMC is in secure mode any direct PMC access from the >>>>>>> non-secure world does not go through and these clocks will not be >>>>>>> functional. >>>>>>> >>>>>>> This patch adds these clocks registration with PMC as a clock >>>>>>> provider >>>>>>> for these clocks. clk_ops callback implementations for these clocks >>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC >>>>>>> programming >>>>>>> in secure mode and non-secure mode. >>>>>>> >>>>>>> Signed-off-by: Sowjanya Komatineni >>>>>>> --- >>>>> [snip] >>>>> >>>>>>> + >>>>>>> +static const struct clk_ops pmc_clk_gate_ops = { >>>>>>> +    .is_enabled = pmc_clk_is_enabled, >>>>>>> +    .enable = pmc_clk_enable, >>>>>>> +    .disable = pmc_clk_disable, >>>>>>> +}; >>>>>> What's the benefit of separating GATE from the MUX? >>>>>> >>>>>> I think it could be a single clock. >>>>> According to TRM: >>>>> >>>>> 1. GATE and MUX are separate entities. >>>>> >>>>> 2. GATE is the parent of MUX (see PMC's CLK_OUT paths diagram in TRM). >>>>> >>>>> 3. PMC doesn't gate EXTPERIPH clock but could "force-enable" it, >>>>> correct? > > Was following existing clk-tegra-pmc as I am not sure of reason for > having these clocks registered as separate mux and gate clocks. > > Yes, PMC clocks can be registered as single clock and can use clk_ops > for set/get parent and enable/disable. > > enable/disable of PMC clocks is for force-enable to force the clock to > run regardless of ACCEPT_REQ or INVERT_REQ. > >>>> 4. clk_m_div2/4 are internal PMC OSC dividers and thus these clocks >>>> should belong to PMC. >>> Also, it should be "osc" and not "clk_m". >> >> I followed the same parents as it were in existing clk-tegra-pmc driver. >> >> Yeah they are wrong and they should be from osc and not clk_m. >> >> Will fix in next version. >> Could you please describe the full EXTPERIPH clock topology and how the pinmux configuration is related to it all? What is internal to the Tegra chip and what are the external outputs? Is it possible to bypass PMC on T30+ for the EXTPERIPH clocks? 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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id k25sm453452lji.42.2019.12.09.12.12.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Dec 2019 12:12:36 -0800 (PST) To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com References: <1575600535-26877-1-git-send-email-skomatineni@nvidia.com> <1575600535-26877-4-git-send-email-skomatineni@nvidia.com> <7cf4ff77-2f33-4ee5-0e09-5aa6aef3e8be@gmail.com> <288a1701-def6-d628-26bc-a305f817bdb1@gmail.com> <78644d45-2ae3-121f-99fc-0a46f205907d@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Mon, 9 Dec 2019 23:12:35 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Mailman-Approved-At: Tue, 10 Dec 2019 07:28:27 +0100 Cc: alsa-devel@alsa-project.org, pgaikwad@nvidia.com, spujar@nvidia.com, linux-kernel@vger.kernel.org, josephl@nvidia.com, linux-clk@vger.kernel.org, arnd@arndb.de, daniel.lezcano@linaro.org, krzk@kernel.org, mturquette@baylibre.com, devicetree@vger.kernel.org, mmaddireddy@nvidia.com, markz@nvidia.com, alexios.zavras@intel.com, broonie@kernel.org, linux-tegra@vger.kernel.org, horms+renesas@verge.net.au, tiwai@suse.com, allison@lohutok.net, pdeschrijver@nvidia.com, lgirdwood@gmail.com, vidyas@nvidia.com, Jisheng.Zhang@synaptics.com Subject: Re: [alsa-devel] [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" MDguMTIuMjAxOSAwMDozNiwgU293amFueWEgS29tYXRpbmVuaSDQv9C40YjQtdGCOgo+IAo+IE9u IDEyLzcvMTkgMTE6NTkgQU0sIFNvd2phbnlhIEtvbWF0aW5lbmkgd3JvdGU6Cj4+Cj4+IE9uIDEy LzcvMTkgODowMCBBTSwgRG1pdHJ5IE9zaXBlbmtvIHdyb3RlOgo+Pj4gMDcuMTIuMjAxOSAxODo1 MywgRG1pdHJ5IE9zaXBlbmtvINC/0LjRiNC10YI6Cj4+Pj4gMDcuMTIuMjAxOSAxODo0NywgRG1p dHJ5IE9zaXBlbmtvINC/0LjRiNC10YI6Cj4+Pj4+IDA3LjEyLjIwMTkgMTc6MjgsIERtaXRyeSBP c2lwZW5rbyDQv9C40YjQtdGCOgo+Pj4+Pj4gMDYuMTIuMjAxOSAwNTo0OCwgU293amFueWEgS29t YXRpbmVuaSDQv9C40YjQtdGCOgo+Pj4+Pj4+IFRlZ3JhMjEwIGFuZCBwcmlvciBUZWdyYSBQTUMg aGFzIGNsa19vdXRfMSwgY2xrX291dF8yLCBjbGtfb3V0XzMKPj4+Pj4+PiB3aXRoCj4+Pj4+Pj4g bXV4IGFuZCBnYXRlIGZvciBlYWNoIG9mIHRoZXNlIGNsb2Nrcy4KPj4+Pj4+Pgo+Pj4+Pj4+IEN1 cnJlbnRseSB0aGVzZSBQTUMgY2xvY2tzIGFyZSByZWdpc3RlcmVkIGJ5IFRlZ3JhIGNsb2NrIGRy aXZlcgo+Pj4+Pj4+IHVzaW5nCj4+Pj4+Pj4gY2xrX3JlZ2lzdGVyX211eCBhbmQgY2xrX3JlZ2lz dGVyX2dhdGUgYnkgcGFzc2luZyBQTUMgYmFzZSBhZGRyZXNzCj4+Pj4+Pj4gYW5kIHJlZ2lzdGVy IG9mZnNldHMgYW5kIFBNQyBwcm9ncmFtbWluZyBmb3IgdGhlc2UgY2xvY2tzIGhhcHBlbnMKPj4+ Pj4+PiB0aHJvdWdoIGRpcmVjdCBQTUMgYWNjZXNzIGJ5IHRoZSBjbG9jayBkcml2ZXIuCj4+Pj4+ Pj4KPj4+Pj4+PiBXaXRoIHRoaXMsIHdoZW4gUE1DIGlzIGluIHNlY3VyZSBtb2RlIGFueSBkaXJl Y3QgUE1DIGFjY2VzcyBmcm9tIHRoZQo+Pj4+Pj4+IG5vbi1zZWN1cmUgd29ybGQgZG9lcyBub3Qg Z28gdGhyb3VnaCBhbmQgdGhlc2UgY2xvY2tzIHdpbGwgbm90IGJlCj4+Pj4+Pj4gZnVuY3Rpb25h bC4KPj4+Pj4+Pgo+Pj4+Pj4+IFRoaXMgcGF0Y2ggYWRkcyB0aGVzZSBjbG9ja3MgcmVnaXN0cmF0 aW9uIHdpdGggUE1DIGFzIGEgY2xvY2sKPj4+Pj4+PiBwcm92aWRlcgo+Pj4+Pj4+IGZvciB0aGVz ZSBjbG9ja3MuIGNsa19vcHMgY2FsbGJhY2sgaW1wbGVtZW50YXRpb25zIGZvciB0aGVzZSBjbG9j a3MKPj4+Pj4+PiB1c2VzIHRlZ3JhX3BtY19yZWFkbCBhbmQgdGVncmFfcG1jX3dyaXRlbCB3aGlj aCBzdXBwb3J0cyBQTUMKPj4+Pj4+PiBwcm9ncmFtbWluZwo+Pj4+Pj4+IGluIHNlY3VyZSBtb2Rl IGFuZCBub24tc2VjdXJlIG1vZGUuCj4+Pj4+Pj4KPj4+Pj4+PiBTaWduZWQtb2ZmLWJ5OiBTb3dq YW55YSBLb21hdGluZW5pIDxza29tYXRpbmVuaUBudmlkaWEuY29tPgo+Pj4+Pj4+IC0tLQo+Pj4+ PiBbc25pcF0KPj4+Pj4KPj4+Pj4+PiArCj4+Pj4+Pj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgY2xr X29wcyBwbWNfY2xrX2dhdGVfb3BzID0gewo+Pj4+Pj4+ICvCoMKgwqAgLmlzX2VuYWJsZWQgPSBw bWNfY2xrX2lzX2VuYWJsZWQsCj4+Pj4+Pj4gK8KgwqDCoCAuZW5hYmxlID0gcG1jX2Nsa19lbmFi bGUsCj4+Pj4+Pj4gK8KgwqDCoCAuZGlzYWJsZSA9IHBtY19jbGtfZGlzYWJsZSwKPj4+Pj4+PiAr fTsKPj4+Pj4+IFdoYXQncyB0aGUgYmVuZWZpdCBvZiBzZXBhcmF0aW5nIEdBVEUgZnJvbSB0aGUg TVVYPwo+Pj4+Pj4KPj4+Pj4+IEkgdGhpbmsgaXQgY291bGQgYmUgYSBzaW5nbGUgY2xvY2suCj4+ Pj4+IEFjY29yZGluZyB0byBUUk06Cj4+Pj4+Cj4+Pj4+IDEuIEdBVEUgYW5kIE1VWCBhcmUgc2Vw YXJhdGUgZW50aXRpZXMuCj4+Pj4+Cj4+Pj4+IDIuIEdBVEUgaXMgdGhlIHBhcmVudCBvZiBNVVgg KHNlZSBQTUMncyBDTEtfT1VUIHBhdGhzIGRpYWdyYW0gaW4gVFJNKS4KPj4+Pj4KPj4+Pj4gMy4g UE1DIGRvZXNuJ3QgZ2F0ZSBFWFRQRVJJUEggY2xvY2sgYnV0IGNvdWxkICJmb3JjZS1lbmFibGUi IGl0LAo+Pj4+PiBjb3JyZWN0Pwo+IAo+IFdhcyBmb2xsb3dpbmcgZXhpc3RpbmcgY2xrLXRlZ3Jh LXBtYyBhcyBJIGFtIG5vdCBzdXJlIG9mIHJlYXNvbiBmb3IKPiBoYXZpbmcgdGhlc2UgY2xvY2tz IHJlZ2lzdGVyZWQgYXMgc2VwYXJhdGUgbXV4IGFuZCBnYXRlIGNsb2Nrcy4KPiAKPiBZZXMsIFBN QyBjbG9ja3MgY2FuIGJlIHJlZ2lzdGVyZWQgYXMgc2luZ2xlIGNsb2NrIGFuZCBjYW4gdXNlIGNs a19vcHMKPiBmb3Igc2V0L2dldCBwYXJlbnQgYW5kIGVuYWJsZS9kaXNhYmxlLgo+IAo+IGVuYWJs ZS9kaXNhYmxlIG9mIFBNQyBjbG9ja3MgaXMgZm9yIGZvcmNlLWVuYWJsZSB0byBmb3JjZSB0aGUg Y2xvY2sgdG8KPiBydW4gcmVnYXJkbGVzcyBvZiBBQ0NFUFRfUkVRIG9yIElOVkVSVF9SRVEuCj4g Cj4+Pj4gNC4gY2xrX21fZGl2Mi80IGFyZSBpbnRlcm5hbCBQTUMgT1NDIGRpdmlkZXJzIGFuZCB0 aHVzIHRoZXNlIGNsb2Nrcwo+Pj4+IHNob3VsZCBiZWxvbmcgdG8gUE1DLgo+Pj4gQWxzbywgaXQg c2hvdWxkIGJlICJvc2MiIGFuZCBub3QgImNsa19tIi4KPj4KPj4gSSBmb2xsb3dlZCB0aGUgc2Ft ZSBwYXJlbnRzIGFzIGl0IHdlcmUgaW4gZXhpc3RpbmcgY2xrLXRlZ3JhLXBtYyBkcml2ZXIuCj4+ Cj4+IFllYWggdGhleSBhcmUgd3JvbmcgYW5kIHRoZXkgc2hvdWxkIGJlIGZyb20gb3NjIGFuZCBu b3QgY2xrX20uCj4+Cj4+IFdpbGwgZml4IGluIG5leHQgdmVyc2lvbi4KPj4KCkNvdWxkIHlvdSBw bGVhc2UgZGVzY3JpYmUgdGhlIGZ1bGwgRVhUUEVSSVBIIGNsb2NrIHRvcG9sb2d5IGFuZCBob3cg dGhlCnBpbm11eCBjb25maWd1cmF0aW9uIGlzIHJlbGF0ZWQgdG8gaXQgYWxsPwoKV2hhdCBpcyBp bnRlcm5hbCB0byB0aGUgVGVncmEgY2hpcCBhbmQgd2hhdCBhcmUgdGhlIGV4dGVybmFsIG91dHB1 dHM/CgpJcyBpdCBwb3NzaWJsZSB0byBieXBhc3MgUE1DIG9uIFQzMCsgZm9yIHRoZSBFWFRQRVJJ UEggY2xvY2tzPwpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f XwpBbHNhLWRldmVsIG1haWxpbmcgbGlzdApBbHNhLWRldmVsQGFsc2EtcHJvamVjdC5vcmcKaHR0 cHM6Ly9tYWlsbWFuLmFsc2EtcHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbHNhLWRldmVs Cg==