From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752899AbeDPJvM (ORCPT ); Mon, 16 Apr 2018 05:51:12 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:32979 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750795AbeDPJvJ (ORCPT ); Mon, 16 Apr 2018 05:51:09 -0400 DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20180416095106euoutp02f884b1070da7873bd262fb4a77488612~l4cC7G5Fq1471114711euoutp02k X-AuditID: cbfec7f5-b5fff700000028a9-e8-5ad47209bcc5 Subject: Re: [PATCH v6 29/30] drm/rockchip: Disallow PSR for the whole atomic commit To: Enric Balletbo i Serra , architt@codeaurora.org, inki.dae@samsung.com, thierry.reding@gmail.com, hjc@rock-chips.com, seanpaul@chromium.org, airlied@linux.ie, tfiga@chromium.org, heiko@sntech.de Cc: dri-devel@lists.freedesktop.org, dianders@chromium.org, ykk@rock-chips.com, kernel@collabora.com, m.szyprowski@samsung.com, linux-samsung-soc@vger.kernel.org, jy0922.shim@samsung.com, rydberg@bitmath.org, krzk@kernel.org, linux-rockchip@lists.infradead.org, kgene@kernel.org, linux-input@vger.kernel.org, orjan.eide@arm.com, wxt@rock-chips.com, jeffy.chen@rock-chips.com, linux-arm-kernel@lists.infradead.org, mark.yao@rock-chips.com, wzz@rock-chips.com, hl@rock-chips.com, jingoohan1@gmail.com, sw0312.kim@samsung.com, linux-kernel@vger.kernel.org, kyungmin.park@samsung.com, Laurent.pinchart@ideasonboard.com, kuankuan.y@gmail.com, hshi@chromium.org, "Kristian H . Kristensen" From: Andrzej Hajda Message-ID: Date: Mon, 16 Apr 2018 11:51:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180405095000.9756-30-enric.balletbo@collabora.com> Content-Transfer-Encoding: 8bit Content-Language: en-US X-Brightmail-Tracker: H4sIAAAAAAAAA02Ta2yTZRTH87z3LhZeCronhQytMwEMw0WSHUQJGkneD5oYPxhSE6W6lw1Z x2zZZDqhdu6KmziIrt0FYraONDM03QZd1ZW1QAe1LU1xbJCuA5bsRhXYjTq3ufaFuG+/c/7/ k+d/TvJwpGKcUXIH8g+LunxNnopJoc5fiQe2ynQ31K+cmtkANYGrBBgrYzT4Lb0M3Jj5m4H2 224ES3cnaWiq+xoe266RMDxqYaGi8y4BddETFMwN+Bk4O21iYWwoREFH4Dsavr83SUIwaGPh ustHgN94n4WqH1pYsN/rp2Hw0SwNYWcjA4+Gl0ioD/YQ8MulCAuOUxcJ6OnwUNA3+yMBEZsf Qf3JcQamyhYZiDubKagotRBQfvM5CBhOsrvThfbmdiRMWSdoocEQooRwbQ0hOCItSOg2R1ih odJEC3ZrFSNcmB2mhehxLyF0tBwTFswuSqjttCLhQn8zKUzZ095brU55PVvMO1Ak6rbt2peS aygrKuhKP+IMe1kDmk6rRhyH+e24rDOrGqVwCv4swqOeCJKKaYRLe1sZqZhCuNd0hahGsuTE xQezSVbwbQh/G39HMsUQLg+20glhLf8B/rXvGzohrOPHEbZdniQSBckP0njo97HkOMNvxgsd g0yC5fwuPB6wJacp/iUcNPqS/Cy/FxtH46zkWYOvmkaoBMv4t3B3W22yT/IbcWlXAylxKr41 cvpJVI8MT7Tvkfht3PeHj5R4LZ7wdrISb8BL3U/9X+HBMSOVCIr5SoSj8xWMJOzEHm+ITlyM XA59zrlNar+B/dEKQjrkKjwQWyNFWIXrzv9ESm05rixXSO4XcNTf9SRBKm69PsOcQC+aVyxm XrGMecUy5v/fPYMoK0oVC/XaHFH/ar74RYZeo9UX5udkfHpIa0fLH8C36J1xoJ5/P3EjnkOq Z+QOf1itoDVF+mKtG2GOVK2TWzTLLXm2pvhLUXfoY11hnqh3o/UcpUqVf7TpqFrB52gOiwdF sUDUPVUJTqY0oJv1Je9qL98JV40OTC7c7jeVtJ3OS3++vnhjKGO3pXEp1Ni0+ejxDPWicu7P W8eUrPX9lzPb+rJcn+3v8sjuP8ZpWwt+m3+N46/ZC8/842JyspQ7dn6+/eHD6aZL+2Il8T3r FfNitvvBnHPoTsPeD1e/GcvdcSTTGPONlB50/OWq+blJRelzNZlbSJ1e8x9iKvjP/AMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTZxSH897P4tZ4LSjvcPGjdtGZrFoQOagjRhNzE/3DxDmV6fQGboBI qbu3EFlmbDCKVkERg21RnJFVVzF2LQ4oCWJnRIZt7WBoJUWiRlfxYwFEjHyMAkv47znnd56T 902OglSN0QmKnDyjKOUJuWpmBtU22hL+SiF1pC8/P/AZlPhbCSg6+poGn/0WAx3v3jJQ0+VF MPakl4bzpw/AkPNPEnpe2Fkorn1CwOnHpyh4/9DHwJUBKwv/dAcpcPtP0HDyaS8JgYCThfs3 2wjwFb1i4VhZNQuup500hPoGaWj3nGOgr2eMBEugiYBrt8Ms1J9pJqDJ/QcFdwcrCAg7fQgs 5REG+g+PMvDBU0VB8SE7AUcezAG/qZxdq+FrqmoQ3+94SfOVpiDFt5eWEHx9uBrxDbYwy1ce tdK8y3GM4esGe2j+8fEWgndXH+RHbDcpvrTWgfi6ziqS73fN2zwzXbtGMuQbxQXZBtn4tfo7 HSRqdamgTVyRqtUlpexalZisXpa2JlPMzSkQpWVpe7TZpsMF+25o9nvaW1gTGphnRjEKzK3A zf8OEmY0Q6HifkHYeifITgbxuPHCa3KSY/Fwp5mZHOpF+G3wEhENYrlvceWb4xNBHBdBuLXk JRstSC5E4y6Hc2rvPYQ7Ht6mowrDfYlH3CEmykouDUf8zok+xX2BA0VtEzyb2467A31TM7Nw q/UZFeUYbh1uuFw68T6SW4yHq/4iJ3k+PnSjcorj8aNnF4hTSGWbptumKbZpim2a8jOiHChO zJf1WXo5USsLejk/L0ubYdC70Pjx/X7nQ209Mr/Z4kWcAqk/Vdb72tNVtFAgF+q9CCtIdZzS Loy3lJlC4Y+iZNgt5eeKshclj3+ujEyYnWEYP+U8425dsi4FUnUpSSlJK0EdrwwsL0xXcVmC UdwrivtE6X+PUMQkmND6uthbmx5kLLHe1dTxV39ofCRtHnFtu/j50JCQE2kK/WSZ6wlUXOyz X47dYPWsjny82uAWKrrgTNkey/rmwPagrtiPrd8X2JceHN26kf17vyb1k7M73ucI15Fl5zfv nsOv8RH7nF0dvy3IfDW8clWtt7PcvKhR46/oXnhgr3+LNaSm5GxBt5SUZOE/Pewz+5IDAAA= X-CMS-MailID: 20180416095104eucas1p1a4a4f1cbd39804702412b0dceff083a6 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-MTR: 20180416095104eucas1p1a4a4f1cbd39804702412b0dceff083a6 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180405095119epcas5p1964fcfc777686af4216a7ff6acd964ce X-RootMTR: 20180405095119epcas5p1964fcfc777686af4216a7ff6acd964ce References: <20180405095000.9756-1-enric.balletbo@collabora.com> <20180405095000.9756-30-enric.balletbo@collabora.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05.04.2018 11:49, Enric Balletbo i Serra wrote: > From: Tomasz Figa > > Currently PSR flush is triggered from CRTC's .atomic_begin() callback, > which is executed after modeset disables and enables and before plane > updates are committed. Since PSR flush and re-enable can be triggered > asynchronously by external sources (input event, delayed work), it can > race with hardware programming done in the aforementioned stages. > > This patch blocks the PSR completely before hardware programming part > begins and unblock after it ends. This relies on reference counted PSR > disable introduced with previous patch. > > Cc: Kristian H. Kristensen > Signed-off-by: Tomasz Figa > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > --- > > drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 61 ++++++++++++++++++++++++++++- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 ---- > 2 files changed, 60 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c > index e266539e04e5..d4f4118b482d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c > @@ -167,8 +167,67 @@ rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, > return ERR_PTR(ret); > } > > +static void > +rockchip_drm_psr_inhibit_get_state(struct drm_atomic_state *state) > +{ > + struct drm_crtc *crtc; > + struct drm_crtc_state *crtc_state; > + struct drm_encoder *encoder; > + u32 encoder_mask = 0; > + int i; > + > + for_each_old_crtc_in_state(state, crtc, crtc_state, i) { > + encoder_mask |= crtc_state->encoder_mask; > + encoder_mask |= crtc->state->encoder_mask; Looks clever and cryptic. More readable would be with for_each_oldnew_crtc_in_state. Anyway: Reviewed-by: Andrzej Hajda  -- Regards Andrzej > + } > + > + drm_for_each_encoder_mask(encoder, state->dev, encoder_mask) > + rockchip_drm_psr_inhibit_get(encoder); > +} > + > +static void > +rockchip_drm_psr_inhibit_put_state(struct drm_atomic_state *state) > +{ > + struct drm_crtc *crtc; > + struct drm_crtc_state *crtc_state; > + struct drm_encoder *encoder; > + u32 encoder_mask = 0; > + int i; > + > + for_each_old_crtc_in_state(state, crtc, crtc_state, i) { > + encoder_mask |= crtc_state->encoder_mask; > + encoder_mask |= crtc->state->encoder_mask; > + } > + > + drm_for_each_encoder_mask(encoder, state->dev, encoder_mask) > + rockchip_drm_psr_inhibit_put(encoder); > +} > + > +static void > +rockchip_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state) > +{ > + struct drm_device *dev = old_state->dev; > + > + rockchip_drm_psr_inhibit_get_state(old_state); > + > + drm_atomic_helper_commit_modeset_disables(dev, old_state); > + > + drm_atomic_helper_commit_modeset_enables(dev, old_state); > + > + drm_atomic_helper_commit_planes(dev, old_state, > + DRM_PLANE_COMMIT_ACTIVE_ONLY); > + > + rockchip_drm_psr_inhibit_put_state(old_state); > + > + drm_atomic_helper_commit_hw_done(old_state); > + > + drm_atomic_helper_wait_for_vblanks(dev, old_state); > + > + drm_atomic_helper_cleanup_planes(dev, old_state); > +} > + > static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = { > - .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, > + .atomic_commit_tail = rockchip_atomic_helper_commit_tail_rpm, > }; > > static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = { > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index 00f7f3441cf6..f14a10ca4792 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -1029,16 +1029,9 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, > } > } > > -static void vop_crtc_atomic_begin(struct drm_crtc *crtc, > - struct drm_crtc_state *old_crtc_state) > -{ > - rockchip_drm_psr_flush(crtc); > -} > - > static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { > .mode_fixup = vop_crtc_mode_fixup, > .atomic_flush = vop_crtc_atomic_flush, > - .atomic_begin = vop_crtc_atomic_begin, > .atomic_enable = vop_crtc_atomic_enable, > .atomic_disable = vop_crtc_atomic_disable, > }; From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrzej Hajda Subject: Re: [PATCH v6 29/30] drm/rockchip: Disallow PSR for the whole atomic commit Date: Mon, 16 Apr 2018 11:51:01 +0200 Message-ID: References: <20180405095000.9756-1-enric.balletbo@collabora.com> <20180405095000.9756-30-enric.balletbo@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20180405095000.9756-30-enric.balletbo@collabora.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Enric Balletbo i Serra , architt@codeaurora.org, inki.dae@samsung.com, thierry.reding@gmail.com, hjc@rock-chips.com, seanpaul@chromium.org, airlied@linux.ie, tfiga@chromium.org, heiko@sntech.de Cc: dri-devel@lists.freedesktop.org, dianders@chromium.org, Laurent.pinchart@ideasonboard.com, ykk@rock-chips.com, "Kristian H . Kristensen" , kernel@collabora.com, m.szyprowski@samsung.com, linux-samsung-soc@vger.kernel.org, rydberg@bitmath.org, krzk@kernel.org, linux-rockchip@lists.infradead.org, kgene@kernel.org, linux-input@vger.kernel.org, orjan.eide@arm.com, wxt@rock-chips.com, jeffy.chen@rock-chips.com, linux-arm-kernel@lists.infradead.org, mark.yao@rock-chips.com, wzz@rock-chips.com, hl@rock-chips.com, jingoohan1@gmail.com, sw0312.kim@samsung.com, linux-kernel@vger.kernel.org, kyungmin.park@samsung.com, kuankuan.y@gmail.com, hshi@chromium.org List-Id: linux-input@vger.kernel.org T24gMDUuMDQuMjAxOCAxMTo0OSwgRW5yaWMgQmFsbGV0Ym8gaSBTZXJyYSB3cm90ZToKPiBGcm9t OiBUb21hc3ogRmlnYSA8dGZpZ2FAY2hyb21pdW0ub3JnPgo+Cj4gQ3VycmVudGx5IFBTUiBmbHVz aCBpcyB0cmlnZ2VyZWQgZnJvbSBDUlRDJ3MgLmF0b21pY19iZWdpbigpIGNhbGxiYWNrLAo+IHdo aWNoIGlzIGV4ZWN1dGVkIGFmdGVyIG1vZGVzZXQgZGlzYWJsZXMgYW5kIGVuYWJsZXMgYW5kIGJl Zm9yZSBwbGFuZQo+IHVwZGF0ZXMgYXJlIGNvbW1pdHRlZC4gU2luY2UgUFNSIGZsdXNoIGFuZCBy ZS1lbmFibGUgY2FuIGJlIHRyaWdnZXJlZAo+IGFzeW5jaHJvbm91c2x5IGJ5IGV4dGVybmFsIHNv dXJjZXMgKGlucHV0IGV2ZW50LCBkZWxheWVkIHdvcmspLCBpdCBjYW4KPiByYWNlIHdpdGggaGFy ZHdhcmUgcHJvZ3JhbW1pbmcgZG9uZSBpbiB0aGUgYWZvcmVtZW50aW9uZWQgc3RhZ2VzLgo+Cj4g VGhpcyBwYXRjaCBibG9ja3MgdGhlIFBTUiBjb21wbGV0ZWx5IGJlZm9yZSBoYXJkd2FyZSBwcm9n cmFtbWluZyBwYXJ0Cj4gYmVnaW5zIGFuZCB1bmJsb2NrIGFmdGVyIGl0IGVuZHMuIFRoaXMgcmVs aWVzIG9uIHJlZmVyZW5jZSBjb3VudGVkIFBTUgo+IGRpc2FibGUgaW50cm9kdWNlZCB3aXRoIHBy ZXZpb3VzIHBhdGNoLgo+Cj4gQ2M6IEtyaXN0aWFuIEguIEtyaXN0ZW5zZW4gPGhvZWdzYmVyZ0Bj aHJvbWl1bS5vcmc+Cj4gU2lnbmVkLW9mZi1ieTogVG9tYXN6IEZpZ2EgPHRmaWdhQGNocm9taXVt Lm9yZz4KPiBTaWduZWQtb2ZmLWJ5OiBTZWFuIFBhdWwgPHNlYW5wYXVsQGNocm9taXVtLm9yZz4K PiBTaWduZWQtb2ZmLWJ5OiBUaGllcnJ5IEVzY2FuZGUgPHRoaWVycnkuZXNjYW5kZUBjb2xsYWJv cmEuY29tPgo+IFNpZ25lZC1vZmYtYnk6IEVucmljIEJhbGxldGJvIGkgU2VycmEgPGVucmljLmJh bGxldGJvQGNvbGxhYm9yYS5jb20+Cj4gVGVzdGVkLWJ5OiBNYXJlayBTenlwcm93c2tpIDxtLnN6 eXByb3dza2lAc2Ftc3VuZy5jb20+Cj4gLS0tCj4KPiAgZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlw L3JvY2tjaGlwX2RybV9mYi5jICB8IDYxICsrKysrKysrKysrKysrKysrKysrKysrKysrKystCj4g IGRyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmMgfCAgNyAtLS0tCj4g IDIgZmlsZXMgY2hhbmdlZCwgNjAgaW5zZXJ0aW9ucygrKSwgOCBkZWxldGlvbnMoLSkKPgo+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX2ZiLmMgYi9k cml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX2ZiLmMKPiBpbmRleCBlMjY2NTM5 ZTA0ZTUuLmQ0ZjQxMThiNDgyZCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2No aXAvcm9ja2NoaXBfZHJtX2ZiLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9j a2NoaXBfZHJtX2ZiLmMKPiBAQCAtMTY3LDggKzE2Nyw2NyBAQCByb2NrY2hpcF91c2VyX2ZiX2Ny ZWF0ZShzdHJ1Y3QgZHJtX2RldmljZSAqZGV2LCBzdHJ1Y3QgZHJtX2ZpbGUgKmZpbGVfcHJpdiwK PiAgCXJldHVybiBFUlJfUFRSKHJldCk7Cj4gIH0KPiAgCj4gK3N0YXRpYyB2b2lkCj4gK3JvY2tj aGlwX2RybV9wc3JfaW5oaWJpdF9nZXRfc3RhdGUoc3RydWN0IGRybV9hdG9taWNfc3RhdGUgKnN0 YXRlKQo+ICt7Cj4gKwlzdHJ1Y3QgZHJtX2NydGMgKmNydGM7Cj4gKwlzdHJ1Y3QgZHJtX2NydGNf c3RhdGUgKmNydGNfc3RhdGU7Cj4gKwlzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXI7Cj4gKwl1 MzIgZW5jb2Rlcl9tYXNrID0gMDsKPiArCWludCBpOwo+ICsKPiArCWZvcl9lYWNoX29sZF9jcnRj X2luX3N0YXRlKHN0YXRlLCBjcnRjLCBjcnRjX3N0YXRlLCBpKSB7Cj4gKwkJZW5jb2Rlcl9tYXNr IHw9IGNydGNfc3RhdGUtPmVuY29kZXJfbWFzazsKPiArCQllbmNvZGVyX21hc2sgfD0gY3J0Yy0+ c3RhdGUtPmVuY29kZXJfbWFzazsKCkxvb2tzIGNsZXZlciBhbmQgY3J5cHRpYy4gTW9yZSByZWFk YWJsZSB3b3VsZCBiZSB3aXRoCmZvcl9lYWNoX29sZG5ld19jcnRjX2luX3N0YXRlLgpBbnl3YXk6 ClJldmlld2VkLWJ5OiBBbmRyemVqIEhhamRhIDxhLmhhamRhQHNhbXN1bmcuY29tPgoKwqAtLQpS ZWdhcmRzCkFuZHJ6ZWoKCj4gKwl9Cj4gKwo+ICsJZHJtX2Zvcl9lYWNoX2VuY29kZXJfbWFzayhl bmNvZGVyLCBzdGF0ZS0+ZGV2LCBlbmNvZGVyX21hc2spCj4gKwkJcm9ja2NoaXBfZHJtX3Bzcl9p bmhpYml0X2dldChlbmNvZGVyKTsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQKPiArcm9ja2NoaXBf ZHJtX3Bzcl9pbmhpYml0X3B1dF9zdGF0ZShzdHJ1Y3QgZHJtX2F0b21pY19zdGF0ZSAqc3RhdGUp Cj4gK3sKPiArCXN0cnVjdCBkcm1fY3J0YyAqY3J0YzsKPiArCXN0cnVjdCBkcm1fY3J0Y19zdGF0 ZSAqY3J0Y19zdGF0ZTsKPiArCXN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlcjsKPiArCXUzMiBl bmNvZGVyX21hc2sgPSAwOwo+ICsJaW50IGk7Cj4gKwo+ICsJZm9yX2VhY2hfb2xkX2NydGNfaW5f c3RhdGUoc3RhdGUsIGNydGMsIGNydGNfc3RhdGUsIGkpIHsKPiArCQllbmNvZGVyX21hc2sgfD0g Y3J0Y19zdGF0ZS0+ZW5jb2Rlcl9tYXNrOwo+ICsJCWVuY29kZXJfbWFzayB8PSBjcnRjLT5zdGF0 ZS0+ZW5jb2Rlcl9tYXNrOwo+ICsJfQo+ICsKPiArCWRybV9mb3JfZWFjaF9lbmNvZGVyX21hc2so ZW5jb2Rlciwgc3RhdGUtPmRldiwgZW5jb2Rlcl9tYXNrKQo+ICsJCXJvY2tjaGlwX2RybV9wc3Jf aW5oaWJpdF9wdXQoZW5jb2Rlcik7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkCj4gK3JvY2tjaGlw X2F0b21pY19oZWxwZXJfY29tbWl0X3RhaWxfcnBtKHN0cnVjdCBkcm1fYXRvbWljX3N0YXRlICpv bGRfc3RhdGUpCj4gK3sKPiArCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBvbGRfc3RhdGUtPmRl djsKPiArCj4gKwlyb2NrY2hpcF9kcm1fcHNyX2luaGliaXRfZ2V0X3N0YXRlKG9sZF9zdGF0ZSk7 Cj4gKwo+ICsJZHJtX2F0b21pY19oZWxwZXJfY29tbWl0X21vZGVzZXRfZGlzYWJsZXMoZGV2LCBv bGRfc3RhdGUpOwo+ICsKPiArCWRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9tb2Rlc2V0X2VuYWJs ZXMoZGV2LCBvbGRfc3RhdGUpOwo+ICsKPiArCWRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9wbGFu ZXMoZGV2LCBvbGRfc3RhdGUsCj4gKwkJCQkJRFJNX1BMQU5FX0NPTU1JVF9BQ1RJVkVfT05MWSk7 Cj4gKwo+ICsJcm9ja2NoaXBfZHJtX3Bzcl9pbmhpYml0X3B1dF9zdGF0ZShvbGRfc3RhdGUpOwo+ ICsKPiArCWRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9od19kb25lKG9sZF9zdGF0ZSk7Cj4gKwo+ ICsJZHJtX2F0b21pY19oZWxwZXJfd2FpdF9mb3JfdmJsYW5rcyhkZXYsIG9sZF9zdGF0ZSk7Cj4g Kwo+ICsJZHJtX2F0b21pY19oZWxwZXJfY2xlYW51cF9wbGFuZXMoZGV2LCBvbGRfc3RhdGUpOwo+ ICt9Cj4gKwo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9tb2RlX2NvbmZpZ19oZWxwZXJfZnVu Y3Mgcm9ja2NoaXBfbW9kZV9jb25maWdfaGVscGVycyA9IHsKPiAtCS5hdG9taWNfY29tbWl0X3Rh aWwgPSBkcm1fYXRvbWljX2hlbHBlcl9jb21taXRfdGFpbF9ycG0sCj4gKwkuYXRvbWljX2NvbW1p dF90YWlsID0gcm9ja2NoaXBfYXRvbWljX2hlbHBlcl9jb21taXRfdGFpbF9ycG0sCj4gIH07Cj4g IAo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9tb2RlX2NvbmZpZ19mdW5jcyByb2NrY2hpcF9k cm1fbW9kZV9jb25maWdfZnVuY3MgPSB7Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9y b2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9j a2NoaXBfZHJtX3ZvcC5jCj4gaW5kZXggMDBmN2YzNDQxY2Y2Li5mMTRhMTBjYTQ3OTIgMTAwNjQ0 Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV92b3AuYwo+ICsr KyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmMKPiBAQCAtMTAy OSwxNiArMTAyOSw5IEBAIHN0YXRpYyB2b2lkIHZvcF9jcnRjX2F0b21pY19mbHVzaChzdHJ1Y3Qg ZHJtX2NydGMgKmNydGMsCj4gIAl9Cj4gIH0KPiAgCj4gLXN0YXRpYyB2b2lkIHZvcF9jcnRjX2F0 b21pY19iZWdpbihzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCj4gLQkJCQkgIHN0cnVjdCBkcm1fY3J0 Y19zdGF0ZSAqb2xkX2NydGNfc3RhdGUpCj4gLXsKPiAtCXJvY2tjaGlwX2RybV9wc3JfZmx1c2go Y3J0Yyk7Cj4gLX0KPiAtCj4gIHN0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX2NydGNfaGVscGVyX2Z1 bmNzIHZvcF9jcnRjX2hlbHBlcl9mdW5jcyA9IHsKPiAgCS5tb2RlX2ZpeHVwID0gdm9wX2NydGNf bW9kZV9maXh1cCwKPiAgCS5hdG9taWNfZmx1c2ggPSB2b3BfY3J0Y19hdG9taWNfZmx1c2gsCj4g LQkuYXRvbWljX2JlZ2luID0gdm9wX2NydGNfYXRvbWljX2JlZ2luLAo+ICAJLmF0b21pY19lbmFi bGUgPSB2b3BfY3J0Y19hdG9taWNfZW5hYmxlLAo+ICAJLmF0b21pY19kaXNhYmxlID0gdm9wX2Ny dGNfYXRvbWljX2Rpc2FibGUsCj4gIH07CgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMu ZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: a.hajda@samsung.com (Andrzej Hajda) Date: Mon, 16 Apr 2018 11:51:01 +0200 Subject: [PATCH v6 29/30] drm/rockchip: Disallow PSR for the whole atomic commit In-Reply-To: <20180405095000.9756-30-enric.balletbo@collabora.com> References: <20180405095000.9756-1-enric.balletbo@collabora.com> <20180405095000.9756-30-enric.balletbo@collabora.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 05.04.2018 11:49, Enric Balletbo i Serra wrote: > From: Tomasz Figa > > Currently PSR flush is triggered from CRTC's .atomic_begin() callback, > which is executed after modeset disables and enables and before plane > updates are committed. Since PSR flush and re-enable can be triggered > asynchronously by external sources (input event, delayed work), it can > race with hardware programming done in the aforementioned stages. > > This patch blocks the PSR completely before hardware programming part > begins and unblock after it ends. This relies on reference counted PSR > disable introduced with previous patch. > > Cc: Kristian H. Kristensen > Signed-off-by: Tomasz Figa > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > --- > > drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 61 ++++++++++++++++++++++++++++- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 ---- > 2 files changed, 60 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c > index e266539e04e5..d4f4118b482d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c > @@ -167,8 +167,67 @@ rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, > return ERR_PTR(ret); > } > > +static void > +rockchip_drm_psr_inhibit_get_state(struct drm_atomic_state *state) > +{ > + struct drm_crtc *crtc; > + struct drm_crtc_state *crtc_state; > + struct drm_encoder *encoder; > + u32 encoder_mask = 0; > + int i; > + > + for_each_old_crtc_in_state(state, crtc, crtc_state, i) { > + encoder_mask |= crtc_state->encoder_mask; > + encoder_mask |= crtc->state->encoder_mask; Looks clever and cryptic. More readable would be with for_each_oldnew_crtc_in_state. Anyway: Reviewed-by: Andrzej Hajda ?-- Regards Andrzej > + } > + > + drm_for_each_encoder_mask(encoder, state->dev, encoder_mask) > + rockchip_drm_psr_inhibit_get(encoder); > +} > + > +static void > +rockchip_drm_psr_inhibit_put_state(struct drm_atomic_state *state) > +{ > + struct drm_crtc *crtc; > + struct drm_crtc_state *crtc_state; > + struct drm_encoder *encoder; > + u32 encoder_mask = 0; > + int i; > + > + for_each_old_crtc_in_state(state, crtc, crtc_state, i) { > + encoder_mask |= crtc_state->encoder_mask; > + encoder_mask |= crtc->state->encoder_mask; > + } > + > + drm_for_each_encoder_mask(encoder, state->dev, encoder_mask) > + rockchip_drm_psr_inhibit_put(encoder); > +} > + > +static void > +rockchip_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state) > +{ > + struct drm_device *dev = old_state->dev; > + > + rockchip_drm_psr_inhibit_get_state(old_state); > + > + drm_atomic_helper_commit_modeset_disables(dev, old_state); > + > + drm_atomic_helper_commit_modeset_enables(dev, old_state); > + > + drm_atomic_helper_commit_planes(dev, old_state, > + DRM_PLANE_COMMIT_ACTIVE_ONLY); > + > + rockchip_drm_psr_inhibit_put_state(old_state); > + > + drm_atomic_helper_commit_hw_done(old_state); > + > + drm_atomic_helper_wait_for_vblanks(dev, old_state); > + > + drm_atomic_helper_cleanup_planes(dev, old_state); > +} > + > static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = { > - .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, > + .atomic_commit_tail = rockchip_atomic_helper_commit_tail_rpm, > }; > > static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = { > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index 00f7f3441cf6..f14a10ca4792 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -1029,16 +1029,9 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, > } > } > > -static void vop_crtc_atomic_begin(struct drm_crtc *crtc, > - struct drm_crtc_state *old_crtc_state) > -{ > - rockchip_drm_psr_flush(crtc); > -} > - > static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { > .mode_fixup = vop_crtc_mode_fixup, > .atomic_flush = vop_crtc_atomic_flush, > - .atomic_begin = vop_crtc_atomic_begin, > .atomic_enable = vop_crtc_atomic_enable, > .atomic_disable = vop_crtc_atomic_disable, > };