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[142.114.143.47]) by smtp.gmail.com with ESMTPSA id z6sm7758851qke.24.2021.07.06.19.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jul 2021 19:09:00 -0700 (PDT) Message-ID: Subject: Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework From: shashi.mallela@linaro.org To: Peter Maydell Date: Tue, 06 Jul 2021 22:08:59 -0400 In-Reply-To: References: <20210630153156.9421-1-shashi.mallela@linaro.org> <20210630153156.9421-2-shashi.mallela@linaro.org> <916a2c2eb368835dbd17fe0b90be541abbebde93.camel@linaro.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-16.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::72e; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x72e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , Radoslaw Biernacki , QEMU Developers , qemu-arm , Igor Mammedov , Leif Lindholm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, 2021-07-05 at 19:58 +0100, Peter Maydell wrote: > On Mon, 5 Jul 2021 at 18:04, wrote: > > On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote: > > > On Mon, 5 Jul 2021 at 16:55, wrote: > > > > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote: > > > > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela < > > > > > shashi.mallela@linaro.org> wrote: > > > > > > Added register definitions relevant to ITS,implemented > > > > > > overall > > > > > > ITS device framework with stubs for ITS control and > > > > > > translater > > > > > > regions read/write,extended ITS common to handle mmio init > > > > > > between > > > > > > existing kvm device and newer qemu device. > > > > > > > > > > > > Signed-off-by: Shashi Mallela > > > > > > Reviewed-by: Peter Maydell > > > > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error > > > > > > **errp) > > > > > > +{ > > > > > > + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); > > > > > > + > > > > > > + gicv3_its_init_mmio(s, &gicv3_its_control_ops, > > > > > > &gicv3_its_translation_ops); > > > > > > + > > > > > > + if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) { > > > > > > > > > > Can you remind me why we make this check, please? When would > > > > > we > > > > > have created an ITS device but not have a GICv3 with LPI > > > > > support? > > > > This check applies to GIC's physical LPI support only as > > > > against > > > > GIC's > > > > virtual LPI support. > > > > > > Right, but when would we have a GIC with no physical LPI support > > > but an ITS is present ? > > If we only support Direct injection of virtual interrupts (which > > can > > have their own vPEID and the vPE table),then the ITS present could > > havejust virtual LPI support > > This patchset does not support a virtual-LPI-only ITS, though: > it doesn't support virtual LPIs at all. > If you use it with CPUs without physical LPI support , this code will > skip > entirely setting GITS_TYPER and will make reset do nothing, and then > the > rest of the ITS implementation will misbehave. > > I think what we should do is: > * in realize, check every CPU to make sure its redistributor > supports physical LPIs, and return an error from realize if not > * in reset, don't check anything Done > > If we add virtual-LPI-only ITS support later, we can always update > this code appropriately. > > thanks > -- PMM