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From: Sandipan Das <sandipan.das@amd.com>
To: <linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>, <x86@kernel.org>
Cc: <peterz@infradead.org>, <bp@alien8.de>,
	<dave.hansen@linux.intel.com>, <acme@kernel.org>,
	<mark.rutland@arm.com>, <alexander.shishkin@linux.intel.com>,
	<namhyung@kernel.org>, <jolsa@kernel.org>, <tglx@linutronix.de>,
	<mingo@redhat.com>, <pbonzini@redhat.com>, <jmattson@google.com>,
	<like.xu.linux@gmail.com>, <eranian@google.com>,
	<ananth.narayan@amd.com>, <ravi.bangoria@amd.com>,
	<santosh.shukla@amd.com>, <sandipan.das@amd.com>
Subject: [PATCH v2 2/7] x86/msr: Add PerfCntrGlobal* registers
Date: Thu, 21 Apr 2022 11:16:54 +0530	[thread overview]
Message-ID: <cdc0d8f75bd519848731b5c64d924f5a0619a573.1650515382.git.sandipan.das@amd.com> (raw)
In-Reply-To: <cover.1650515382.git.sandipan.das@amd.com>

Add MSR definitions that will be used to enable the new AMD
Performance Monitoring Version 2 (PerfMonV2) features. These
include:

  * Performance Counter Global Control (PerfCntrGlobalCtl)
  * Performance Counter Global Status (PerfCntrGlobalStatus)
  * Performance Counter Global Status Clear (PerfCntrGlobalStatusClr)

The new Performance Counter Global Control and Status MSRs
provide an interface for enabling or disabling multiple
counters at the same time and for testing overflow without
probing the individual registers for each PMC.

The availability of these registers is indicated through the
PerfMonV2 feature bit of CPUID leaf 0x80000022 EAX.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
 arch/x86/include/asm/msr-index.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 9e2e7185fc1d..a040f4af93c9 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -527,6 +527,11 @@
 #define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
 #define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
 
+/* AMD Performance Counter Global Status and Control MSRs */
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
+#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
+
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF			0xc00000e9
 
-- 
2.32.0


  parent reply	other threads:[~2022-04-21  5:48 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-21  5:46 [PATCH v2 0/7] perf/x86/amd/core: Add AMD PerfMonV2 support Sandipan Das
2022-04-21  5:46 ` [PATCH v2 1/7] x86/cpufeatures: Add PerfMonV2 feature bit Sandipan Das
2022-04-21  5:46 ` Sandipan Das [this message]
2022-04-21  5:46 ` [PATCH v2 3/7] perf/x86/amd/core: Detect PerfMonV2 support Sandipan Das
2022-04-21  5:46 ` [PATCH v2 4/7] perf/x86/amd/core: Detect available counters Sandipan Das
2022-04-21  5:46 ` [PATCH v2 5/7] perf/x86/amd/core: Add PerfMonV2 counter control Sandipan Das
2022-04-21  5:46 ` [PATCH v2 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling Sandipan Das
2022-04-21  5:46 ` [PATCH v2 7/7] kvm: x86/cpuid: Fix CPUID leaf 0xA Sandipan Das
2022-04-26  8:15   ` Peter Zijlstra
2022-04-26  8:40     ` Sandipan Das
2022-04-26 11:45       ` Wen Pu
2022-04-26 12:39         ` Peter Zijlstra

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