From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753349AbdLMPQT (ORCPT ); Wed, 13 Dec 2017 10:16:19 -0500 Received: from foss.arm.com ([217.140.101.70]:58770 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752407AbdLMPQQ (ORCPT ); Wed, 13 Dec 2017 10:16:16 -0500 Subject: Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information To: Leo Yan Cc: linux-kernel@vger.kernel.org, Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Dietmar Eggemann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> <20171213145311.GA30463@leoy-ThinkPad-T440> From: Valentin Schneider Message-ID: Date: Wed, 13 Dec 2017 15:16:13 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20171213145311.GA30463@leoy-ThinkPad-T440> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Leo, On 12/13/2017 02:53 PM, Leo Yan wrote: > Hi Valentin, > > On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote: >> The following dt entries are added: >> cpus [0-3] (Cortex A53): >> - capacity-dmips-mhz = <592>; >> >> cpus [4-7] (Cortex A73): >> - capacity-dmips-mhz = <1024>; >> >> Those values were obtained by running dhrystone 2.1 on a >> HiKey960 with the following procedure: >> - Offline all CPUs but CPU0 (A53) >> - Set CPU0 frequency to maximum >> - Run Dhrystone 2.1 for 20 seconds >> >> - Offline all CPUs but CPU4 (A73) >> - set CPU4 frequency to maximum >> - Run Dhrystone 2.1 for 20 seconds >> >> The results are as follows: >> A53: 129633887 loops >> A73: 287034147 loops > Seems to me the capacity-dmips-mhz should be: > > CA53: 129633887 / 20 / 1844 = 3515 > CA73: 287034147 / 20 / 2362 = 6076 > > After normalized to range [0..1024], we could get: > > CA53: 592 > CA73: 1024 Yes, that's the "direct approach". I wanted to underline the fact that there are two different max frequencies so what I followed would be: 1) Computing the performance ratio: (129633887 / 287034147) * 1024 = 462.47 2) Scaling that to the same frequency scale: 462.47 * (2362/1844) = 592.38 Which gives the same end result (it's the same equation but split in two steps). Also it makes it easy to check that the cpu_capacity sysfs entry for the A53s gets correctly set (to 462). > > Reviewed-by: Leo Yan > >> By scaling those values so that the A73s use 1024, we end up with 462 >> for the A53s. However, they have different maximum frequencies: >> 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 >> value to truly represent dmips per MHz, and we end up with 592. >> >> The impact of this change can be verified on HiKey960: >> >> $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq >> 1844000 >> 1844000 >> 1844000 >> 1844000 >> 2362000 >> 2362000 >> 2362000 >> 2362000 >> >> $ cat /sys/devices/system/cpu/cpu*/cpu_capacity >> 462 >> 462 >> 462 >> 462 >> 1024 >> 1024 >> 1024 >> 1024 >> >> Signed-off-by: Valentin Schneider >> --- >> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> index ab0b95b..04a8d28 100644 >> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> @@ -61,6 +61,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu1: cpu@1 { >> @@ -70,6 +71,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu2: cpu@2 { >> @@ -79,6 +81,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu3: cpu@3 { >> @@ -88,6 +91,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu4: cpu@100 { >> @@ -101,6 +105,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu5: cpu@101 { >> @@ -114,6 +119,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu6: cpu@102 { >> @@ -127,6 +133,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu7: cpu@103 { >> @@ -140,6 +147,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> idle-states { >> -- >> 2.7.4 >> From mboxrd@z Thu Jan 1 00:00:00 1970 From: Valentin Schneider Subject: Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information Date: Wed, 13 Dec 2017 15:16:13 +0000 Message-ID: References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> <20171213145311.GA30463@leoy-ThinkPad-T440> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20171213145311.GA30463@leoy-ThinkPad-T440> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Leo Yan Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Dietmar Eggemann , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Hi Leo, On 12/13/2017 02:53 PM, Leo Yan wrote: > Hi Valentin, > > On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote: >> The following dt entries are added: >> cpus [0-3] (Cortex A53): >> - capacity-dmips-mhz = <592>; >> >> cpus [4-7] (Cortex A73): >> - capacity-dmips-mhz = <1024>; >> >> Those values were obtained by running dhrystone 2.1 on a >> HiKey960 with the following procedure: >> - Offline all CPUs but CPU0 (A53) >> - Set CPU0 frequency to maximum >> - Run Dhrystone 2.1 for 20 seconds >> >> - Offline all CPUs but CPU4 (A73) >> - set CPU4 frequency to maximum >> - Run Dhrystone 2.1 for 20 seconds >> >> The results are as follows: >> A53: 129633887 loops >> A73: 287034147 loops > Seems to me the capacity-dmips-mhz should be: > > CA53: 129633887 / 20 / 1844 = 3515 > CA73: 287034147 / 20 / 2362 = 6076 > > After normalized to range [0..1024], we could get: > > CA53: 592 > CA73: 1024 Yes, that's the "direct approach". I wanted to underline the fact that there are two different max frequencies so what I followed would be: 1) Computing the performance ratio: (129633887 / 287034147) * 1024 = 462.47 2) Scaling that to the same frequency scale: 462.47 * (2362/1844) = 592.38 Which gives the same end result (it's the same equation but split in two steps). Also it makes it easy to check that the cpu_capacity sysfs entry for the A53s gets correctly set (to 462). > > Reviewed-by: Leo Yan > >> By scaling those values so that the A73s use 1024, we end up with 462 >> for the A53s. However, they have different maximum frequencies: >> 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 >> value to truly represent dmips per MHz, and we end up with 592. >> >> The impact of this change can be verified on HiKey960: >> >> $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq >> 1844000 >> 1844000 >> 1844000 >> 1844000 >> 2362000 >> 2362000 >> 2362000 >> 2362000 >> >> $ cat /sys/devices/system/cpu/cpu*/cpu_capacity >> 462 >> 462 >> 462 >> 462 >> 1024 >> 1024 >> 1024 >> 1024 >> >> Signed-off-by: Valentin Schneider >> --- >> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> index ab0b95b..04a8d28 100644 >> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> @@ -61,6 +61,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu1: cpu@1 { >> @@ -70,6 +71,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu2: cpu@2 { >> @@ -79,6 +81,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu3: cpu@3 { >> @@ -88,6 +91,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu4: cpu@100 { >> @@ -101,6 +105,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu5: cpu@101 { >> @@ -114,6 +119,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu6: cpu@102 { >> @@ -127,6 +133,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu7: cpu@103 { >> @@ -140,6 +147,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> idle-states { >> -- >> 2.7.4 >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: valentin.schneider@arm.com (Valentin Schneider) Date: Wed, 13 Dec 2017 15:16:13 +0000 Subject: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information In-Reply-To: <20171213145311.GA30463@leoy-ThinkPad-T440> References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> <20171213145311.GA30463@leoy-ThinkPad-T440> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Leo, On 12/13/2017 02:53 PM, Leo Yan wrote: > Hi Valentin, > > On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote: >> The following dt entries are added: >> cpus [0-3] (Cortex A53): >> - capacity-dmips-mhz = <592>; >> >> cpus [4-7] (Cortex A73): >> - capacity-dmips-mhz = <1024>; >> >> Those values were obtained by running dhrystone 2.1 on a >> HiKey960 with the following procedure: >> - Offline all CPUs but CPU0 (A53) >> - Set CPU0 frequency to maximum >> - Run Dhrystone 2.1 for 20 seconds >> >> - Offline all CPUs but CPU4 (A73) >> - set CPU4 frequency to maximum >> - Run Dhrystone 2.1 for 20 seconds >> >> The results are as follows: >> A53: 129633887 loops >> A73: 287034147 loops > Seems to me the capacity-dmips-mhz should be: > > CA53: 129633887 / 20 / 1844 = 3515 > CA73: 287034147 / 20 / 2362 = 6076 > > After normalized to range [0..1024], we could get: > > CA53: 592 > CA73: 1024 Yes, that's the "direct approach". I wanted to underline the fact that there are two different max frequencies so what I followed would be: 1) Computing the performance ratio: (129633887 / 287034147) * 1024 = 462.47 2) Scaling that to the same frequency scale: 462.47 * (2362/1844) = 592.38 Which gives the same end result (it's the same equation but split in two steps). Also it makes it easy to check that the cpu_capacity sysfs entry for the A53s gets correctly set (to 462). > > Reviewed-by: Leo Yan > >> By scaling those values so that the A73s use 1024, we end up with 462 >> for the A53s. However, they have different maximum frequencies: >> 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 >> value to truly represent dmips per MHz, and we end up with 592. >> >> The impact of this change can be verified on HiKey960: >> >> $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq >> 1844000 >> 1844000 >> 1844000 >> 1844000 >> 2362000 >> 2362000 >> 2362000 >> 2362000 >> >> $ cat /sys/devices/system/cpu/cpu*/cpu_capacity >> 462 >> 462 >> 462 >> 462 >> 1024 >> 1024 >> 1024 >> 1024 >> >> Signed-off-by: Valentin Schneider >> --- >> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> index ab0b95b..04a8d28 100644 >> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi >> @@ -61,6 +61,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu1: cpu at 1 { >> @@ -70,6 +71,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu2: cpu at 2 { >> @@ -79,6 +81,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu3: cpu at 3 { >> @@ -88,6 +91,7 @@ >> enable-method = "psci"; >> next-level-cache = <&A53_L2>; >> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; >> + capacity-dmips-mhz = <592>; >> }; >> >> cpu4: cpu at 100 { >> @@ -101,6 +105,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu5: cpu at 101 { >> @@ -114,6 +119,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu6: cpu at 102 { >> @@ -127,6 +133,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> cpu7: cpu at 103 { >> @@ -140,6 +147,7 @@ >> &CPU_SLEEP >> &CLUSTER_SLEEP_1 >> >; >> + capacity-dmips-mhz = <1024>; >> }; >> >> idle-states { >> -- >> 2.7.4 >>