From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cB3Yy-0004ze-0F for qemu-devel@nongnu.org; Sun, 27 Nov 2016 12:48:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cB3Yu-0006AA-Lv for qemu-devel@nongnu.org; Sun, 27 Nov 2016 12:48:28 -0500 Received: from mout.kundenserver.de ([212.227.17.13]:65392) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cB3Yu-00069s-Ba for qemu-devel@nongnu.org; Sun, 27 Nov 2016 12:48:24 -0500 References: <1478899549-21459-1-git-send-email-laurent@vivier.eu> From: Laurent Vivier Message-ID: Date: Sun, 27 Nov 2016 18:48:17 +0100 MIME-Version: 1.0 In-Reply-To: <1478899549-21459-1-git-send-email-laurent@vivier.eu> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v4] target-m68k: add rol/ror/roxl/roxr instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Richard Henderson Le 11/11/2016 à 22:25, Laurent Vivier a écrit : > --- a/target-m68k/translate.c > +++ b/target-m68k/translate.c > +DISAS_INSN(rotate16_im) > +{ > + int left = (insn & 0x100); > + TCGv reg; > + TCGv shift; > + int tmp; > + > + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); > + tmp = (insn >> 9) & 7; > + if (tmp == 0) { > + tmp = 8; > + } > + > + shift = tcg_const_i32(tmp); > + if (insn & 8) { > + rotate(reg, shift, left, 16); > + } else { > + TCGv X = rotate_x(reg, shift, left, 16); > + rotate_x_flags(reg, X, 8); Must be: rotate_x_flags(reg, X, 16); > + tcg_temp_free(X); > + } > + tcg_temp_free(shift); > + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); > + set_cc_op(s, CC_OP_FLAGS); > +} Thanks, Laurent