* [RFC v2 00/15] support subsets of bitmanip extension
@ 2020-12-16 2:01 frank.chang
2020-12-16 2:01 ` frank.chang
` (14 more replies)
0 siblings, 15 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Frank Chang
From: Frank Chang <frank.chang@sifive.com>
This patchset implements RISC-V B-extension draft version Zbb, Zbs and
Zba subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zbb-, Zbs- and Zba-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
Specification:
https://github.com/riscv/riscv-bitmanip
Summary of current proposals for Zb{abcs}:
https://lists.riscv.org/g/tech-bitmanip/topic/summary_of_current_proposals/77924315
The port is available here:
https://github.com/sifive/qemu/tree/rvb-upstream-v2
To test rvb implementation, specify cpu argument with 'x-b=true' to
enable B-extension support.
Changelog:
v2:
* Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
* Remove addwu, subwu and addiwu instructions as they are not longer
exist in latest draft.
* Optimize implementation with cleaner tcg ops.
Frank Chang (3):
target/riscv: rvb: count bits set
target/riscv: rvb: generalized reverse
target/riscv: rvb: generalized or-combine
Kito Cheng (12):
target/riscv: reformat @sh format encoding for B-extension
target/riscv: rvb: count leading/trailing zeros
target/riscv: rvb: logic-with-negate
target/riscv: rvb: pack two words into one register
target/riscv: rvb: min/max instructions
target/riscv: rvb: sign-extend instructions
target/riscv: rvb: single-bit instructions
target/riscv: rvb: shift ones
target/riscv: rvb: rotate (left/right)
target/riscv: rvb: address calculation
target/riscv: rvb: add/sub with postfix zero-extend
target/riscv: rvb: support and turn on B-extension from command line
target/riscv/bitmanip_helper.c | 103 ++++++
target/riscv/cpu.c | 4 +
target/riscv/cpu.h | 2 +
target/riscv/helper.h | 9 +
target/riscv/insn32-64.decode | 33 ++
target/riscv/insn32.decode | 54 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 466 ++++++++++++++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 337 +++++++++++++++++
9 files changed, 1003 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/bitmanip_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 63+ messages in thread
* [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18ca..3823b3ea800 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,7 +22,7 @@
%rs1 15:5
%rd 7:5
-%sh10 20:10
+%sh7 20:7
%csr 20:12
%rm 12:3
%nf 29:3 !function=ex_plus_1
@@ -58,7 +58,7 @@
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
-@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@@ -122,9 +122,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
-slli 00.... ...... ..... 001 ..... 0010011 @sh
-srli 00.... ...... ..... 101 ..... 0010011 @sh
-srai 01.... ...... ..... 101 ..... 0010011 @sh
+slli 00000. ...... ..... 001 ..... 0010011 @sh
+srli 00000. ...... ..... 101 ..... 0010011 @sh
+srai 01000. ...... ..... 101 ..... 0010011 @sh
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18ca..3823b3ea800 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,7 +22,7 @@
%rs1 15:5
%rd 7:5
-%sh10 20:10
+%sh7 20:7
%csr 20:12
%rm 12:3
%nf 29:3 !function=ex_plus_1
@@ -58,7 +58,7 @@
@u .................... ..... ....... &u imm=%imm_u %rd
@j .................... ..... ....... &j imm=%imm_j %rd
-@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
+@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
@@ -122,9 +122,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
-slli 00.... ...... ..... 001 ..... 0010011 @sh
-srli 00.... ...... ..... 101 ..... 0010011 @sh
-srai 01.... ...... ..... 101 ..... 0010011 @sh
+slli 00000. ...... ..... 001 ..... 0010011 @sh
+srli 00000. ...... ..... 101 ..... 0010011 @sh
+srai 01000. ...... ..... 101 ..... 0010011 @sh
add 0000000 ..... ..... 000 ..... 0110011 @r
sub 0100000 ..... ..... 000 ..... 0110011 @r
sll 0000000 ..... ..... 001 ..... 0110011 @r
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
target/riscv/translate.c | 42 ++++++++++++++++++++++
4 files changed, 99 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8157dee8b7c..f4c42720fc7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -86,3 +86,7 @@ fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3823b3ea800..8fe838cf0d0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
&i imm rs1 rd
&j imm rd
&r rd rs1 rs2
+&r2 rd rs1
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -67,7 +68,7 @@
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -592,3 +593,7 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+
+# *** RV32B Standard Extension ***
+clz 011000 000000 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..fb6e16143db
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,47 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_clz);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_ctz);
+}
+
+/* RV64-only instructions */
+#ifdef TARGET_RISCV64
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_clzw);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_ctzw);
+}
+
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 554d52a4be3..398d4502a96 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
#endif
+#ifdef TARGET_RISCV64
+
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
+ tcg_gen_ctzi_i64(ret, ret, 32);
+}
+
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_i64(ret, arg1);
+ tcg_gen_clzi_i64(ret, ret, 64);
+ tcg_gen_subi_i64(ret, ret, 32);
+}
+
+#endif
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -747,6 +764,30 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+ void(*func)(TCGv, TCGv))
+{
+ TCGv source = tcg_temp_new();
+
+ gen_get_gpr(source, a->rs1);
+
+ (*func)(source, source);
+
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.c.inc"
@@ -755,6 +796,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rvd.c.inc"
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 4 +++
target/riscv/insn32.decode | 7 +++-
target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
target/riscv/translate.c | 42 ++++++++++++++++++++++
4 files changed, 99 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8157dee8b7c..f4c42720fc7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -86,3 +86,7 @@ fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
+
+# *** RV64B Standard Extension (in addition to RV32B) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3823b3ea800..8fe838cf0d0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -40,6 +40,7 @@
&i imm rs1 rd
&j imm rd
&r rd rs1 rs2
+&r2 rd rs1
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -67,7 +68,7 @@
@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
-@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@@ -592,3 +593,7 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+
+# *** RV32B Standard Extension ***
+clz 011000 000000 ..... 001 ..... 0010011 @r2
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
new file mode 100644
index 00000000000..fb6e16143db
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -0,0 +1,47 @@
+/*
+ * RISC-V translation routines for the RVB Standard Extension.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_clz(DisasContext *ctx, arg_clz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_clz);
+}
+
+static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_ctz);
+}
+
+/* RV64-only instructions */
+#ifdef TARGET_RISCV64
+
+static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_clzw);
+}
+
+static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_ctzw);
+}
+
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 554d52a4be3..398d4502a96 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,23 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
#endif
+#ifdef TARGET_RISCV64
+
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
+ tcg_gen_ctzi_i64(ret, ret, 32);
+}
+
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_i64(ret, arg1);
+ tcg_gen_clzi_i64(ret, ret, 64);
+ tcg_gen_subi_i64(ret, ret, 32);
+}
+
+#endif
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
@@ -747,6 +764,30 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+ tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
+static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+ void(*func)(TCGv, TCGv))
+{
+ TCGv source = tcg_temp_new();
+
+ gen_get_gpr(source, a->rs1);
+
+ (*func)(source, source);
+
+ gen_set_gpr(a->rd, source);
+ tcg_temp_free(source);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.c.inc"
#include "insn_trans/trans_rvm.c.inc"
@@ -755,6 +796,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
#include "insn_trans/trans_rvd.c.inc"
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 03/15] target/riscv: rvb: count bits set
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
target/riscv/translate.c | 6 ++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index f4c42720fc7..00c56a93151 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8fe838cf0d0..ac4d8395a45 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
+pcnt 011000 000010 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index fb6e16143db..f5930f2ad53 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_unary(ctx, a, &gen_ctz);
}
+static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
return gen_unary(ctx, a, &gen_ctzw);
}
+static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_pcntw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 398d4502a96..4c9eb86e630 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -726,6 +726,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
tcg_gen_subi_i64(ret, ret, 32);
}
+static void gen_pcntw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 03/15] target/riscv: rvb: count bits set
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Kito Cheng, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
target/riscv/translate.c | 6 ++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index f4c42720fc7..00c56a93151 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8fe838cf0d0..ac4d8395a45 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
+pcnt 011000 000010 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index fb6e16143db..f5930f2ad53 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_unary(ctx, a, &gen_ctz);
}
+static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
return gen_unary(ctx, a, &gen_ctzw);
}
+static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_pcntw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 398d4502a96..4c9eb86e630 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -726,6 +726,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
tcg_gen_subi_i64(ret, ret, 32);
}
+static void gen_pcntw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 04/15] target/riscv: rvb: logic-with-negate
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
target/riscv/translate.c | 21 +++++++++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ac4d8395a45..85421dccb99 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,3 +598,7 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
pcnt 011000 000010 ..... 001 ..... 0010011 @r2
+
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index f5930f2ad53..6016ceefd64 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_andn);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_orn);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_xnor);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4c9eb86e630..fb0b2fd0728 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,27 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
#endif
+static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_andc_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
+static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_orc_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
+static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_eqv_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 04/15] target/riscv: rvb: logic-with-negate
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
target/riscv/translate.c | 21 +++++++++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ac4d8395a45..85421dccb99 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,3 +598,7 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
pcnt 011000 000010 ..... 001 ..... 0010011 @r2
+
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index f5930f2ad53..6016ceefd64 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_andn);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_orn);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_xnor);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4c9eb86e630..fb0b2fd0728 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,27 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
#endif
+static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_andc_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
+static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_orc_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
+static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_eqv_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 05/15] target/riscv: rvb: pack two words into one register
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 30 ++++++++++++++++++
target/riscv/translate.c | 41 +++++++++++++++++++++++++
4 files changed, 77 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 00c56a93151..fd7e0492372 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -91,3 +91,6 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
+
+packw 0000100 .......... 100 ..... 0111011 @r
+packuw 0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 85421dccb99..c337aed8ca3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -602,3 +602,6 @@ pcnt 011000 000010 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
+pack 0000100 .......... 100 ..... 0110011 @r
+packu 0100100 .......... 100 ..... 0110011 @r
+packh 0000100 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 6016ceefd64..3da233047a9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, &gen_xnor);
}
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packh);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -74,4 +92,16 @@ static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
return gen_unary(ctx, a, &gen_pcntw);
}
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packuw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb0b2fd0728..7b427a9caec 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -732,6 +732,30 @@ static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_deposit_tl(ret, arg1, arg2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
+ tcg_temp_free(t);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -753,6 +777,23 @@ static void gen_pcntw(TCGv ret, TCGv arg1)
tcg_gen_ctpop_tl(ret, arg1);
}
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_i64(t, arg2);
+ tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_i64(t, arg1, 16);
+ tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
+ tcg_gen_ext32s_i64(ret, ret);
+ tcg_temp_free(t);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 05/15] target/riscv: rvb: pack two words into one register
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 30 ++++++++++++++++++
target/riscv/translate.c | 41 +++++++++++++++++++++++++
4 files changed, 77 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 00c56a93151..fd7e0492372 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -91,3 +91,6 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
+
+packw 0000100 .......... 100 ..... 0111011 @r
+packuw 0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 85421dccb99..c337aed8ca3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -602,3 +602,6 @@ pcnt 011000 000010 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
+pack 0000100 .......... 100 ..... 0110011 @r
+packu 0100100 .......... 100 ..... 0110011 @r
+packh 0000100 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 6016ceefd64..3da233047a9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, &gen_xnor);
}
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packh);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -74,4 +92,16 @@ static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
return gen_unary(ctx, a, &gen_pcntw);
}
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_packuw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb0b2fd0728..7b427a9caec 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -732,6 +732,30 @@ static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_deposit_tl(ret, arg1, arg2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
+ tcg_temp_free(t);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -753,6 +777,23 @@ static void gen_pcntw(TCGv ret, TCGv arg1)
tcg_gen_ctpop_tl(ret, arg1);
}
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_i64(t, arg2);
+ tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_i64(t, arg1, 16);
+ tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
+ tcg_gen_ext32s_i64(ret, ret);
+ tcg_temp_free(t);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 06/15] target/riscv: rvb: min/max instructions
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c337aed8ca3..0d6a8a1c0a5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -605,3 +605,7 @@ xnor 0100000 .......... 100 ..... 0110011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+max 0000101 .......... 110 ..... 0110011 @r
+maxu 0000101 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 3da233047a9..bd66c2ad84d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
return gen_arith(ctx, a, &gen_packh);
}
+static bool trans_min(DisasContext *ctx, arg_min *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_smin_tl);
+}
+
+static bool trans_max(DisasContext *ctx, arg_max *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_smax_tl);
+}
+
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_umin_tl);
+}
+
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_umax_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 06/15] target/riscv: rvb: min/max instructions
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c337aed8ca3..0d6a8a1c0a5 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -605,3 +605,7 @@ xnor 0100000 .......... 100 ..... 0110011 @r
pack 0000100 .......... 100 ..... 0110011 @r
packu 0100100 .......... 100 ..... 0110011 @r
packh 0000100 .......... 111 ..... 0110011 @r
+min 0000101 .......... 100 ..... 0110011 @r
+minu 0000101 .......... 101 ..... 0110011 @r
+max 0000101 .......... 110 ..... 0110011 @r
+maxu 0000101 .......... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 3da233047a9..bd66c2ad84d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -71,6 +71,30 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
return gen_arith(ctx, a, &gen_packh);
}
+static bool trans_min(DisasContext *ctx, arg_min *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_smin_tl);
+}
+
+static bool trans_max(DisasContext *ctx, arg_max *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_smax_tl);
+}
+
+static bool trans_minu(DisasContext *ctx, arg_minu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_umin_tl);
+}
+
+static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_umax_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 07/15] target/riscv: rvb: sign-extend instructions
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0d6a8a1c0a5..4baafed21f1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,6 +598,8 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
pcnt 011000 000010 ..... 001 ..... 0010011 @r2
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index bd66c2ad84d..5ea0f0ff81c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,19 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
return gen_arith(ctx, a, &tcg_gen_umax_tl);
}
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
+}
+
+{
/* RV64-only instructions */
#ifdef TARGET_RISCV64
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 07/15] target/riscv: rvb: sign-extend instructions
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 13 +++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0d6a8a1c0a5..4baafed21f1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,6 +598,8 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
pcnt 011000 000010 ..... 001 ..... 0010011 @r2
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index bd66c2ad84d..5ea0f0ff81c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,19 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
return gen_arith(ctx, a, &tcg_gen_umax_tl);
}
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
+}
+
+{
/* RV64-only instructions */
#ifdef TARGET_RISCV64
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 08/15] target/riscv: rvb: single-bit instructions
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 8 ++
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvb.c.inc | 90 +++++++++++++++++++++
target/riscv/translate.c | 102 ++++++++++++++++++++++++
4 files changed, 209 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index fd7e0492372..e2490f791b7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -94,3 +94,11 @@ pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
+sbsetw 0010100 .......... 001 ..... 0111011 @r
+sbclrw 0100100 .......... 001 ..... 0111011 @r
+sbinvw 0110100 .......... 001 ..... 0111011 @r
+sbextw 0100100 .......... 101 ..... 0111011 @r
+
+sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
+sbclriw 0100100 .......... 001 ..... 0011011 @sh5
+sbinviw 0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4baafed21f1..c697ff5c867 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -611,3 +611,12 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
+sbset 0010100 .......... 001 ..... 0110011 @r
+sbclr 0100100 .......... 001 ..... 0110011 @r
+sbinv 0110100 .......... 001 ..... 0110011 @r
+sbext 0100100 .......... 101 ..... 0110011 @r
+
+sbseti 00101. ........... 001 ..... 0010011 @sh
+sbclri 01001. ........... 001 ..... 0010011 @sh
+sbinvi 01101. ........... 001 ..... 0010011 @sh
+sbexti 01001. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 5ea0f0ff81c..43e9b670f73 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
}
+static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbext(DisasContext *ctx, arg_sbext *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbext);
+}
+
+static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbext);
+}
+
{
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, &gen_packuw);
}
+static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbext);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7b427a9caec..ca176709674 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -755,6 +755,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
+{
+ tcg_gen_movi_tl(ret, 1);
+ tcg_gen_shl_tl(ret, ret, shamt);
+}
+
+static void gen_sbset(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_or_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_sbclr(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_andc_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_sbinv(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_xor_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_sbext(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ tcg_gen_shr_tl(ret, arg1, shamt);
+ tcg_gen_andi_tl(ret, ret, 1);
+}
+
#ifdef TARGET_RISCV64
@@ -832,6 +874,66 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
return true;
}
+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->shamt);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+
+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 31);
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->shamt);
+
+ tcg_gen_andi_tl(source2, source2, 31);
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#endif
+
static void gen_ctz(TCGv ret, TCGv arg1)
{
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 08/15] target/riscv: rvb: single-bit instructions
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 8 ++
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvb.c.inc | 90 +++++++++++++++++++++
target/riscv/translate.c | 102 ++++++++++++++++++++++++
4 files changed, 209 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index fd7e0492372..e2490f791b7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -94,3 +94,11 @@ pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
+sbsetw 0010100 .......... 001 ..... 0111011 @r
+sbclrw 0100100 .......... 001 ..... 0111011 @r
+sbinvw 0110100 .......... 001 ..... 0111011 @r
+sbextw 0100100 .......... 101 ..... 0111011 @r
+
+sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
+sbclriw 0100100 .......... 001 ..... 0011011 @sh5
+sbinviw 0110100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4baafed21f1..c697ff5c867 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -611,3 +611,12 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
max 0000101 .......... 110 ..... 0110011 @r
maxu 0000101 .......... 111 ..... 0110011 @r
+sbset 0010100 .......... 001 ..... 0110011 @r
+sbclr 0100100 .......... 001 ..... 0110011 @r
+sbinv 0110100 .......... 001 ..... 0110011 @r
+sbext 0100100 .......... 101 ..... 0110011 @r
+
+sbseti 00101. ........... 001 ..... 0010011 @sh
+sbclri 01001. ........... 001 ..... 0010011 @sh
+sbinvi 01101. ........... 001 ..... 0010011 @sh
+sbexti 01001. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 5ea0f0ff81c..43e9b670f73 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
}
+static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbext(DisasContext *ctx, arg_sbext *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sbext);
+}
+
+static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shifti(ctx, a, &gen_sbext);
+}
+
{
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, &gen_packuw);
}
+static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sbset);
+}
+
+static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sbclr);
+}
+
+static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sbinv);
+}
+
+static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sbext);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7b427a9caec..ca176709674 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -755,6 +755,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
+{
+ tcg_gen_movi_tl(ret, 1);
+ tcg_gen_shl_tl(ret, ret, shamt);
+}
+
+static void gen_sbset(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_or_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_sbclr(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_andc_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_sbinv(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ TCGv t = tcg_temp_new();
+
+ gen_sbop_mask(t, shamt);
+ tcg_gen_xor_tl(ret, arg1, t);
+
+ tcg_temp_free(t);
+}
+
+static void gen_sbext(TCGv ret, TCGv arg1, TCGv shamt)
+{
+ tcg_gen_shr_tl(ret, arg1, shamt);
+ tcg_gen_andi_tl(ret, ret, 1);
+}
+
#ifdef TARGET_RISCV64
@@ -832,6 +874,66 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
return true;
}
+static bool gen_shifti(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->shamt);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+
+static bool gen_shiftw(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 31);
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->shamt);
+
+ tcg_gen_andi_tl(source2, source2, 31);
+ (*func)(source1, source1, source2);
+ tcg_gen_ext32s_tl(source1, source1);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#endif
+
static void gen_ctz(TCGv ret, TCGv arg1)
{
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 09/15] target/riscv: rvb: shift ones
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvb.c.inc | 58 +++++++++++++++++++++++++
target/riscv/translate.c | 13 ++++++
4 files changed, 79 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index e2490f791b7..6d017c70c74 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -98,7 +98,11 @@ sbsetw 0010100 .......... 001 ..... 0111011 @r
sbclrw 0100100 .......... 001 ..... 0111011 @r
sbinvw 0110100 .......... 001 ..... 0111011 @r
sbextw 0100100 .......... 101 ..... 0111011 @r
+slow 0010000 .......... 001 ..... 0111011 @r
+srow 0010000 .......... 101 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
sbinviw 0110100 .......... 001 ..... 0011011 @sh5
+sloiw 0010000 .......... 001 ..... 0011011 @sh5
+sroiw 0010000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c697ff5c867..78ce4b11097 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -615,8 +615,12 @@ sbset 0010100 .......... 001 ..... 0110011 @r
sbclr 0100100 .......... 001 ..... 0110011 @r
sbinv 0110100 .......... 001 ..... 0110011 @r
sbext 0100100 .......... 101 ..... 0110011 @r
+slo 0010000 .......... 001 ..... 0110011 @r
+sro 0010000 .......... 101 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
sbinvi 01101. ........... 001 ..... 0010011 @sh
sbexti 01001. ........... 101 ..... 0010011 @sh
+sloi 00100. ........... 001 ..... 0010011 @sh
+sroi 00100. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 43e9b670f73..11b5439e703 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -155,6 +155,40 @@ static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
return gen_shifti(ctx, a, &gen_sbext);
}
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_slo);
+}
+
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_shifti(ctx, a, &gen_slo);
+}
+
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sro);
+}
+
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_shifti(ctx, a, &gen_sro);
+}
+
{
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -231,4 +265,28 @@ static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
return gen_shiftw(ctx, a, &gen_sbext);
}
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_slo);
+}
+
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_slo);
+}
+
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sro);
+}
+
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sro);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ca176709674..0c00d20ab1b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -797,6 +797,19 @@ static void gen_sbext(TCGv ret, TCGv arg1, TCGv shamt)
tcg_gen_andi_tl(ret, ret, 1);
}
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shl_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
+
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shr_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
#ifdef TARGET_RISCV64
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 09/15] target/riscv: rvb: shift ones
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvb.c.inc | 58 +++++++++++++++++++++++++
target/riscv/translate.c | 13 ++++++
4 files changed, 79 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index e2490f791b7..6d017c70c74 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -98,7 +98,11 @@ sbsetw 0010100 .......... 001 ..... 0111011 @r
sbclrw 0100100 .......... 001 ..... 0111011 @r
sbinvw 0110100 .......... 001 ..... 0111011 @r
sbextw 0100100 .......... 101 ..... 0111011 @r
+slow 0010000 .......... 001 ..... 0111011 @r
+srow 0010000 .......... 101 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
sbinviw 0110100 .......... 001 ..... 0011011 @sh5
+sloiw 0010000 .......... 001 ..... 0011011 @sh5
+sroiw 0010000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c697ff5c867..78ce4b11097 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -615,8 +615,12 @@ sbset 0010100 .......... 001 ..... 0110011 @r
sbclr 0100100 .......... 001 ..... 0110011 @r
sbinv 0110100 .......... 001 ..... 0110011 @r
sbext 0100100 .......... 101 ..... 0110011 @r
+slo 0010000 .......... 001 ..... 0110011 @r
+sro 0010000 .......... 101 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
sbinvi 01101. ........... 001 ..... 0010011 @sh
sbexti 01001. ........... 101 ..... 0010011 @sh
+sloi 00100. ........... 001 ..... 0010011 @sh
+sroi 00100. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 43e9b670f73..11b5439e703 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -155,6 +155,40 @@ static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a)
return gen_shifti(ctx, a, &gen_sbext);
}
+static bool trans_slo(DisasContext *ctx, arg_slo *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_slo);
+}
+
+static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_shifti(ctx, a, &gen_slo);
+}
+
+static bool trans_sro(DisasContext *ctx, arg_sro *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_sro);
+}
+
+static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_shifti(ctx, a, &gen_sro);
+}
+
{
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -231,4 +265,28 @@ static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a)
return gen_shiftw(ctx, a, &gen_sbext);
}
+static bool trans_slow(DisasContext *ctx, arg_slow *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_slo);
+}
+
+static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_slo);
+}
+
+static bool trans_srow(DisasContext *ctx, arg_srow *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_sro);
+}
+
+static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftiw(ctx, a, &gen_sro);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ca176709674..0c00d20ab1b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -797,6 +797,19 @@ static void gen_sbext(TCGv ret, TCGv arg1, TCGv shamt)
tcg_gen_andi_tl(ret, ret, 1);
}
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shl_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
+
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_not_tl(ret, arg1);
+ tcg_gen_shr_tl(ret, ret, arg2);
+ tcg_gen_not_tl(ret, ret);
+}
#ifdef TARGET_RISCV64
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 10/15] target/riscv: rvb: rotate (left/right)
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 61 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++
4 files changed, 103 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6d017c70c74..ac0634d754a 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -100,9 +100,12 @@ sbinvw 0110100 .......... 001 ..... 0111011 @r
sbextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
sbinviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 78ce4b11097..b4677293582 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -617,6 +617,8 @@ sbinv 0110100 .......... 001 ..... 0110011 @r
sbext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -624,3 +626,4 @@ sbinvi 01101. ........... 001 ..... 0010011 @sh
sbexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 11b5439e703..433cc7f9fc8 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -189,7 +189,36 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, &gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ TCGv source1 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_rotri_tl(source1, source1, a->shamt);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
+ return true;
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_rotl_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -289,4 +318,36 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
return gen_shiftiw(ctx, a, &gen_sro);
}
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ if (a->shamt == 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_rolw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0c00d20ab1b..10b4142a3ab 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -849,6 +849,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 10/15] target/riscv: rvb: rotate (left/right)
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvb.c.inc | 61 +++++++++++++++++++++++++
target/riscv/translate.c | 36 +++++++++++++++
4 files changed, 103 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6d017c70c74..ac0634d754a 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -100,9 +100,12 @@ sbinvw 0110100 .......... 001 ..... 0111011 @r
sbextw 0100100 .......... 101 ..... 0111011 @r
slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
+rorw 0110000 .......... 101 ..... 0111011 @r
+rolw 0110000 .......... 001 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
sbinviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
+roriw 0110000 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 78ce4b11097..b4677293582 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -617,6 +617,8 @@ sbinv 0110100 .......... 001 ..... 0110011 @r
sbext 0100100 .......... 101 ..... 0110011 @r
slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -624,3 +626,4 @@ sbinvi 01101. ........... 001 ..... 0010011 @sh
sbexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
+rori 01100. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 11b5439e703..433cc7f9fc8 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -189,7 +189,36 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
return gen_shifti(ctx, a, &gen_sro);
}
+static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_rotr_tl);
+}
+
+static bool trans_rori(DisasContext *ctx, arg_rori *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ TCGv source1 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_rotri_tl(source1, source1, a->shamt);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
+ return true;
+}
+
+static bool trans_rol(DisasContext *ctx, arg_rol *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &tcg_gen_rotl_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -289,4 +318,36 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
return gen_shiftiw(ctx, a, &gen_sro);
}
+static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_rorw);
+}
+
+static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ if (a->shamt == 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ return true;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_rorw);
+}
+
+static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_rolw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0c00d20ab1b..10b4142a3ab 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -849,6 +849,42 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(t);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 11/15] target/riscv: rvb: generalized reverse
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/bitmanip_helper.c | 72 +++++++++++++++++++++++++
target/riscv/helper.h | 7 +++
target/riscv/insn32-64.decode | 2 +
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvb.c.inc | 34 ++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 32 +++++++++++
7 files changed, 150 insertions(+)
create mode 100644 target/riscv/bitmanip_helper.c
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 00000000000..716d80aab59
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,72 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg.h"
+
+static const uint64_t adjacent_masks[] = {
+ dup_const(MO_8, 0x55),
+ dup_const(MO_8, 0x33),
+ dup_const(MO_8, 0x0f),
+ dup_const(MO_16, 0xff),
+ dup_const(MO_32, 0xffff),
+#ifdef TARGET_RISCV64
+ UINT32_MAX
+#endif
+};
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x = do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, 32);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 939731c345d..a055c539fad 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,13 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
#endif
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
+#if defined(TARGET_RISCV64)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+#endif
+
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index ac0634d754a..a355b91e399 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -102,6 +102,7 @@ slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
+grevw 0110100 .......... 101 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -109,3 +110,4 @@ sbinviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
+greviw 0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b4677293582..fd8f4238ef7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -619,6 +619,7 @@ slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
+grev 0110100 .......... 101 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -627,3 +628,4 @@ sbexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
+grevi 01101. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 433cc7f9fc8..142e9123d68 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -219,6 +219,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_arith(ctx, a, &tcg_gen_rotl_tl);
}
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_helper_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_grevi(ctx, a);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -350,4 +367,21 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
return gen_shiftw(ctx, a, &gen_rolw);
}
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_grevw);
+}
+
#endif
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 14a5c62dace..de530298454 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -21,6 +21,7 @@ riscv_ss.add(files(
'gdbstub.c',
'op_helper.c',
'vector_helper.c',
+ 'bitmanip_helper.c',
'translate.c',
))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 10b4142a3ab..b40d170c01b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -811,6 +811,32 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2;
+
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt == (TARGET_LONG_BITS - 8)) {
+ /* rev8, byte swaps */
+#ifdef TARGET_RISCV32
+ tcg_gen_bswap32_tl(source1, source1);
+#else
+ tcg_gen_bswap64_tl(source1, source1);
+#endif
+ } else {
+ source2 = tcg_temp_new();
+ tcg_gen_movi_tl(source2, a->shamt);
+ gen_helper_grev(source1, source1, source2);
+ tcg_temp_free(source2);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -885,6 +911,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free_i32(t2);
}
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_grev(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 11/15] target/riscv: rvb: generalized reverse
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/bitmanip_helper.c | 72 +++++++++++++++++++++++++
target/riscv/helper.h | 7 +++
target/riscv/insn32-64.decode | 2 +
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvb.c.inc | 34 ++++++++++++
target/riscv/meson.build | 1 +
target/riscv/translate.c | 32 +++++++++++
7 files changed, 150 insertions(+)
create mode 100644 target/riscv/bitmanip_helper.c
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
new file mode 100644
index 00000000000..716d80aab59
--- /dev/null
+++ b/target/riscv/bitmanip_helper.c
@@ -0,0 +1,72 @@
+/*
+ * RISC-V Bitmanip Extension Helpers for QEMU.
+ *
+ * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+ * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg.h"
+
+static const uint64_t adjacent_masks[] = {
+ dup_const(MO_8, 0x55),
+ dup_const(MO_8, 0x33),
+ dup_const(MO_8, 0x0f),
+ dup_const(MO_16, 0xff),
+ dup_const(MO_32, 0xffff),
+#ifdef TARGET_RISCV64
+ UINT32_MAX
+#endif
+};
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+static target_ulong do_grev(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x = do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, TARGET_LONG_BITS);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_grev(rs1, rs2, 32);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 939731c345d..a055c539fad 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,13 @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
#endif
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+/* Bitmanip */
+DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+
+#if defined(TARGET_RISCV64)
+DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+#endif
+
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index ac0634d754a..a355b91e399 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -102,6 +102,7 @@ slow 0010000 .......... 001 ..... 0111011 @r
srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
+grevw 0110100 .......... 101 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -109,3 +110,4 @@ sbinviw 0110100 .......... 001 ..... 0011011 @sh5
sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
+greviw 0110100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b4677293582..fd8f4238ef7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -619,6 +619,7 @@ slo 0010000 .......... 001 ..... 0110011 @r
sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
+grev 0110100 .......... 101 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -627,3 +628,4 @@ sbexti 01001. ........... 101 ..... 0010011 @sh
sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
+grevi 01101. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 433cc7f9fc8..142e9123d68 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -219,6 +219,23 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_arith(ctx, a, &tcg_gen_rotl_tl);
}
+static bool trans_grev(DisasContext *ctx, arg_grev *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_helper_grev);
+}
+
+static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_grevi(ctx, a);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -350,4 +367,21 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
return gen_shiftw(ctx, a, &gen_rolw);
}
+static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_grevw);
+}
+
+static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_grevw);
+}
+
#endif
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 14a5c62dace..de530298454 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -21,6 +21,7 @@ riscv_ss.add(files(
'gdbstub.c',
'op_helper.c',
'vector_helper.c',
+ 'bitmanip_helper.c',
'translate.c',
))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 10b4142a3ab..b40d170c01b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -811,6 +811,32 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_not_tl(ret, ret);
}
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2;
+
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt == (TARGET_LONG_BITS - 8)) {
+ /* rev8, byte swaps */
+#ifdef TARGET_RISCV32
+ tcg_gen_bswap32_tl(source1, source1);
+#else
+ tcg_gen_bswap64_tl(source1, source1);
+#endif
+ } else {
+ source2 = tcg_temp_new();
+ tcg_gen_movi_tl(source2, a->shamt);
+ gen_helper_grev(source1, source1, source2);
+ tcg_temp_free(source2);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -885,6 +911,12 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free_i32(t2);
}
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_grev(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 12/15] target/riscv: rvb: generalized or-combine
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/bitmanip_helper.c | 31 ++++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32-64.decode | 2 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 34 +++++++++++++++++++++++++
target/riscv/translate.c | 6 +++++
6 files changed, 77 insertions(+)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 716d80aab59..6ab55b4b176 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -70,3 +70,34 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
#endif
+static target_ulong do_gorc(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x |= do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, TARGET_LONG_BITS);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, 32);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a055c539fad..de3c341c2f4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,9 +68,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
#endif
/* Special functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index a355b91e399..46f469700b5 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -103,6 +103,7 @@ srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
+gorcw 0010100 .......... 101 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -111,3 +112,4 @@ sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
+gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fd8f4238ef7..98d2ee0ab56 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -620,6 +620,7 @@ sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
+gorc 0010100 .......... 101 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -629,3 +630,4 @@ sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
+gorci 00101. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 142e9123d68..c35fe84444c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -236,6 +236,23 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
return gen_grevi(ctx, a);
}
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_helper_gorc);
+}
+
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_shifti(ctx, a, &gen_helper_gorc);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -384,4 +401,21 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
return gen_shiftiw(ctx, a, &gen_grevw);
}
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_gorcw);
+}
+
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_gorcw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b40d170c01b..021daf10875 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -917,6 +917,12 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_grev(ret, arg1, arg2);
}
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_gorc(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 12/15] target/riscv: rvb: generalized or-combine
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/bitmanip_helper.c | 31 ++++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32-64.decode | 2 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 34 +++++++++++++++++++++++++
target/riscv/translate.c | 6 +++++
6 files changed, 77 insertions(+)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 716d80aab59..6ab55b4b176 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -70,3 +70,34 @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
#endif
+static target_ulong do_gorc(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ target_ulong x = rs1;
+ int i, shift;
+
+ for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+ if (rs2 & shift) {
+ x |= do_swap(x, adjacent_masks[i], shift);
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, TARGET_LONG_BITS);
+}
+
+/* RV64-only instruction */
+#ifdef TARGET_RISCV64
+
+target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+{
+ return do_gorc(rs1, rs2, 32);
+}
+
+#endif
+
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a055c539fad..de3c341c2f4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,9 +68,11 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
#if defined(TARGET_RISCV64)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
#endif
/* Special functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index a355b91e399..46f469700b5 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -103,6 +103,7 @@ srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
+gorcw 0010100 .......... 101 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -111,3 +112,4 @@ sloiw 0010000 .......... 001 ..... 0011011 @sh5
sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
+gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fd8f4238ef7..98d2ee0ab56 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -620,6 +620,7 @@ sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
+gorc 0010100 .......... 101 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
@@ -629,3 +630,4 @@ sloi 00100. ........... 001 ..... 0010011 @sh
sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
+gorci 00101. ........... 101 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 142e9123d68..c35fe84444c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -236,6 +236,23 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
return gen_grevi(ctx, a);
}
+static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shift(ctx, a, &gen_helper_gorc);
+}
+
+static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ return gen_shifti(ctx, a, &gen_helper_gorc);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -384,4 +401,21 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
return gen_shiftiw(ctx, a, &gen_grevw);
}
+static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_shiftw(ctx, a, &gen_gorcw);
+}
+
+static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+
+ if (a->shamt >= 32) {
+ return false;
+ }
+
+ return gen_shiftiw(ctx, a, &gen_gorcw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b40d170c01b..021daf10875 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -917,6 +917,12 @@ static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_grev(ret, arg1, arg2);
}
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ gen_helper_gorc(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 13/15] target/riscv: rvb: address calculation
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
target/riscv/translate.c | 32 +++++++++++++++++++++++++
4 files changed, 61 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 46f469700b5..1059cab5aa4 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -104,6 +104,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
+sh1addu_w 0010000 .......... 010 ..... 0111011 @r
+sh2addu_w 0010000 .......... 100 ..... 0111011 @r
+sh3addu_w 0010000 .......... 110 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 98d2ee0ab56..67c8bc5485b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -621,6 +621,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index c35fe84444c..07fe662b005 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -253,6 +253,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, &gen_helper_gorc);
}
+#define GEN_TRANS_SHADD(SHAMT) \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, &gen_sh##SHAMT##add); \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -418,4 +429,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
return gen_shiftiw(ctx, a, &gen_gorcw);
}
+#define GEN_TRANS_SHADDU_W(SHAMT) \
+static bool trans_sh##SHAMT##addu_w(DisasContext *ctx, \
+ arg_sh##SHAMT##addu_w *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, &gen_sh##SHAMT##addu_w); \
+}
+
+GEN_TRANS_SHADDU_W(1)
+GEN_TRANS_SHADDU_W(2)
+GEN_TRANS_SHADDU_W(3)
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 021daf10875..f9385bbcd4f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -837,6 +837,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
return true;
}
+#define GEN_SHADD(SHAMT) \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -923,6 +938,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_gorc(ret, arg1, arg2);
}
+#define GEN_SHADDU_W(SHAMT) \
+static void gen_sh##SHAMT##addu_w(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_ext32u_tl(t, arg1); \
+ \
+ tcg_gen_shli_tl(t, t, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADDU_W(1)
+GEN_SHADDU_W(2)
+GEN_SHADDU_W(3)
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 13/15] target/riscv: rvb: address calculation
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn32.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
target/riscv/translate.c | 32 +++++++++++++++++++++++++
4 files changed, 61 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 46f469700b5..1059cab5aa4 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -104,6 +104,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
+sh1addu_w 0010000 .......... 010 ..... 0111011 @r
+sh2addu_w 0010000 .......... 100 ..... 0111011 @r
+sh3addu_w 0010000 .......... 110 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 98d2ee0ab56..67c8bc5485b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -621,6 +621,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
sbseti 00101. ........... 001 ..... 0010011 @sh
sbclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index c35fe84444c..07fe662b005 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -253,6 +253,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, &gen_helper_gorc);
}
+#define GEN_TRANS_SHADD(SHAMT) \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, &gen_sh##SHAMT##add); \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -418,4 +429,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
return gen_shiftiw(ctx, a, &gen_gorcw);
}
+#define GEN_TRANS_SHADDU_W(SHAMT) \
+static bool trans_sh##SHAMT##addu_w(DisasContext *ctx, \
+ arg_sh##SHAMT##addu_w *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, &gen_sh##SHAMT##addu_w); \
+}
+
+GEN_TRANS_SHADDU_W(1)
+GEN_TRANS_SHADDU_W(2)
+GEN_TRANS_SHADDU_W(3)
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 021daf10875..f9385bbcd4f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -837,6 +837,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
return true;
}
+#define GEN_SHADD(SHAMT) \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -923,6 +938,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_gorc(ret, arg1, arg2);
}
+#define GEN_SHADDU_W(SHAMT) \
+static void gen_sh##SHAMT##addu_w(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_ext32u_tl(t, arg1); \
+ \
+ tcg_gen_shli_tl(t, t, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADDU_W(1)
+GEN_SHADDU_W(2)
+GEN_SHADDU_W(3)
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 22 ++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 31 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 1059cab5aa4..f819028266c 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -107,6 +107,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r
sh1addu_w 0010000 .......... 010 ..... 0111011 @r
sh2addu_w 0010000 .......... 100 ..... 0111011 @r
sh3addu_w 0010000 .......... 110 ..... 0111011 @r
+addu_w 0000100 .......... 000 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -116,3 +117,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+
+slliu_w 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 07fe662b005..323ca5eccee 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -441,4 +441,26 @@ GEN_TRANS_SHADDU_W(1)
GEN_TRANS_SHADDU_W(2)
GEN_TRANS_SHADDU_W(3)
+static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_addu_w);
+}
+
+static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
+{
+ TCGv source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt < 32) {
+ tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
+ } else {
+ tcg_gen_shli_i64(source1, source1, a->shamt);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f9385bbcd4f..84e55880234 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -955,6 +955,12 @@ GEN_SHADDU_W(1)
GEN_SHADDU_W(2)
GEN_SHADDU_W(3)
+static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_add_tl(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 3 +++
target/riscv/insn_trans/trans_rvb.c.inc | 22 ++++++++++++++++++++++
target/riscv/translate.c | 6 ++++++
3 files changed, 31 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 1059cab5aa4..f819028266c 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -107,6 +107,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r
sh1addu_w 0010000 .......... 010 ..... 0111011 @r
sh2addu_w 0010000 .......... 100 ..... 0111011 @r
sh3addu_w 0010000 .......... 110 ..... 0111011 @r
+addu_w 0000100 .......... 000 ..... 0111011 @r
sbsetiw 0010100 .......... 001 ..... 0011011 @sh5
sbclriw 0100100 .......... 001 ..... 0011011 @sh5
@@ -116,3 +117,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
+
+slliu_w 00001. ........... 001 ..... 0011011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 07fe662b005..323ca5eccee 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -441,4 +441,26 @@ GEN_TRANS_SHADDU_W(1)
GEN_TRANS_SHADDU_W(2)
GEN_TRANS_SHADDU_W(3)
+static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_addu_w);
+}
+
+static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a)
+{
+ TCGv source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ if (a->shamt < 32) {
+ tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
+ } else {
+ tcg_gen_shli_i64(source1, source1, a->shamt);
+ }
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f9385bbcd4f..84e55880234 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -955,6 +955,12 @@ GEN_SHADDU_W(1)
GEN_SHADDU_W(2)
GEN_SHADDU_W(3)
+static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_add_tl(ret, arg1, arg2);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
@ 2020-12-16 2:01 ` frank.chang
2020-12-16 2:01 ` frank.chang
` (13 subsequent siblings)
14 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a0264fc6b1..33fa112c4ac 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -441,6 +441,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_b) {
+ target_misa |= RVB;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -511,6 +514,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c0a326c8430..4868f62f32b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,6 +66,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -276,6 +277,7 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
+ bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line
@ 2020-12-16 2:01 ` frank.chang
0 siblings, 0 replies; 63+ messages in thread
From: frank.chang @ 2020-12-16 2:01 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Kito Cheng, Frank Chang, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
From: Kito Cheng <kito.cheng@sifive.com>
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a0264fc6b1..33fa112c4ac 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -441,6 +441,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_b) {
+ target_misa |= RVB;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -511,6 +514,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
+ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c0a326c8430..4868f62f32b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -66,6 +66,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVB RV('B')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -276,6 +277,7 @@ struct RISCVCPU {
bool ext_f;
bool ext_d;
bool ext_c;
+ bool ext_b;
bool ext_s;
bool ext_u;
bool ext_h;
--
2.17.1
^ permalink raw reply related [flat|nested] 63+ messages in thread
* Re: [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 9:14 ` Kito Cheng
-1 siblings, 0 replies; 63+ messages in thread
From: Kito Cheng @ 2020-12-16 9:14 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Palmer Dabbelt, Alistair Francis
Hi Alistair, Frank:
Should we add the bext_spec option like Vector-ext? I would suggest
adding one to align the behavior between V and B.
But I have no strong opinion for this.
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line
@ 2020-12-16 9:14 ` Kito Cheng
0 siblings, 0 replies; 63+ messages in thread
From: Kito Cheng @ 2020-12-16 9:14 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann
Hi Alistair, Frank:
Should we add the bext_spec option like Vector-ext? I would suggest
adding one to align the behavior between V and B.
But I have no strong opinion for this.
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 15:15 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32.decode | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension
@ 2020-12-16 15:15 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32.decode | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 15:21 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:21 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 4 +++
> target/riscv/insn32.decode | 7 +++-
> target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> target/riscv/translate.c | 42 ++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_i64(ret, ret, 32);
> +}
One nit: use clzi_i64(ret, ret, 64).
Most hosts, including x86_64, naturally return the register width for zero. If
you use something else, like this, then tcg will generate an extra comparison
and conditional move.
In this case you know that zero is impossible, because you just set all of the
high 32 bits, but that knowledge won't be present in the expansion of ctzi.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros
@ 2020-12-16 15:21 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:21 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 4 +++
> target/riscv/insn32.decode | 7 +++-
> target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> target/riscv/translate.c | 42 ++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_i64(ret, ret, 32);
> +}
One nit: use clzi_i64(ret, ret, 64).
Most hosts, including x86_64, naturally return the register width for zero. If
you use something else, like this, then tcg will generate an extra comparison
and conditional move.
In this case you know that zero is impossible, because you just set all of the
high 32 bits, but that knowledge won't be present in the expansion of ctzi.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 03/15] target/riscv: rvb: count bits set
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 15:24 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:24 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> + return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
...
> + return gen_unary(ctx, a, &gen_pcntw);
You can drop all of the unnecessary &'s.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 03/15] target/riscv: rvb: count bits set
@ 2020-12-16 15:24 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:24 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> + return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
...
> + return gen_unary(ctx, a, &gen_pcntw);
You can drop all of the unnecessary &'s.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 04/15] target/riscv: rvb: logic-with-negate
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 15:25 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:25 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_andc_tl(ret, arg1, arg2);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_orc_tl(ret, arg1, arg2);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_eqv_tl(ret, arg1, arg2);
> + tcg_temp_free(t);
> +}
Drop these functions entirely, along with their unused temporaries.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 04/15] target/riscv: rvb: logic-with-negate
@ 2020-12-16 15:25 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 15:25 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_andc_tl(ret, arg1, arg2);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_orc_tl(ret, arg1, arg2);
> + tcg_temp_free(t);
> +}
> +
> +static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_eqv_tl(ret, arg1, arg2);
> + tcg_temp_free(t);
> +}
Drop these functions entirely, along with their unused temporaries.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 05/15] target/riscv: rvb: pack two words into one register
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:23 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:23 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 3 ++
> target/riscv/insn32.decode | 3 ++
> target/riscv/insn_trans/trans_rvb.c.inc | 30 ++++++++++++++++++
> target/riscv/translate.c | 41 +++++++++++++++++++++++++
> 4 files changed, 77 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 05/15] target/riscv: rvb: pack two words into one register
@ 2020-12-16 16:23 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:23 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 3 ++
> target/riscv/insn32.decode | 3 ++
> target/riscv/insn_trans/trans_rvb.c.inc | 30 ++++++++++++++++++
> target/riscv/translate.c | 41 +++++++++++++++++++++++++
> 4 files changed, 77 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 06/15] target/riscv: rvb: min/max instructions
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:23 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:23 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32.decode | 4 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 06/15] target/riscv: rvb: min/max instructions
@ 2020-12-16 16:23 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:23 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32.decode | 4 ++++
> target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
> 2 files changed, 28 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 07/15] target/riscv: rvb: sign-extend instructions
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:25 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:25 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
> +}
> +
> +{
Stray "{".
Presumably a rebase error fixed up in a later patch?
Anyway, with that fixed,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 07/15] target/riscv: rvb: sign-extend instructions
@ 2020-12-16 16:25 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:25 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_unary(ctx, a, &tcg_gen_ext16s_tl);
> +}
> +
> +{
Stray "{".
Presumably a rebase error fixed up in a later patch?
Anyway, with that fixed,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:34 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:34 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
Don't make the tcg optimizer do what it's easy to do in C, e.g.
tcg_gen_movi_tl(source2, a->shamt & (TARGET_LONG_BITS - 1));
Except in this case, I believe that shamt *cannot* be out of range, because
that would be an illegal instruction. E.g. in trans_srli, we check for that first.
In the previous review I had recommended that you convert the existing
immediate shift instructions to this new interface, which should have shown
this problem.
> +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + tcg_gen_andi_tl(source2, source2, 31);
This mask is unnecesary because the decode already uses @sh5.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions
@ 2020-12-16 16:34 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:34 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
Don't make the tcg optimizer do what it's easy to do in C, e.g.
tcg_gen_movi_tl(source2, a->shamt & (TARGET_LONG_BITS - 1));
Except in this case, I believe that shamt *cannot* be out of range, because
that would be an illegal instruction. E.g. in trans_srli, we check for that first.
In the previous review I had recommended that you convert the existing
immediate shift instructions to this new interface, which should have shown
this problem.
> +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + tcg_gen_andi_tl(source2, source2, 31);
This mask is unnecesary because the decode already uses @sh5.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 09/15] target/riscv: rvb: shift ones
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:35 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:35 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
As I mentioned vs the previous patch, these checks should be in gen_shifti.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 09/15] target/riscv: rvb: shift ones
@ 2020-12-16 16:35 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:35 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
As I mentioned vs the previous patch, these checks should be in gen_shifti.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 10/15] target/riscv: rvb: rotate (left/right)
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:39 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:39 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_ror(DisasContext *ctx, arg_ror *a)
> {
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &tcg_gen_rotr_tl);
> +}
Use gen_shift.
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + TCGv source1 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_rotri_tl(source1, source1, a->shamt);
> + gen_set_gpr(a->rd, source1);
Use gen_shifti.
> +static bool trans_rol(DisasContext *ctx, arg_rol *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &tcg_gen_rotl_tl);
> +}
Use gen_shift.
> +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, &gen_rorw);
> +}
> +
> +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= 32) {
> + return false;
> + }
Test is impossible due to @sh5.
> + if (a->shamt == 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_ext32s_tl(t, t);
> + gen_set_gpr(a->rd, t);
> + tcg_temp_free(t);
> + return true;
> + }
Why do you need this special case? The general expansion would appear to work
fine, and surely this needs no special optimization.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 10/15] target/riscv: rvb: rotate (left/right)
@ 2020-12-16 16:39 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:39 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_ror(DisasContext *ctx, arg_ror *a)
> {
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &tcg_gen_rotr_tl);
> +}
Use gen_shift.
> +static bool trans_rori(DisasContext *ctx, arg_rori *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> + TCGv source1 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_rotri_tl(source1, source1, a->shamt);
> + gen_set_gpr(a->rd, source1);
Use gen_shifti.
> +static bool trans_rol(DisasContext *ctx, arg_rol *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_arith(ctx, a, &tcg_gen_rotl_tl);
> +}
Use gen_shift.
> +static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> + return gen_shiftw(ctx, a, &gen_rorw);
> +}
> +
> +static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= 32) {
> + return false;
> + }
Test is impossible due to @sh5.
> + if (a->shamt == 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_ext32s_tl(t, t);
> + gen_set_gpr(a->rd, t);
> + tcg_temp_free(t);
> + return true;
> + }
Why do you need this special case? The general expansion would appear to work
fine, and surely this needs no special optimization.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 11/15] target/riscv: rvb: generalized reverse
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 16:52 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:52 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
> +{
> + return do_grev(rs1, rs2, 32);
> +}
> +
> +#endif
> +
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
Stray whitespace at the end of the file.
checkpatch or git should have complained about this.
> +static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2;
> +
> + gen_get_gpr(source1, a->rs1);
> +
> + if (a->shamt == (TARGET_LONG_BITS - 8)) {
> + /* rev8, byte swaps */
> +#ifdef TARGET_RISCV32
> + tcg_gen_bswap32_tl(source1, source1);
> +#else
> + tcg_gen_bswap64_tl(source1, source1);
> +#endif
I should add a tcg_gen_bswap_tl define so that this ifdef is not necessary.
For the to-do list...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 11/15] target/riscv: rvb: generalized reverse
@ 2020-12-16 16:52 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 16:52 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
> +{
> + return do_grev(rs1, rs2, 32);
> +}
> +
> +#endif
> +
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
Stray whitespace at the end of the file.
checkpatch or git should have complained about this.
> +static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2;
> +
> + gen_get_gpr(source1, a->rs1);
> +
> + if (a->shamt == (TARGET_LONG_BITS - 8)) {
> + /* rev8, byte swaps */
> +#ifdef TARGET_RISCV32
> + tcg_gen_bswap32_tl(source1, source1);
> +#else
> + tcg_gen_bswap64_tl(source1, source1);
> +#endif
I should add a tcg_gen_bswap_tl define so that this ifdef is not necessary.
For the to-do list...
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 12/15] target/riscv: rvb: generalized or-combine
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 18:15 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
Check should be in gen_shifti.
> +static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= 32) {
> + return false;
> + }
Check is unnecessary due to @sh5.
> +static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_ext32u_tl(arg1, arg1);
> + gen_helper_gorc(ret, arg1, arg2);
> +}
Calling the wrong helper. The zero-extension should be unnecessary -- the high
bits will be overridden by the sign-extension at the end of gen_shiftw.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 12/15] target/riscv: rvb: generalized or-combine
@ 2020-12-16 18:15 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:15 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
Check should be in gen_shifti.
> +static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= 32) {
> + return false;
> + }
Check is unnecessary due to @sh5.
> +static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_ext32u_tl(arg1, arg1);
> + gen_helper_gorc(ret, arg1, arg2);
> +}
Calling the wrong helper. The zero-extension should be unnecessary -- the high
bits will be overridden by the sign-extension at the end of gen_shiftw.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 13/15] target/riscv: rvb: address calculation
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 18:17 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:17 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 3 +++
> target/riscv/insn32.decode | 3 +++
> target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
> target/riscv/translate.c | 32 +++++++++++++++++++++++++
> 4 files changed, 61 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 13/15] target/riscv: rvb: address calculation
@ 2020-12-16 18:17 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:17 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 3 +++
> target/riscv/insn32.decode | 3 +++
> target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++++++++++
> target/riscv/translate.c | 32 +++++++++++++++++++++++++
> 4 files changed, 61 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend
2020-12-16 2:01 ` frank.chang
@ 2020-12-16 18:30 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:30 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Kito Cheng, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 3 +++
> target/riscv/insn_trans/trans_rvb.c.inc | 22 ++++++++++++++++++++++
> target/riscv/translate.c | 6 ++++++
> 3 files changed, 31 insertions(+)
Subject should be add/slli as there is no sub.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend
@ 2020-12-16 18:30 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:30 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Alistair Francis,
Palmer Dabbelt, Kito Cheng
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 3 +++
> target/riscv/insn_trans/trans_rvb.c.inc | 22 ++++++++++++++++++++++
> target/riscv/translate.c | 6 ++++++
> 3 files changed, 31 insertions(+)
Subject should be add/slli as there is no sub.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line
2020-12-16 9:14 ` Kito Cheng
@ 2020-12-16 18:31 ` Richard Henderson
-1 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:31 UTC (permalink / raw)
To: Kito Cheng, Frank Chang
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Alistair Francis, Palmer Dabbelt
On 12/16/20 3:14 AM, Kito Cheng wrote:
> Hi Alistair, Frank:
>
> Should we add the bext_spec option like Vector-ext? I would suggest
> adding one to align the behavior between V and B.
> But I have no strong opinion for this.
>
I don't think there's any point in that. The experimental extension will be
updated without backward compatibility until it reaches 1.0. After which we
could add one, *if* we expected there to be future incompatible changes.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line
@ 2020-12-16 18:31 ` Richard Henderson
0 siblings, 0 replies; 63+ messages in thread
From: Richard Henderson @ 2020-12-16 18:31 UTC (permalink / raw)
To: Kito Cheng, Frank Chang
Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, qemu-devel,
Palmer Dabbelt, Alistair Francis
On 12/16/20 3:14 AM, Kito Cheng wrote:
> Hi Alistair, Frank:
>
> Should we add the bext_spec option like Vector-ext? I would suggest
> adding one to align the behavior between V and B.
> But I have no strong opinion for this.
>
I don't think there's any point in that. The experimental extension will be
updated without backward compatibility until it reaches 1.0. After which we
could add one, *if* we expected there to be future incompatible changes.
r~
^ permalink raw reply [flat|nested] 63+ messages in thread
end of thread, other threads:[~2020-12-16 18:35 UTC | newest]
Thread overview: 63+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
2020-12-16 2:01 ` [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 15:15 ` Richard Henderson
2020-12-16 15:15 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 15:21 ` Richard Henderson
2020-12-16 15:21 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 03/15] target/riscv: rvb: count bits set frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 15:24 ` Richard Henderson
2020-12-16 15:24 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 04/15] target/riscv: rvb: logic-with-negate frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 15:25 ` Richard Henderson
2020-12-16 15:25 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 05/15] target/riscv: rvb: pack two words into one register frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:23 ` Richard Henderson
2020-12-16 16:23 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 06/15] target/riscv: rvb: min/max instructions frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:23 ` Richard Henderson
2020-12-16 16:23 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 07/15] target/riscv: rvb: sign-extend instructions frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:25 ` Richard Henderson
2020-12-16 16:25 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 08/15] target/riscv: rvb: single-bit instructions frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:34 ` Richard Henderson
2020-12-16 16:34 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 09/15] target/riscv: rvb: shift ones frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:35 ` Richard Henderson
2020-12-16 16:35 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 10/15] target/riscv: rvb: rotate (left/right) frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:39 ` Richard Henderson
2020-12-16 16:39 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 11/15] target/riscv: rvb: generalized reverse frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 16:52 ` Richard Henderson
2020-12-16 16:52 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 12/15] target/riscv: rvb: generalized or-combine frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 18:15 ` Richard Henderson
2020-12-16 18:15 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 13/15] target/riscv: rvb: address calculation frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 18:17 ` Richard Henderson
2020-12-16 18:17 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 18:30 ` Richard Henderson
2020-12-16 18:30 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2020-12-16 2:01 ` frank.chang
2020-12-16 9:14 ` Kito Cheng
2020-12-16 9:14 ` Kito Cheng
2020-12-16 18:31 ` Richard Henderson
2020-12-16 18:31 ` Richard Henderson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.