From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D664C33CA2 for ; Sun, 12 Jan 2020 15:12:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2C259214D8 for ; Sun, 12 Jan 2020 15:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733063AbgALPMa (ORCPT ); Sun, 12 Jan 2020 10:12:30 -0500 Received: from foss.arm.com ([217.140.110.172]:59698 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733062AbgALPMa (ORCPT ); Sun, 12 Jan 2020 10:12:30 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51B7FDA7; Sun, 12 Jan 2020 07:12:29 -0800 (PST) Received: from [192.168.3.111] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CE9653F68E; Sun, 12 Jan 2020 07:12:27 -0800 (PST) Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes To: Maxime Ripard Cc: Chen-Yu Tsai , Mark Brown , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, Icenowy Zheng , devicetree@vger.kernel.org, Rob Herring , Mark Rutland References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> <20200111172639.to3lhzros6ca5hj2@gilmour.lan> From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Autocrypt: addr=andre.przywara@arm.com; prefer-encrypt=mutual; keydata= xsFNBFNPCKMBEAC+6GVcuP9ri8r+gg2fHZDedOmFRZPtcrMMF2Cx6KrTUT0YEISsqPoJTKld tPfEG0KnRL9CWvftyHseWTnU2Gi7hKNwhRkC0oBL5Er2hhNpoi8x4VcsxQ6bHG5/dA7ctvL6 kYvKAZw4X2Y3GTbAZIOLf+leNPiF9175S8pvqMPi0qu67RWZD5H/uT/TfLpvmmOlRzNiXMBm kGvewkBpL3R2clHquv7pB6KLoY3uvjFhZfEedqSqTwBVu/JVZZO7tvYCJPfyY5JG9+BjPmr+ REe2gS6w/4DJ4D8oMWKoY3r6ZpHx3YS2hWZFUYiCYovPxfj5+bOr78sg3JleEd0OB0yYtzTT esiNlQpCo0oOevwHR+jUiaZevM4xCyt23L2G+euzdRsUZcK/M6qYf41Dy6Afqa+PxgMEiDto ITEH3Dv+zfzwdeqCuNU0VOGrQZs/vrKOUmU/QDlYL7G8OIg5Ekheq4N+Ay+3EYCROXkstQnf YYxRn5F1oeVeqoh1LgGH7YN9H9LeIajwBD8OgiZDVsmb67DdF6EQtklH0ycBcVodG1zTCfqM AavYMfhldNMBg4vaLh0cJ/3ZXZNIyDlV372GmxSJJiidxDm7E1PkgdfCnHk+pD8YeITmSNyb 7qeU08Hqqh4ui8SSeUp7+yie9zBhJB5vVBJoO5D0MikZAODIDwARAQABzS1BbmRyZSBQcnp5 d2FyYSAoQVJNKSA8YW5kcmUucHJ6eXdhcmFAYXJtLmNvbT7CwXsEEwECACUCGwMGCwkIBwMC BhUIAgkKCwQWAgMBAh4BAheABQJTWSV8AhkBAAoJEAL1yD+ydue63REP/1tPqTo/f6StS00g NTUpjgVqxgsPWYWwSLkgkaUZn2z9Edv86BLpqTY8OBQZ19EUwfNehcnvR+Olw+7wxNnatyxo D2FG0paTia1SjxaJ8Nx3e85jy6l7N2AQrTCFCtFN9lp8Pc0LVBpSbjmP+Peh5Mi7gtCBNkpz KShEaJE25a/+rnIrIXzJHrsbC2GwcssAF3bd03iU41J1gMTalB6HCtQUwgqSsbG8MsR/IwHW XruOnVp0GQRJwlw07e9T3PKTLj3LWsAPe0LHm5W1Q+euoCLsZfYwr7phQ19HAxSCu8hzp43u zSw0+sEQsO+9wz2nGDgQCGepCcJR1lygVn2zwRTQKbq7Hjs+IWZ0gN2nDajScuR1RsxTE4WR lj0+Ne6VrAmPiW6QqRhliDO+e82riI75ywSWrJb9TQw0+UkIQ2DlNr0u0TwCUTcQNN6aKnru ouVt3qoRlcD5MuRhLH+ttAcmNITMg7GQ6RQajWrSKuKFrt6iuDbjgO2cnaTrLbNBBKPTG4oF D6kX8Zea0KvVBagBsaC1CDTDQQMxYBPDBSlqYCb/b2x7KHTvTAHUBSsBRL6MKz8wwruDodTM 4E4ToV9URl4aE/msBZ4GLTtEmUHBh4/AYwk6ACYByYKyx5r3PDG0iHnJ8bV0OeyQ9ujfgBBP B2t4oASNnIOeGEEcQ2rjzsFNBFNPCKMBEACm7Xqafb1Dp1nDl06aw/3O9ixWsGMv1Uhfd2B6 it6wh1HDCn9HpekgouR2HLMvdd3Y//GG89irEasjzENZPsK82PS0bvkxxIHRFm0pikF4ljIb 6tca2sxFr/H7CCtWYZjZzPgnOPtnagN0qVVyEM7L5f7KjGb1/o5EDkVR2SVSSjrlmNdTL2Rd zaPqrBoxuR/y/n856deWqS1ZssOpqwKhxT1IVlF6S47CjFJ3+fiHNjkljLfxzDyQXwXCNoZn BKcW9PvAMf6W1DGASoXtsMg4HHzZ5fW+vnjzvWiC4pXrcP7Ivfxx5pB+nGiOfOY+/VSUlW/9 GdzPlOIc1bGyKc6tGREH5lErmeoJZ5k7E9cMJx+xzuDItvnZbf6RuH5fg3QsljQy8jLlr4S6 8YwxlObySJ5K+suPRzZOG2+kq77RJVqAgZXp3Zdvdaov4a5J3H8pxzjj0yZ2JZlndM4X7Msr P5tfxy1WvV4Km6QeFAsjcF5gM+wWl+mf2qrlp3dRwniG1vkLsnQugQ4oNUrx0ahwOSm9p6kM CIiTITo+W7O9KEE9XCb4vV0ejmLlgdDV8ASVUekeTJkmRIBnz0fa4pa1vbtZoi6/LlIdAEEt PY6p3hgkLLtr2GRodOW/Y3vPRd9+rJHq/tLIfwc58ZhQKmRcgrhtlnuTGTmyUqGSiMNfpwAR AQABwsFfBBgBAgAJBQJTTwijAhsMAAoJEAL1yD+ydue64BgP/33QKczgAvSdj9XTC14wZCGE U8ygZwkkyNf021iNMj+o0dpLU48PIhHIMTXlM2aiiZlPWgKVlDRjlYuc9EZqGgbOOuR/pNYA JX9vaqszyE34JzXBL9DBKUuAui8z8GcxRcz49/xtzzP0kH3OQbBIqZWuMRxKEpRptRT0wzBL O31ygf4FRxs68jvPCuZjTGKELIo656/Hmk17cmjoBAJK7JHfqdGkDXk5tneeHCkB411p9WJU vMO2EqsHjobjuFm89hI0pSxlUoiTL0Nuk9Edemjw70W4anGNyaQtBq+qu1RdjUPBvoJec7y/ EXJtoGxq9Y+tmm22xwApSiIOyMwUi9A1iLjQLmngLeUdsHyrEWTbEYHd2sAM2sqKoZRyBDSv ejRvZD6zwkY/9nRqXt02H1quVOP42xlkwOQU6gxm93o/bxd7S5tEA359Sli5gZRaucpNQkwd KLQdCvFdksD270r4jU/rwR2R/Ubi+txfy0dk2wGBjl1xpSf0Lbl/KMR5TQntELfLR4etizLq Xpd2byn96Ivi8C8u9zJruXTueHH8vt7gJ1oax3yKRGU5o2eipCRiKZ0s/T7fvkdq+8beg9ku fDO4SAgJMIl6H5awliCY2zQvLHysS/Wb8QuB09hmhLZ4AifdHyF1J5qeePEhgTA+BaUbiUZf i4aIXCH3Wv6K Organization: ARM Ltd. Message-ID: Date: Sun, 12 Jan 2020 15:12:19 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.1 MIME-Version: 1.0 In-Reply-To: <20200111172639.to3lhzros6ca5hj2@gilmour.lan> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 11/01/2020 17:26, Maxime Ripard wrote: Hi Maxime, > On Wed, Jan 08, 2020 at 10:10:05AM +0000, Andre Przywara wrote: >> The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, >> but with the added capability of 3-wire and 4-wire operation modes. >> For now the driver does not support those, but the SPI registers are >> fully backwards-compatible, just adding bits and registers which were >> formerly reserved. So we can use the existing driver for the "normal" SPI >> modes, for instance to access the SPI NOR flash soldered on the PineH64 >> board. >> We use an H6 specific compatible string in addition to the existing H3 >> string, so when the driver later gains Quad SPI support, it should work >> automatically without any DT changes. >> >> Tested by accessing the SPI flash on a Pine H64 board (SPI0), also >> connecting another SPI flash to the SPI1 header pins. >> >> Signed-off-by: Andre Przywara >> --- >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> index 3329283e38ab..40835850893e 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> @@ -338,6 +338,30 @@ >> bias-pull-up; >> }; >> >> + /omit-if-no-ref/ >> + spi0_pins: spi0-pins { >> + pins = "PC0", "PC2", "PC3"; >> + function = "spi0"; >> + }; >> + >> + /omit-if-no-ref/ >> + spi0_cs_pin: spi0-cs-pin { >> + pins = "PC5"; >> + function = "spi0"; >> + }; > > It seems suspicious to use it in the Pine H64, since PC5 is also used > by the eMMC (and this prevents either the SPI or the emmc controller > to probe, depending on which probed first). Argh, good catch! I saw that AW changed the pin sharing between SPI and MMC2 slightly, but didn't actually check that they made it worse :-( Because this time it's the MMC CMD pin affected, and not the somewhat optional DS pin as in the A64. So I see we can't really have both at the same time. So what about this: We keep the SPI flash chip described as in patch 2/2 (as it's soldered on every board), but mark it as disabled and explain this in a comment. This way we can't access it under Linux, but keep a potential eMMC chip accessible. In U-Boot's DT copy we could deviate and mark it as "okay", as U-Boot doesn't use both eMMC and SPI at the same time. I need to check whether this works or we would need to move the pinmux setup out of the probe routine into something later. And we could go one step further: If U-Boot detects an eMMC connected (it's on a socket and so optional), it changes the SPI flash status to "disabled", to allow EFI apps and kernels using this DT to access the eMMC - which is far more useful than the SPI flash. Otherwise (no eMMC connected) it can stay at "okay", as there would be no conflict. Does this make sense? Cheers, Andre. From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Date: Sun, 12 Jan 2020 15:12:19 +0000 Message-ID: References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> <20200111172639.to3lhzros6ca5hj2@gilmour.lan> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: Chen-Yu Tsai , Mark Brown , linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Icenowy Zheng , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Mark Rutland To: Maxime Ripard Return-path: In-Reply-To: <20200111172639.to3lhzros6ca5hj2-2DbqMqoCcjvhXIiyNabO3w@public.gmane.org> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-spi.vger.kernel.org On 11/01/2020 17:26, Maxime Ripard wrote: Hi Maxime, > On Wed, Jan 08, 2020 at 10:10:05AM +0000, Andre Przywara wrote: >> The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, >> but with the added capability of 3-wire and 4-wire operation modes. >> For now the driver does not support those, but the SPI registers are >> fully backwards-compatible, just adding bits and registers which were >> formerly reserved. So we can use the existing driver for the "normal" SPI >> modes, for instance to access the SPI NOR flash soldered on the PineH64 >> board. >> We use an H6 specific compatible string in addition to the existing H3 >> string, so when the driver later gains Quad SPI support, it should work >> automatically without any DT changes. >> >> Tested by accessing the SPI flash on a Pine H64 board (SPI0), also >> connecting another SPI flash to the SPI1 header pins. >> >> Signed-off-by: Andre Przywara >> --- >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> index 3329283e38ab..40835850893e 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> @@ -338,6 +338,30 @@ >> bias-pull-up; >> }; >> >> + /omit-if-no-ref/ >> + spi0_pins: spi0-pins { >> + pins = "PC0", "PC2", "PC3"; >> + function = "spi0"; >> + }; >> + >> + /omit-if-no-ref/ >> + spi0_cs_pin: spi0-cs-pin { >> + pins = "PC5"; >> + function = "spi0"; >> + }; > > It seems suspicious to use it in the Pine H64, since PC5 is also used > by the eMMC (and this prevents either the SPI or the emmc controller > to probe, depending on which probed first). Argh, good catch! I saw that AW changed the pin sharing between SPI and MMC2 slightly, but didn't actually check that they made it worse :-( Because this time it's the MMC CMD pin affected, and not the somewhat optional DS pin as in the A64. So I see we can't really have both at the same time. So what about this: We keep the SPI flash chip described as in patch 2/2 (as it's soldered on every board), but mark it as disabled and explain this in a comment. This way we can't access it under Linux, but keep a potential eMMC chip accessible. In U-Boot's DT copy we could deviate and mark it as "okay", as U-Boot doesn't use both eMMC and SPI at the same time. I need to check whether this works or we would need to move the pinmux setup out of the probe routine into something later. And we could go one step further: If U-Boot detects an eMMC connected (it's on a socket and so optional), it changes the SPI flash status to "disabled", to allow EFI apps and kernels using this DT to access the eMMC - which is far more useful than the SPI flash. Otherwise (no eMMC connected) it can stay at "okay", as there would be no conflict. Does this make sense? Cheers, Andre. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2963BC33CA2 for ; Sun, 12 Jan 2020 15:12:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5C0B214D8 for ; Sun, 12 Jan 2020 15:12:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lbVhU1o7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5C0B214D8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=c7euvxDM9ARnnkuwMTA7eyx63n/cN0Y34glU1+hSBto=; b=lbVhU1o7VIEfdS HLMUu1c51i23zXR7pp2tMBQfWds7CO9osW7TD2341VU7wXV+h18yYz9UL16cOdAEw96XTTJC7e57g WJ1Tdil99hQXCJoiWWml6Y56/SIsb8XAHbXwgA+u+UeTkIAsCKetoO3Wuf6gUacNt0L1lnACdAmxl x2c1WluFwKlwass3B9yHEk/HrCRTZ/5bUbNSrRJeGkZOMcVNJPpM1svTbvTIRX1j0F+aqMw/C7/LM RDY5DAanD4IBjSPcbfEHI/41+wfXCg3AKMA9J/9IquPTjfROpW/HDMMBqPyhUI2T1SmfdPJRom8lY dH0zbjbiuQoGwt5isWxg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iqeup-0006p0-6a; Sun, 12 Jan 2020 15:12:35 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iqeum-0006oh-Cy for linux-arm-kernel@lists.infradead.org; Sun, 12 Jan 2020 15:12:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51B7FDA7; Sun, 12 Jan 2020 07:12:29 -0800 (PST) Received: from [192.168.3.111] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CE9653F68E; Sun, 12 Jan 2020 07:12:27 -0800 (PST) Subject: Re: [PATCH 1/2] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes To: Maxime Ripard References: <20200108101006.150706-1-andre.przywara@arm.com> <20200108101006.150706-2-andre.przywara@arm.com> <20200111172639.to3lhzros6ca5hj2@gilmour.lan> From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Autocrypt: addr=andre.przywara@arm.com; prefer-encrypt=mutual; keydata= xsFNBFNPCKMBEAC+6GVcuP9ri8r+gg2fHZDedOmFRZPtcrMMF2Cx6KrTUT0YEISsqPoJTKld tPfEG0KnRL9CWvftyHseWTnU2Gi7hKNwhRkC0oBL5Er2hhNpoi8x4VcsxQ6bHG5/dA7ctvL6 kYvKAZw4X2Y3GTbAZIOLf+leNPiF9175S8pvqMPi0qu67RWZD5H/uT/TfLpvmmOlRzNiXMBm kGvewkBpL3R2clHquv7pB6KLoY3uvjFhZfEedqSqTwBVu/JVZZO7tvYCJPfyY5JG9+BjPmr+ REe2gS6w/4DJ4D8oMWKoY3r6ZpHx3YS2hWZFUYiCYovPxfj5+bOr78sg3JleEd0OB0yYtzTT esiNlQpCo0oOevwHR+jUiaZevM4xCyt23L2G+euzdRsUZcK/M6qYf41Dy6Afqa+PxgMEiDto ITEH3Dv+zfzwdeqCuNU0VOGrQZs/vrKOUmU/QDlYL7G8OIg5Ekheq4N+Ay+3EYCROXkstQnf YYxRn5F1oeVeqoh1LgGH7YN9H9LeIajwBD8OgiZDVsmb67DdF6EQtklH0ycBcVodG1zTCfqM AavYMfhldNMBg4vaLh0cJ/3ZXZNIyDlV372GmxSJJiidxDm7E1PkgdfCnHk+pD8YeITmSNyb 7qeU08Hqqh4ui8SSeUp7+yie9zBhJB5vVBJoO5D0MikZAODIDwARAQABzS1BbmRyZSBQcnp5 d2FyYSAoQVJNKSA8YW5kcmUucHJ6eXdhcmFAYXJtLmNvbT7CwXsEEwECACUCGwMGCwkIBwMC BhUIAgkKCwQWAgMBAh4BAheABQJTWSV8AhkBAAoJEAL1yD+ydue63REP/1tPqTo/f6StS00g NTUpjgVqxgsPWYWwSLkgkaUZn2z9Edv86BLpqTY8OBQZ19EUwfNehcnvR+Olw+7wxNnatyxo D2FG0paTia1SjxaJ8Nx3e85jy6l7N2AQrTCFCtFN9lp8Pc0LVBpSbjmP+Peh5Mi7gtCBNkpz KShEaJE25a/+rnIrIXzJHrsbC2GwcssAF3bd03iU41J1gMTalB6HCtQUwgqSsbG8MsR/IwHW XruOnVp0GQRJwlw07e9T3PKTLj3LWsAPe0LHm5W1Q+euoCLsZfYwr7phQ19HAxSCu8hzp43u zSw0+sEQsO+9wz2nGDgQCGepCcJR1lygVn2zwRTQKbq7Hjs+IWZ0gN2nDajScuR1RsxTE4WR lj0+Ne6VrAmPiW6QqRhliDO+e82riI75ywSWrJb9TQw0+UkIQ2DlNr0u0TwCUTcQNN6aKnru ouVt3qoRlcD5MuRhLH+ttAcmNITMg7GQ6RQajWrSKuKFrt6iuDbjgO2cnaTrLbNBBKPTG4oF D6kX8Zea0KvVBagBsaC1CDTDQQMxYBPDBSlqYCb/b2x7KHTvTAHUBSsBRL6MKz8wwruDodTM 4E4ToV9URl4aE/msBZ4GLTtEmUHBh4/AYwk6ACYByYKyx5r3PDG0iHnJ8bV0OeyQ9ujfgBBP B2t4oASNnIOeGEEcQ2rjzsFNBFNPCKMBEACm7Xqafb1Dp1nDl06aw/3O9ixWsGMv1Uhfd2B6 it6wh1HDCn9HpekgouR2HLMvdd3Y//GG89irEasjzENZPsK82PS0bvkxxIHRFm0pikF4ljIb 6tca2sxFr/H7CCtWYZjZzPgnOPtnagN0qVVyEM7L5f7KjGb1/o5EDkVR2SVSSjrlmNdTL2Rd zaPqrBoxuR/y/n856deWqS1ZssOpqwKhxT1IVlF6S47CjFJ3+fiHNjkljLfxzDyQXwXCNoZn BKcW9PvAMf6W1DGASoXtsMg4HHzZ5fW+vnjzvWiC4pXrcP7Ivfxx5pB+nGiOfOY+/VSUlW/9 GdzPlOIc1bGyKc6tGREH5lErmeoJZ5k7E9cMJx+xzuDItvnZbf6RuH5fg3QsljQy8jLlr4S6 8YwxlObySJ5K+suPRzZOG2+kq77RJVqAgZXp3Zdvdaov4a5J3H8pxzjj0yZ2JZlndM4X7Msr P5tfxy1WvV4Km6QeFAsjcF5gM+wWl+mf2qrlp3dRwniG1vkLsnQugQ4oNUrx0ahwOSm9p6kM CIiTITo+W7O9KEE9XCb4vV0ejmLlgdDV8ASVUekeTJkmRIBnz0fa4pa1vbtZoi6/LlIdAEEt PY6p3hgkLLtr2GRodOW/Y3vPRd9+rJHq/tLIfwc58ZhQKmRcgrhtlnuTGTmyUqGSiMNfpwAR AQABwsFfBBgBAgAJBQJTTwijAhsMAAoJEAL1yD+ydue64BgP/33QKczgAvSdj9XTC14wZCGE U8ygZwkkyNf021iNMj+o0dpLU48PIhHIMTXlM2aiiZlPWgKVlDRjlYuc9EZqGgbOOuR/pNYA JX9vaqszyE34JzXBL9DBKUuAui8z8GcxRcz49/xtzzP0kH3OQbBIqZWuMRxKEpRptRT0wzBL O31ygf4FRxs68jvPCuZjTGKELIo656/Hmk17cmjoBAJK7JHfqdGkDXk5tneeHCkB411p9WJU vMO2EqsHjobjuFm89hI0pSxlUoiTL0Nuk9Edemjw70W4anGNyaQtBq+qu1RdjUPBvoJec7y/ EXJtoGxq9Y+tmm22xwApSiIOyMwUi9A1iLjQLmngLeUdsHyrEWTbEYHd2sAM2sqKoZRyBDSv ejRvZD6zwkY/9nRqXt02H1quVOP42xlkwOQU6gxm93o/bxd7S5tEA359Sli5gZRaucpNQkwd KLQdCvFdksD270r4jU/rwR2R/Ubi+txfy0dk2wGBjl1xpSf0Lbl/KMR5TQntELfLR4etizLq Xpd2byn96Ivi8C8u9zJruXTueHH8vt7gJ1oax3yKRGU5o2eipCRiKZ0s/T7fvkdq+8beg9ku fDO4SAgJMIl6H5awliCY2zQvLHysS/Wb8QuB09hmhLZ4AifdHyF1J5qeePEhgTA+BaUbiUZf i4aIXCH3Wv6K Organization: ARM Ltd. Message-ID: Date: Sun, 12 Jan 2020 15:12:19 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.1 MIME-Version: 1.0 In-Reply-To: <20200111172639.to3lhzros6ca5hj2@gilmour.lan> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200112_071232_530725_BEB00FDA X-CRM114-Status: GOOD ( 23.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, Rob Herring , linux-spi@vger.kernel.org, Chen-Yu Tsai , Mark Brown , Icenowy Zheng , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/01/2020 17:26, Maxime Ripard wrote: Hi Maxime, > On Wed, Jan 08, 2020 at 10:10:05AM +0000, Andre Przywara wrote: >> The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, >> but with the added capability of 3-wire and 4-wire operation modes. >> For now the driver does not support those, but the SPI registers are >> fully backwards-compatible, just adding bits and registers which were >> formerly reserved. So we can use the existing driver for the "normal" SPI >> modes, for instance to access the SPI NOR flash soldered on the PineH64 >> board. >> We use an H6 specific compatible string in addition to the existing H3 >> string, so when the driver later gains Quad SPI support, it should work >> automatically without any DT changes. >> >> Tested by accessing the SPI flash on a Pine H64 board (SPI0), also >> connecting another SPI flash to the SPI1 header pins. >> >> Signed-off-by: Andre Przywara >> --- >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> index 3329283e38ab..40835850893e 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> @@ -338,6 +338,30 @@ >> bias-pull-up; >> }; >> >> + /omit-if-no-ref/ >> + spi0_pins: spi0-pins { >> + pins = "PC0", "PC2", "PC3"; >> + function = "spi0"; >> + }; >> + >> + /omit-if-no-ref/ >> + spi0_cs_pin: spi0-cs-pin { >> + pins = "PC5"; >> + function = "spi0"; >> + }; > > It seems suspicious to use it in the Pine H64, since PC5 is also used > by the eMMC (and this prevents either the SPI or the emmc controller > to probe, depending on which probed first). Argh, good catch! I saw that AW changed the pin sharing between SPI and MMC2 slightly, but didn't actually check that they made it worse :-( Because this time it's the MMC CMD pin affected, and not the somewhat optional DS pin as in the A64. So I see we can't really have both at the same time. So what about this: We keep the SPI flash chip described as in patch 2/2 (as it's soldered on every board), but mark it as disabled and explain this in a comment. This way we can't access it under Linux, but keep a potential eMMC chip accessible. In U-Boot's DT copy we could deviate and mark it as "okay", as U-Boot doesn't use both eMMC and SPI at the same time. I need to check whether this works or we would need to move the pinmux setup out of the probe routine into something later. And we could go one step further: If U-Boot detects an eMMC connected (it's on a socket and so optional), it changes the SPI flash status to "disabled", to allow EFI apps and kernels using this DT to access the eMMC - which is far more useful than the SPI flash. Otherwise (no eMMC connected) it can stay at "okay", as there would be no conflict. Does this make sense? Cheers, Andre. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel