From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 619DEC4167B for ; Fri, 16 Dec 2022 20:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229583AbiLPUxd (ORCPT ); Fri, 16 Dec 2022 15:53:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231283AbiLPUxb (ORCPT ); Fri, 16 Dec 2022 15:53:31 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A743757B6B; Fri, 16 Dec 2022 12:53:30 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BGJBBgr024824; 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Fri, 16 Dec 2022 20:53:10 GMT Received: from [10.110.127.101] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 16 Dec 2022 12:53:08 -0800 Message-ID: Date: Fri, 16 Dec 2022 12:53:08 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [RFC PATCH 2/6] drm/msm/dpu1: Add DSC config for sm8150 and sm8250 Content-Language: en-US To: Marijn Suijten , , Rob Clark , "Dmitry Baryshkov" , Vinod Koul CC: <~postmarketos/upstreaming@lists.sr.ht>, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , Sean Paul , David Airlie , Daniel Vetter , "Stephen Boyd" , Bjorn Andersson , "Jessica Zhang" , =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= , Kuogee Hsieh , "Jani Nikula" , sunliming , "Sam Ravnborg" , Haowen Bai , Konrad Dybcio , Loic Poulain , "Vinod Polimera" , Douglas Anderson , Vladimir Lypak , , , , References: <20221213232207.113607-1-marijn.suijten@somainline.org> <20221213232207.113607-3-marijn.suijten@somainline.org> From: Abhinav Kumar In-Reply-To: <20221213232207.113607-3-marijn.suijten@somainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1bRcK7Mx4X9HduAcyW6FAX9RncDD9be6 X-Proofpoint-ORIG-GUID: 1bRcK7Mx4X9HduAcyW6FAX9RncDD9be6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-16_14,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212160185 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 12/13/2022 3:22 PM, Marijn Suijten wrote: > These blocks on CTL V1 support setting a PINGPONG idx to send pixel > output to. > > Signed-off-by: Marijn Suijten Reviewed-by: Abhinav Kumar > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 23 ++++++++++++++----- > 1 file changed, 17 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 318f0b4dbf6e..114ad8ca4554 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -1566,18 +1566,25 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > /************************************************************* > * DSC sub blocks config > *************************************************************/ > -#define DSC_BLK(_name, _id, _base) \ > +#define DSC_BLK(_name, _id, _base, _features) \ > {\ > .name = _name, .id = _id, \ > .base = _base, .len = 0x140, \ > - .features = 0, \ > + .features = _features, \ > } > > static struct dpu_dsc_cfg sdm845_dsc[] = { > - DSC_BLK("dsc_0", DSC_0, 0x80000), > - DSC_BLK("dsc_1", DSC_1, 0x80400), > - DSC_BLK("dsc_2", DSC_2, 0x80800), > - DSC_BLK("dsc_3", DSC_3, 0x80c00), > + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), > + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), > + DSC_BLK("dsc_2", DSC_2, 0x80800, 0), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), > +}; > + > +static struct dpu_dsc_cfg sm8150_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), > }; > > /************************************************************* > @@ -2474,6 +2481,8 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { > .mixer = sm8150_lm, > .dspp_count = ARRAY_SIZE(sm8150_dspp), > .dspp = sm8150_dspp, > + .dsc_count = ARRAY_SIZE(sm8150_dsc), > + .dsc = sm8150_dsc, > .pingpong_count = ARRAY_SIZE(sm8150_pp), > .pingpong = sm8150_pp, > .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), > @@ -2524,6 +2533,8 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mixer = sm8150_lm, > .dspp_count = ARRAY_SIZE(sm8150_dspp), > .dspp = sm8150_dspp, > + .dsc_count = ARRAY_SIZE(sm8150_dsc), > + .dsc = sm8150_dsc, > .pingpong_count = ARRAY_SIZE(sm8150_pp), > .pingpong = sm8150_pp, > .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D1C2C4332F for ; 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Fri, 16 Dec 2022 20:53:12 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BGKrAx7004922 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Dec 2022 20:53:10 GMT Received: from [10.110.127.101] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 16 Dec 2022 12:53:08 -0800 Message-ID: Date: Fri, 16 Dec 2022 12:53:08 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [RFC PATCH 2/6] drm/msm/dpu1: Add DSC config for sm8150 and sm8250 Content-Language: en-US To: Marijn Suijten , , Rob Clark , "Dmitry Baryshkov" , Vinod Koul References: <20221213232207.113607-1-marijn.suijten@somainline.org> <20221213232207.113607-3-marijn.suijten@somainline.org> From: Abhinav Kumar In-Reply-To: <20221213232207.113607-3-marijn.suijten@somainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1bRcK7Mx4X9HduAcyW6FAX9RncDD9be6 X-Proofpoint-ORIG-GUID: 1bRcK7Mx4X9HduAcyW6FAX9RncDD9be6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-16_14,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212160185 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , Vinod Polimera , Sam Ravnborg , Haowen Bai , Kuogee Hsieh , Jessica Zhang , Jani Nikula , linux-arm-msm@vger.kernel.org, Stephen Boyd , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Sean Paul , Loic Poulain , Jami Kettunen , Bjorn Andersson , Vladimir Lypak , Douglas Anderson , Konrad Dybcio , sunliming , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 12/13/2022 3:22 PM, Marijn Suijten wrote: > These blocks on CTL V1 support setting a PINGPONG idx to send pixel > output to. > > Signed-off-by: Marijn Suijten Reviewed-by: Abhinav Kumar > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 23 ++++++++++++++----- > 1 file changed, 17 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 318f0b4dbf6e..114ad8ca4554 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -1566,18 +1566,25 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > /************************************************************* > * DSC sub blocks config > *************************************************************/ > -#define DSC_BLK(_name, _id, _base) \ > +#define DSC_BLK(_name, _id, _base, _features) \ > {\ > .name = _name, .id = _id, \ > .base = _base, .len = 0x140, \ > - .features = 0, \ > + .features = _features, \ > } > > static struct dpu_dsc_cfg sdm845_dsc[] = { > - DSC_BLK("dsc_0", DSC_0, 0x80000), > - DSC_BLK("dsc_1", DSC_1, 0x80400), > - DSC_BLK("dsc_2", DSC_2, 0x80800), > - DSC_BLK("dsc_3", DSC_3, 0x80c00), > + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), > + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), > + DSC_BLK("dsc_2", DSC_2, 0x80800, 0), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), > +}; > + > +static struct dpu_dsc_cfg sm8150_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), > }; > > /************************************************************* > @@ -2474,6 +2481,8 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = { > .mixer = sm8150_lm, > .dspp_count = ARRAY_SIZE(sm8150_dspp), > .dspp = sm8150_dspp, > + .dsc_count = ARRAY_SIZE(sm8150_dsc), > + .dsc = sm8150_dsc, > .pingpong_count = ARRAY_SIZE(sm8150_pp), > .pingpong = sm8150_pp, > .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), > @@ -2524,6 +2533,8 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mixer = sm8150_lm, > .dspp_count = ARRAY_SIZE(sm8150_dspp), > .dspp = sm8150_dspp, > + .dsc_count = ARRAY_SIZE(sm8150_dsc), > + .dsc = sm8150_dsc, > .pingpong_count = ARRAY_SIZE(sm8150_pp), > .pingpong = sm8150_pp, > .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),