Re: [PATCH v2 1/2] net/mlx5: add enhanced multi-packet send for ConnectX-5

From: Ferruh Yigit <ferruh.yigit@intel.com>
To: Yongseok Koh <yskoh@mellanox.com>
Cc: dev@dpdk.org, adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com
Subject: Re: [PATCH v2 1/2] net/mlx5: add enhanced multi-packet send for ConnectX-5
Date: Wed, 15 Mar 2017 14:28:01 +0000	[thread overview]
Message-ID: <cefea552-45ae-03c3-6520-ce3583c8a606@intel.com> (raw)
In-Reply-To: <20170310231334.2457-2-yskoh@mellanox.com>

On 3/10/2017 11:13 PM, Yongseok Koh wrote:
> ConnectX-5 supports enhanced version of multi-packet send (MPS). An MPS Tx
> descriptor can carry multiple packets either by including pointers of
> packets or by inlining packets. Inlining packet data can be helpful to
> better utilize PCIe bandwidth. In addition, Enhanced MPS supports hybrid
> mode - mixing inlined packets and pointers in a descriptor. This feature is
> enabled by default if supported by HW.
> 
> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
<...>

> +		uintptr_t addr;

<...>

> +			addr = htonll(addr);
> +			*dseg = (rte_v128u32_t) {
> +				htonl(length),
> +				txq_mp2mr(txq, txq_mb2mp(buf)),
> +				addr,
> +				addr >> 32,

This creates build error for 32bit target:

...drivers/net/mlx5/mlx5_rxtx.c: In function ‘mlx5_tx_burst_empw’:
...drivers/net/mlx5/mlx5_rxtx.c:1630:10:
error: right shift count >= width of type [-Werror=shift-count-overflow]
     addr >> 32,
          ^~