From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0094BC433EF for ; Sun, 15 May 2022 14:46:54 +0000 (UTC) Received: from localhost ([::1]:39994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqFWH-0000Nc-Qu for qemu-devel@archiver.kernel.org; Sun, 15 May 2022 10:46:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqFV1-0007zb-8b; Sun, 15 May 2022 10:45:36 -0400 Received: from mail-sender-0.a4lg.com ([2401:2500:203:30b:4000:6bfe:4757:0]:48490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqFUw-0000Wb-Ff; Sun, 15 May 2022 10:45:34 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4F773300089; Sun, 15 May 2022 14:45:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652625920; bh=MScmeQ+XDoeosLgefl1nfQ0+2TMf3yH5haXzW8IDIgA=; h=Message-ID:Date:Mime-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=hmRzKsCx2pUqfMq7u1NmOg3StOwHm1Cn4GQdYV6s9mR/ugxR7hDGGPEOaK+39XlCc 8w+ZmZAdAikXIRFuMoo1E+YZQep/zJzimkVE3aAWHD3xgQCfyCQsO+Wz+xmTUVdN+W 6iHGp4U7fm+nOnAP+QkLTo0zON08MxTOW8mLqcXk= Message-ID: Date: Sun, 15 May 2022 23:45:18 +0900 Mime-Version: 1.0 Subject: Re: [PATCH v2 4/5] target/riscv: FP extension requirements Content-Language: en-US To: Weiwei Li , Alistair Francis , Frank Chang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com> From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2401:2500:203:30b:4000:6bfe:4757:0; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2022/05/15 23:37, Weiwei Li wrote: > > 在 2022/5/15 上午10:56, Tsukasa OI 写道: >> QEMU allowed inconsistent configurations that made floating point >> arithmetic effectively unusable. >> >> This commit adds certain checks for consistent FP arithmetic: >> >> -   F requires Zicsr >> -   Zfinx requires Zicsr >> -   Zfh/Zfhmin require F >> -   D requires F >> -   V requires D > > Why 'V requires D'? I know partial vector instructions require D, However,  I think they  just like c.fsd > > instruction requires D, not 'C requires D' or 'D requires C'. Is there any rvv spec change I don't know? I thought it was crystal-clear. RISC-V "V" Vector Extension Version 1.0 (riscv-v-spec-1.0.pdf) 18.3. V: Vector Extension for Application Processors Page 94: > The V extension requires the scalar processor implements the F and D > extensions, and implements all vector floating-point instructions > (Section Vector Floating-Point Instructions) for floating-point operands > with EEW=32 or EEW=64 (including widening instructions and conversions > between FP32 and FP64). c.f. Thanks, Tsukasa > > Regards. > > Weiwei Li > >> >> Because F/D/Zicsr are enabled by default (and an error will not occur unless >> we manually disable one or more of prerequisites), this commit just enforces >> the user to give consistent combinations. >> >> Signed-off-by: Tsukasa OI >> --- >>   target/riscv/cpu.c | 25 +++++++++++++++++++++++++ >>   1 file changed, 25 insertions(+) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 0854ca9103..f910a41407 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -610,11 +610,36 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) >>               cpu->cfg.ext_ifencei = true; >>           } >>   +        if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { >> +            error_setg(errp, "F extension requires Zicsr"); >> +            return; >> +        } >> + >> +        if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { >> +            error_setg(errp, "Zfh/Zfhmin extensions require F extension"); >> +            return; >> +        } >> + >> +        if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { >> +            error_setg(errp, "D extension requires F extension"); >> +            return; >> +        } >> + >> +        if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { >> +            error_setg(errp, "V extension requires D extension"); >> +            return; >> +        } >> + >>           if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || >>               cpu->cfg.ext_zhinxmin) { >>               cpu->cfg.ext_zfinx = true; >>           } >>   +        if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) { >> +            error_setg(errp, "Zfinx extension requires Zicsr"); >> +            return; >> +        } >> + >>           if (cpu->cfg.ext_zk) { >>               cpu->cfg.ext_zkn = true; >>               cpu->cfg.ext_zkr = true; >