[Qemu-devel] [PATCH v1 0/4] Petercs target-arm queue

[Qemu-devel] [PATCH v1 0/4] Petercs target-arm queue

[peter.crosthwaite]

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Hi Peter,

Heres is a mixed bag of target-arm patches from my tree. They are
independent of each other and only threaded together for review
convenience.

Regards,
Peter


Nathan Rossi (1):
  target-arm: Add CP15 VBAR support

Peter Crosthwaite (3):
  target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
  target-arm/helper.c: Implement MIDR aliases
  target-arm/helper.c: Allow const opaques in arm CP

 target-arm/cpu.h    |  1 +
 target-arm/helper.c | 55 ++++++++++++++++++++++++++++++++++++++---------------
 2 files changed, 41 insertions(+), 15 deletions(-)

-- 
1.8.3.rc1.44.gb387c77.dirty

[Qemu-devel] [PATCH v1 1/4] target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup

[peter.crosthwaite]

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

The if block detecting OMAP/StrongARM modifies the id_cp_reginfo
.access fields in place. So there is no need to replicate the call
to define_arm_cp_reg(). Dropped, and let the OMAP case fall through
to the normal behaviour after the in-place modification.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/helper.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5f639fd..47e6c09 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1435,21 +1435,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             arm_feature(env, ARM_FEATURE_STRONGARM)) {
             ARMCPRegInfo *r;
             /* Register the blanket "writes ignored" value first to cover the
-             * whole space. Then define the specific ID registers, but update
-             * their access field to allow write access, so that they ignore
-             * writes rather than causing them to UNDEF.
+             * whole space. Then update the specific ID registers to allow write
+             * access, so that they ignore writes rather than causing them to
+             * UNDEF.
              */
             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
                 r->access = PL1_RW;
-                define_one_arm_cp_reg(cpu, r);
             }
-        } else {
-            /* Just register the standard ID registers (read-only, meaning
-             * that writes will UNDEF).
-             */
-            define_arm_cp_regs(cpu, id_cp_reginfo);
         }
+        define_arm_cp_regs(cpu, id_cp_reginfo);
     }
 
     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
-- 
1.8.3.rc1.44.gb387c77.dirty

[Qemu-devel] [PATCH v1 2/4] target-arm/helper.c: Implement MIDR aliases

[peter.crosthwaite]

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default
to aliasing the MIDR register. Set all registers in the space to access
MIDR by default.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/helper.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 47e6c09..6f0a87e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1378,9 +1378,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
     }
-    if (arm_feature(env, ARM_FEATURE_MPIDR)) {
-        define_arm_cp_regs(cpu, mpidr_cp_reginfo);
-    }
     if (arm_feature(env, ARM_FEATURE_LPAE)) {
         define_arm_cp_regs(cpu, lpae_cp_reginfo);
     }
@@ -1393,12 +1390,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             /* Note that the MIDR isn't a simple constant register because
              * of the TI925 behaviour where writes to another register can
              * cause the MIDR value to change.
+             *
+             * Unimlplemented register in the c15 0 0 0 space default to
+             * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
+             * and friends override accordingly.
              */
             { .name = "MIDR",
-              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
+              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
               .access = PL1_R, .resetvalue = cpu->midr,
               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
-              .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) },
+              .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
+              .type = ARM_CP_OVERRIDE },
             { .name = "CTR",
               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
@@ -1447,6 +1449,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, id_cp_reginfo);
     }
 
+    if (arm_feature(env, ARM_FEATURE_MPIDR)) {
+        define_arm_cp_regs(cpu, mpidr_cp_reginfo);
+    }
+
     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
         ARMCPRegInfo auxcr = {
             .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
-- 
1.8.3.rc1.44.gb387c77.dirty

[Qemu-devel] [PATCH v1 3/4] target-arm/helper.c: Allow const opaques in arm CP

[peter.crosthwaite]

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Allow for defining const opaque data in ARM CP register definitions by
setting .opaque = foo. If non null opaque is passes into
define_one_arm_cp_reg_with_opaque then that opaque will take
precedence, otherwise if null opaque is passed, the original opaque
data will be used.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f0a87e..f8b9ef4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1608,7 +1608,9 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
                 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
                 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
-                r2->opaque = opaque;
+                if (opaque) {
+                    r2->opaque = opaque;
+                }
                 /* Make sure reginfo passed to helpers for wildcarded regs
                  * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
                  */
-- 
1.8.3.rc1.44.gb387c77.dirty

[Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[peter.crosthwaite]

From: Nathan Rossi <nathan.rossi@xilinx.com>

Added Vector Base Address remapping on ARM v7.

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed since v1:
Removed obsolete VMSD logic (rebase)
Forced lower 5 bits of VBAR ro 0 (PMM review)
Simplified if-else logic to not worry about pre-v7 (PMM review)

 target-arm/cpu.h    |  1 +
 target-arm/helper.c | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index abcc0b4..f27ccd5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -138,6 +138,7 @@ typedef struct CPUARMState {
         uint32_t c9_pmxevtyper; /* perf monitor event type */
         uint32_t c9_pmuserenr; /* perf monitor user enable */
         uint32_t c9_pminten; /* perf monitor interrupt enables */
+        uint32_t c12_vbar; /* vector base address register */
         uint32_t c13_fcse; /* FCSE PID.  */
         uint32_t c13_context; /* Context ID.  */
         uint32_t c13_tls1; /* User RW Thread register.  */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f8b9ef4..4e88754 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -520,6 +520,14 @@ static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     return 0;
 }
 
+static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                      uint64_t value)
+{
+    value &= (1 << 31);
+    env->cp15.c12_vbar = value & ~0x1Ful;
+    return 0;
+}
+
 static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t *value)
 {
@@ -605,6 +613,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .resetvalue = 0, .writefn = pmintenclr_write, },
+    { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
+      .access = PL1_RW, .writefn = vbar_write,
+      .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
+      .resetvalue = 0 },
     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
       .resetvalue = 0, },
@@ -2134,7 +2146,17 @@ void arm_cpu_do_interrupt(CPUState *cs)
     }
     /* High vectors.  */
     if (env->cp15.c1_sys & (1 << 13)) {
+        /* when enabled, base address cannot be remapped.  */
         addr += 0xffff0000;
+    } else {
+        /* ARM v7 architectures provide a vector base address register to remap
+         * the interrupt vector table.
+         * This register is only followed in non-monitor mode, and has a secure
+         * and un-secure copy. Since the cpu is always in a un-secure operation
+         * and is never in monitor mode this feature is always active.
+         * Note: only bits 31:5 are valid.
+         */
+        addr += env->cp15.c12_vbar;
     }
     switch_mode (env, new_mode);
     env->spsr = cpsr_read(env);
-- 
1.8.3.rc1.44.gb387c77.dirty

Re: [Qemu-devel] [PATCH v1 3/4] target-arm/helper.c: Allow const opaques in arm CP

[Peter Maydell]

On 10 July 2013 05:22,  <peter.crosthwaite@xilinx.com> wrote:
> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>
> Allow for defining const opaque data in ARM CP register definitions by
> setting .opaque = foo. If non null opaque is passes into
> define_one_arm_cp_reg_with_opaque then that opaque will take
> precedence, otherwise if null opaque is passed, the original opaque
> data will be used.

This doesn't seem to have any motivating use in later
patches in the series, or did I miss it? I guess being able
to have the opaque data in the data-tables is nice, though.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 3/4] target-arm/helper.c: Allow const opaques in arm CP

[Peter Crosthwaite]

Hi Peter,

On Wed, Jul 10, 2013 at 5:32 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 10 July 2013 05:22,  <peter.crosthwaite@xilinx.com> wrote:
>> From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>>
>> Allow for defining const opaque data in ARM CP register definitions by
>> setting .opaque = foo. If non null opaque is passes into
>> define_one_arm_cp_reg_with_opaque then that opaque will take
>> precedence, otherwise if null opaque is passed, the original opaque
>> data will be used.
>
> This doesn't seem to have any motivating use in later
> patches in the series, or did I miss it? I guess being able
> to have the opaque data in the data-tables is nice, though.
>

No on-list motivation but I thought I might send this through to get
opinion on its validity before I start relying on it out of tree.

Regards,
peter

> thanks
> -- PMM
>

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Maydell]

On 10 July 2013 05:23,  <peter.crosthwaite@xilinx.com> wrote:
> From: Nathan Rossi <nathan.rossi@xilinx.com>
>
> Added Vector Base Address remapping on ARM v7.

This is only present on CPUs with TrustZone. On the other
hand we already implement one or two TZ-only registers
for pragmatic get-code-working reasons. I'll try to find
time over the next day or two for a more careful think
about what we should do here.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Crosthwaite]

Ping!

On Wed, Jul 10, 2013 at 5:38 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 10 July 2013 05:23,  <peter.crosthwaite@xilinx.com> wrote:
>> From: Nathan Rossi <nathan.rossi@xilinx.com>
>>
>> Added Vector Base Address remapping on ARM v7.
>
> This is only present on CPUs with TrustZone. On the other
> hand we already implement one or two TZ-only registers
> for pragmatic get-code-working reasons.

Does this perhaps just fall in that basket? I have guests that are
broken without this and would like to fix mainline.

> I'll try to find
> time over the next day or two for a more careful think
> about what we should do here.
>

Any further thoughts? Can we perhaps /* FIXME: */ merge this (perhaps
even FIXME: flag the other TZ specific regs along with it) and come
back to it 1.7?

Regards,
Peter

> thanks
> -- PMM
>

Re: [Qemu-devel] [PATCH v1 0/4] Petercs target-arm queue

[Peter Maydell]

On 10 July 2013 05:21,  <peter.crosthwaite@xilinx.com> wrote:
> Heres is a mixed bag of target-arm patches from my tree. They are
> independent of each other and only threaded together for review
> convenience.

Applied 1-3 to target-arm.next, thanks (the VBAR one I
still need to think about.)

-- PMM

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Sebastian Huber]

Hello,

it would be really nice to get the CP15 VBAR support integrated.  This allows 
unit test suites of single address space real-time systems to catch NULL 
pointer read/write access for example.

The ARM documentation says that this is a banked register that is only present 
in an implementation that includes the Security Extensions.  Is this equivalent 
to having TrustZone?

In the ID_PFR1, Processor Feature Register 1, the bits [4:7] indicate if a 
particular CPU has this feature.  Is it possible to use this register to 
determine the availability of the VBAR register in Qemu?  This may avoid adding 
a new enum arm_features.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Sebastian Huber]

On 2013-07-10 06:23, peter.crosthwaite@xilinx.com wrote:
> +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
> +                      uint64_t value)
> +{
> +    value &= (1 << 31);

Is the above correct?

> +    env->cp15.c12_vbar = value & ~0x1Ful;
> +    return 0;
> +}

Shouldn't this be

{
   env->cp15.c12_vbar = (uint32_t) (value & ~0x1FUL);
   return 0;
}

?

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Maydell]

On 16 September 2013 16:34, Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
> it would be really nice to get the CP15 VBAR support integrated.  This
> allows unit test suites of single address space real-time systems to catch
> NULL pointer read/write access for example.

I agree it would be useful. As I said, it needs thought about whether
it makes sense to add it.

> The ARM documentation says that this is a banked register that is only
> present in an implementation that includes the Security Extensions.  Is this
> equivalent to having TrustZone?

Yes; the ARM ARM uses the term "Security Extensions" but this is
interchangeable with TrustZone.

> In the ID_PFR1, Processor Feature Register 1, the bits [4:7] indicate if a
> particular CPU has this feature.  Is it possible to use this register to
> determine the availability of the VBAR register in Qemu?  This may avoid
> adding a new enum arm_features.

Unfortunately QEMU tends to not pass the right values in the PFRs:
we usually report what the real h/w CPU has even if we don't implement
everything.

In any case a new arm_features bit is hardly a big deal: the actual
question is whether it makes sense to provide this register that
shouldn't really exist for the cpu configurations we're modelling.

-- PMM

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Sebastian Huber]

On 2013-09-17 10:37, Peter Maydell wrote:
> In any case a new arm_features bit is hardly a big deal: the actual
> question is whether it makes sense to provide this register that
> shouldn't really exist for the cpu configurations we're modelling.

I use Qemu to run unit tests for a real-time operating system that runs on real 
Xilinx Zynq or Altera Cyclone-V for example.  Both systems use an ARM 
Cortex-A9MPCore with Security Extensions.  The operating system will run in 
secure mode all the time within a single address space and one-to-one mapped 
addresses.  Everything we use from this Security Extensions is the VBAR.  So 
for me the only missing Qemu feature is the VBAR if I want to use nearly the 
same binary on Qemu and the real hardware.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Maydell]

On 10 July 2013 05:23,  <peter.crosthwaite@xilinx.com> wrote:
> From: Nathan Rossi <nathan.rossi@xilinx.com>
>
> Added Vector Base Address remapping on ARM v7.

Apologies for this dropping off my radar for so long.
I've had a bit of a think and I think that you're right
that we can put in this register as part of our "random
things we provide even though we aren't strictly implementing
all of TZ", like the existing SCR register support.

> +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
> +                      uint64_t value)
> +{
> +    value &= (1 << 31);

This seems spurious -- we end up ignoring all but
the high bit of the written value.

> +    env->cp15.c12_vbar = value & ~0x1Ful;
> +    return 0;
> +}
> +

Otherwise looks OK. We should probably put in an ARM_FEATURE_TZ
at some point, but for now putting it in the v7 regs with SCR is
OK I think.

-- PMM

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Maydell]

On 17 October 2013 11:38, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 10 July 2013 05:23,  <peter.crosthwaite@xilinx.com> wrote:
>> From: Nathan Rossi <nathan.rossi@xilinx.com>
>>
>> Added Vector Base Address remapping on ARM v7.
>
> Apologies for this dropping off my radar for so long.
> I've had a bit of a think and I think that you're right
> that we can put in this register as part of our "random
> things we provide even though we aren't strictly implementing
> all of TZ", like the existing SCR register support.
>
>> +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> +                      uint64_t value)
>> +{
>> +    value &= (1 << 31);
>
> This seems spurious -- we end up ignoring all but
> the high bit of the written value.
>
>> +    env->cp15.c12_vbar = value & ~0x1Ful;
>> +    return 0;
>> +}
>> +
>
> Otherwise looks OK.

Update: I've removed the spurious mask line noted above
and added the edited patch to target-arm.next.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Crosthwaite]

Hi,

> -----Original Message-----
> From: Peter Maydell [mailto:peter.maydell@linaro.org]
> Sent: Saturday, October 19, 2013 12:06 AM
> To: Peter Crosthwaite
> Cc: QEMU Developers
> Subject: Re: [PATCH v1 4/4] target-arm: Add CP15 VBAR support
>
> On 17 October 2013 11:38, Peter Maydell <peter.maydell@linaro.org> wrote:
> > On 10 July 2013 05:23,  <peter.crosthwaite@xilinx.com> wrote:
> >> From: Nathan Rossi <nathan.rossi@xilinx.com>
> >>
> >> Added Vector Base Address remapping on ARM v7.
> >
> > Apologies for this dropping off my radar for so long.
> > I've had a bit of a think and I think that you're right that we can
> > put in this register as part of our "random things we provide even
> > though we aren't strictly implementing all of TZ", like the existing
> > SCR register support.
> >
> >> +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
> >> +                      uint64_t value) {
> >> +    value &= (1 << 31);
> >
> > This seems spurious -- we end up ignoring all but the high bit of the
> > written value.
> >
> >> +    env->cp15.c12_vbar = value & ~0x1Ful;
> >> +    return 0;
> >> +}
> >> +
> >
> > Otherwise looks OK.
>
> Update: I've removed the spurious mask line noted above and added the edited
> patch to target-arm.next.
>

Thanks Peter,

Sorry about the delays my end.

Regards,
Peter

> thanks
> -- PMM



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Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Roy Franz]

On Fri, Oct 18, 2013 at 7:05 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 17 October 2013 11:38, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 10 July 2013 05:23,  <peter.crosthwaite@xilinx.com> wrote:
>>> From: Nathan Rossi <nathan.rossi@xilinx.com>
>>>
>>> Added Vector Base Address remapping on ARM v7.
>>
>> Apologies for this dropping off my radar for so long.
>> I've had a bit of a think and I think that you're right
>> that we can put in this register as part of our "random
>> things we provide even though we aren't strictly implementing
>> all of TZ", like the existing SCR register support.
>>
>>> +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
>>> +                      uint64_t value)
>>> +{
>>> +    value &= (1 << 31);
>>
>> This seems spurious -- we end up ignoring all but
>> the high bit of the written value.
>>
>>> +    env->cp15.c12_vbar = value & ~0x1Ful;
>>> +    return 0;
>>> +}
>>> +
>>
>> Otherwise looks OK.
>
> Update: I've removed the spurious mask line noted above
> and added the edited patch to target-arm.next.
>
> thanks
> -- PMM
>

Hi Peter,

   Glad to see this go in.  Is your target-arm.next branch available
in a public repo?
I found one on git.linaro.org but that is out of date.

Thanks,
Roy

Re: [Qemu-devel] [PATCH v1 4/4] target-arm: Add CP15 VBAR support

[Peter Maydell]

On 19 October 2013 00:38, Roy Franz <roy.franz@linaro.org> wrote:
>    Glad to see this go in.  Is your target-arm.next branch available
> in a public repo?

No, not generally.

-- PMM