* [PATCH v5 0/2] Add freescale S/PDIF CPU DAI and machine drivers
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: linuxppc-dev, alsa-devel, devicetree, timur, rob.herring,
shawn.guo, festevam
Changelog:
v4->v5:
* Dropped rx/tx-clksrc-names DT bindings.
* Use standard clock binding instead to pass the clock source list.
* Update the compatible list by using "imx35", the first SoC that has spdif.
v3->v4:
* Use regmap for CPU DAI driver.
* Use individual clock source for 32KHz, 44KHz, 48KHz playback.
* Determine clock source configuration from 'clocks' entry.
* Added imx53 to compatible list, merged imx6q and imx6dl in the list.
* Improve the algorism of reverse_bits().
* Dropped the unneeded clk_put().
v2->v3:
* Removed a wrong tag from the commit of patch-1.
v1->v2:
* Dropped one applied patch for spdif dummy codec drivers.
* Use generic DMA DT binding.
* Let spdif controller driver calculate the clock div.
* Added one optional clock source for spdif tx.
* Reivsed documentation accordingly.
Nicolin Chen (2):
ASoC: fsl: Add S/PDIF CPU DAI driver
ASoC: fsl: Add S/PDIF machine driver
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +
sound/soc/fsl/Kconfig | 14 +
sound/soc/fsl/Makefile | 4 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
sound/soc/fsl/imx-spdif.c | 134 ++
7 files changed, 1817 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
create mode 100644 sound/soc/fsl/imx-spdif.c
^ permalink raw reply [flat|nested] 77+ messages in thread
* [PATCH v5 0/2] Add freescale S/PDIF CPU DAI and machine drivers
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
Changelog:
v4->v5:
* Dropped rx/tx-clksrc-names DT bindings.
* Use standard clock binding instead to pass the clock source list.
* Update the compatible list by using "imx35", the first SoC that has spdif.
v3->v4:
* Use regmap for CPU DAI driver.
* Use individual clock source for 32KHz, 44KHz, 48KHz playback.
* Determine clock source configuration from 'clocks' entry.
* Added imx53 to compatible list, merged imx6q and imx6dl in the list.
* Improve the algorism of reverse_bits().
* Dropped the unneeded clk_put().
v2->v3:
* Removed a wrong tag from the commit of patch-1.
v1->v2:
* Dropped one applied patch for spdif dummy codec drivers.
* Use generic DMA DT binding.
* Let spdif controller driver calculate the clock div.
* Added one optional clock source for spdif tx.
* Reivsed documentation accordingly.
Nicolin Chen (2):
ASoC: fsl: Add S/PDIF CPU DAI driver
ASoC: fsl: Add S/PDIF machine driver
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +
sound/soc/fsl/Kconfig | 14 +
sound/soc/fsl/Makefile | 4 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
sound/soc/fsl/imx-spdif.c | 134 ++
7 files changed, 1817 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
create mode 100644 sound/soc/fsl/imx-spdif.c
^ permalink raw reply [flat|nested] 77+ messages in thread
* [PATCH v5 0/2] Add freescale S/PDIF CPU DAI and machine drivers
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
Changelog:
v4->v5:
* Dropped rx/tx-clksrc-names DT bindings.
* Use standard clock binding instead to pass the clock source list.
* Update the compatible list by using "imx35", the first SoC that has spdif.
v3->v4:
* Use regmap for CPU DAI driver.
* Use individual clock source for 32KHz, 44KHz, 48KHz playback.
* Determine clock source configuration from 'clocks' entry.
* Added imx53 to compatible list, merged imx6q and imx6dl in the list.
* Improve the algorism of reverse_bits().
* Dropped the unneeded clk_put().
v2->v3:
* Removed a wrong tag from the commit of patch-1.
v1->v2:
* Dropped one applied patch for spdif dummy codec drivers.
* Use generic DMA DT binding.
* Let spdif controller driver calculate the clock div.
* Added one optional clock source for spdif tx.
* Reivsed documentation accordingly.
Nicolin Chen (2):
ASoC: fsl: Add S/PDIF CPU DAI driver
ASoC: fsl: Add S/PDIF machine driver
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +
sound/soc/fsl/Kconfig | 14 +
sound/soc/fsl/Makefile | 4 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
sound/soc/fsl/imx-spdif.c | 134 ++
7 files changed, 1817 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
create mode 100644 sound/soc/fsl/imx-spdif.c
^ permalink raw reply [flat|nested] 77+ messages in thread
* [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-15 11:26 ` Nicolin Chen
(?)
@ 2013-08-15 11:26 ` Nicolin Chen
-1 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: linuxppc-dev, alsa-devel, devicetree, timur, rob.herring,
shawn.guo, festevam
This patch add S/PDIF controller driver for Freescale SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
sound/soc/fsl/Kconfig | 3 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
5 files changed, 1641 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
new file mode 100644
index 0000000..301b827
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -0,0 +1,76 @@
+Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
+
+The Freescale S/PDIF audio block is a stereo transceiver that allows the
+processor to receive and transmit digital audio via an coaxial cable or
+a fibre cable.
+
+Required properties:
+
+ - compatible : Compatible list, contains "fsl,<chip>-spdif".
+
+ - reg : Offset and length of the register set for the device.
+
+ - interrupts : Contains spdif interrupt.
+
+ - dmas : Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
+
+ - dma-names : Two dmas have to be defined, "tx" and "rx".
+
+ - clocks : Contains an entry for each entry in clock-names.
+
+ - clock-names : Includes the following entries:
+ name type comments
+ "core" Required The core clock of spdif controller
+
+ "rx" Optional Rx clock source for spdif record.
+ If absent, will use core clock.
+
+ "tx" Optional Tx clock source for spdif playback.
+ If absent, will use core clock.
+
+ "tx-32000" Optional Tx clock source for 32000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-44100" Optional Tx clock source for 44100Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-48000" Optional Tx clock source for 48000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "src<0-7>" Optional Clock source list for tx and rx clock
+ to look up their clock source indexes.
+ This clock list should be identical to
+ the list of TxClk_Source bit value of
+ register SPDIF_STC. If absent or failed
+ to look up, tx and rx clock would then
+ ignore the "rx", "tx" "tx-32000",
+ "tx-44100", "tx-48000" clock phandles
+ and select the core clock as default
+ tx and rx clock.
+
+Optional properties:
+
+ - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel bit
+ of SPDIF_SRPC would be set a clock source that cares DPLL locked condition.
+
+Example:
+
+spdif: spdif@02004000 {
+ compatible = "fsl,imx6q-spdif",
+ "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 0x04>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+
+ clocks = <&clks 197>, <&clks 3>, <&clks 197>,
+ <&clks 107>, <&clks 118>, <&clks 62>,
+ <&clks 139>;
+ clock-names = "core", "src0", "src1", "src2",
+ "src4", "src5", "src6";
+ rx-clksrc-lock;
+
+ status = "okay";
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e15f771..2c518db 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
config SND_SOC_FSL_SSI
tristate
+config SND_SOC_FSL_SPDIF
+ tristate
+
config SND_SOC_FSL_UTILS
tristate
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index d4b4aa8..4b5970e 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
# Freescale PowerPC SSI/DMA Platform Support
snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-spdif-objs := fsl_spdif.o
snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
new file mode 100644
index 0000000..173d699
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -0,0 +1,1336 @@
+/*
+ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <sound/asoundef.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "fsl_spdif.h"
+#include "imx-pcm.h"
+
+#define FSL_SPDIF_TXFIFO_WML 0x8
+#define FSL_SPDIF_RXFIFO_WML 0x8
+
+#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
+#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
+ INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
+ INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
+
+/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel bit of SRPC */
+static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb, };
+#define SRPC_NODPLL_START1 0x5
+#define SRPC_NODPLL_START2 0xc
+
+/*
+ * SPDIF control structure
+ * Defines channel status, subcode and Q sub
+ */
+struct spdif_mixer_control {
+ /* spinlock to access control data */
+ spinlock_t ctl_lock;
+
+ /* IEC958 channel tx status bit */
+ unsigned char ch_status[4];
+
+ /* User bits */
+ unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+
+ /* Q subcode part of user bits */
+ unsigned char qsub[2 * SPDIF_QSUB_SIZE];
+
+ /* buffer ptrs for writer */
+ u32 upos;
+ u32 qpos;
+
+ /* ready buffer index of the two buffers */
+ u32 ready_buf;
+};
+
+struct fsl_spdif_priv {
+ struct spdif_mixer_control fsl_spdif_control;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ atomic_t dpll_locked;
+ u32 irq;
+ s8 rxclk_src;
+ s8 txclk_src[SPDIF_TXRATE_MAX];
+ u8 txclk_div[SPDIF_TXRATE_MAX];
+ struct clk *txclk[SPDIF_TXRATE_MAX];
+ struct clk *txclk_main;
+ struct clk *rxclk;
+ struct clk *coreclk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+
+ /* The name space will be allocated dynamically */
+ char name[0];
+};
+
+
+#ifdef DEBUG
+static void dumpregs(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val, i;
+ int ret;
+
+ /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
+ for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
+ ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
+ if (!ret)
+ dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
+ }
+}
+#else
+static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
+#endif
+
+
+/* DPLL locked and lock loss interrupt handler */
+static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 locked;
+
+ regmap_read(regmap, REG_SPDIF_SRPC, &locked);
+ locked &= SRPC_DPLL_LOCKED;
+
+ dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
+ locked ? "locked" : "loss lock");
+
+ atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
+}
+
+/* Receiver found illegal symbol interrupt handler */
+static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
+
+ if (!atomic_read(&spdif_priv->dpll_locked)) {
+ /* dpll unlocked seems no audio stream */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
+ }
+}
+
+/* U/Q Channel receive register full */
+static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 *pos, size, val, reg;
+
+ switch (name) {
+ case 'U':
+ pos = &ctrl->upos;
+ size = SPDIF_UBITS_SIZE;
+ reg = REG_SPDIF_SRU;
+ break;
+ case 'Q':
+ pos = &ctrl->qpos;
+ size = SPDIF_QSUB_SIZE;
+ reg = REG_SPDIF_SRQ;
+ break;
+ default:
+ return;
+ }
+
+ dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
+
+ if (*pos >= size * 2) {
+ *pos = 0;
+ } else if (unlikely((*pos % size) + 3 > size)) {
+ dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
+ return;
+ }
+
+ regmap_read(regmap, reg, &val);
+ ctrl->subcode[*pos++] = val >> 16;
+ ctrl->subcode[*pos++] = val >> 8;
+ ctrl->subcode[*pos++] = val;
+}
+
+/* U/Q Channel sync found */
+static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
+
+ /* U/Q buffer reset */
+ if (ctrl->qpos == 0)
+ return;
+
+ /* set ready to this buffer */
+ ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
+}
+
+/* U/Q Channel framing error */
+static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
+
+ /* read U/Q data and do buffer reset */
+ regmap_read(regmap, REG_SPDIF_SRU, &val);
+ regmap_read(regmap, REG_SPDIF_SRQ, &val);
+
+ /* drop this U/Q buffer */
+ ctrl->ready_buf = 0;
+ ctrl->upos = 0;
+ ctrl->qpos = 0;
+}
+
+/* Get spdif interrupt status and clear the interrupt */
+static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, val2;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ regmap_read(regmap, REG_SPDIF_SIE, &val2);
+
+ regmap_write(regmap, REG_SPDIF_SIC, val & val2);
+
+ return val;
+}
+
+static irqreturn_t spdif_isr(int irq, void *devid)
+{
+ struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sis;
+
+ sis = spdif_intr_status_clear(spdif_priv);
+
+ if (sis & INT_DPLL_LOCKED)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ if (sis & INT_TXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
+
+ if (sis & INT_TXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
+
+ if (sis & INT_CNEW)
+ dev_dbg(&pdev->dev, "isr: cstatus new\n");
+
+ if (sis & INT_VAL_NOGOOD)
+ dev_dbg(&pdev->dev, "isr: validity flag no good\n");
+
+ if (sis & INT_SYM_ERR)
+ spdif_irq_sym_error(spdif_priv);
+
+ if (sis & INT_BIT_ERR)
+ dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
+
+ if (sis & INT_URX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'U');
+
+ if (sis & INT_URX_OV)
+ dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
+
+ if (sis & INT_QRX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'Q');
+
+ if (sis & INT_QRX_OV)
+ dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
+
+ if (sis & INT_UQ_SYNC)
+ spdif_irq_uq_sync(spdif_priv);
+
+ if (sis & INT_UQ_ERR)
+ spdif_irq_uq_err(spdif_priv);
+
+ if (sis & INT_RXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
+
+ if (sis & INT_RXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
+
+ if (sis & INT_LOSS_LOCK)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ /* FIXME: Write Tx FIFO to clear TxEm */
+ if (sis & INT_TX_EM)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
+
+ /* FIXME: Read Rx FIFO to clear RxFIFOFul */
+ if (sis & INT_RXFIFO_FUL)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
+
+ return IRQ_HANDLED;
+}
+
+static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, cycle = 1000;
+
+ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+ regcache_sync(regmap);
+
+ /* RESET bit would be cleared after finishing its reset procedure */
+ do {
+ regmap_read(regmap, REG_SPDIF_SCR, &val);
+ } while ((val & SCR_SOFT_RESET) && cycle--);
+}
+
+static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
+ u8 mask, u8 cstatus)
+{
+ ctrl->ch_status[3] &= ~mask;
+ ctrl->ch_status[3] |= cstatus & mask;
+}
+
+static u8 reverse_bits(u8 input)
+{
+ u8 tmp = input;
+
+ tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
+ tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
+ tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
+
+ return tmp;
+}
+
+static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 ch_status;
+
+ ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
+ (reverse_bits(ctrl->ch_status[1]) << 8) |
+ reverse_bits(ctrl->ch_status[2]);
+ regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
+
+ ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
+ regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
+}
+
+/* Set SPDIF PhaseConfig register for rx clock */
+static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel, int dpll_locked)
+{
+ enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
+ struct regmap *regmap = spdif_priv->regmap;
+
+ if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
+ return -EINVAL;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRPC,
+ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
+ SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
+
+ return 0;
+}
+
+static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long rate_actual;
+
+ rate_actual = clk_round_rate(clk, rate);
+ clk_set_rate(clk, rate_actual);
+
+ return 0;
+}
+
+static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
+ int sample_rate)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ unsigned long clk = -1, div = 1, csfs = 0;
+ u32 stc, mask, rate;
+
+ switch (sample_rate) {
+ case 32000:
+ rate = SPDIF_TXRATE_32000;
+ csfs = IEC958_AES3_CON_FS_32000;
+ break;
+ case 44100:
+ rate = SPDIF_TXRATE_44100;
+ csfs = IEC958_AES3_CON_FS_44100;
+ break;
+ case 48000:
+ rate = SPDIF_TXRATE_48000;
+ csfs = IEC958_AES3_CON_FS_48000;
+ break;
+ default:
+ dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
+ return -EINVAL;
+ }
+
+ clk = spdif_priv->txclk_src[rate];
+ if (clk < 0) {
+ dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
+ return -EINVAL;
+ }
+
+ div = spdif_priv->txclk_div[rate];
+ if (div == 0) {
+ dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
+ return -EINVAL;
+ }
+ /*
+ * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
+ * will divide by (div). So request 64 * fs * (div+1) which will
+ * get rounded.
+ */
+ spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1));
+
+ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
+ (int)(64 * sample_rate * div));
+ dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
+ (int)clk_get_rate(spdif_priv->txclk[rate]));
+
+ /* set fs field in consumer channel status */
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
+
+ /* select clock source and divisor */
+ stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
+ mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MASK;
+ regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
+
+ dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
+
+ return 0;
+}
+
+int fsl_spdif_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ /* Reset module and interrupts only for first initialization */
+ if (!cpu_dai->active) {
+ spdif_softreset(spdif_priv);
+
+ /* disable all the interrupts */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
+ }
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
+ SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
+ SCR_TXFIFO_FSEL_IF8;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_enable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_enable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power up SPDIF module */
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
+
+ return 0;
+}
+
+static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = 0;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_disable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_disable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power down SPDIF module only if tx&rx are both inactive */
+ if (!cpu_dai->active) {
+ spdif_intr_status_clear(spdif_priv);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, SCR_LOW_POWER);
+ }
+}
+
+static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sample_rate = params_rate(params);
+ int ret = 0;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = spdif_set_sample_rate(substream, sample_rate);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
+ __func__, sample_rate);
+ return ret;
+ }
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
+ IEC958_AES3_CON_CLOCK_1000PPM);
+ spdif_write_channel_status(spdif_priv);
+ } else {
+ /* setup rx clock source */
+ ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
+ }
+
+ return ret;
+}
+
+static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+ u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
+ u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
+ dumpregs(spdif_priv);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+struct snd_soc_dai_ops fsl_spdif_dai_ops = {
+ .startup = fsl_spdif_startup,
+ .hw_params = fsl_spdif_hw_params,
+ .trigger = fsl_spdif_trigger,
+ .shutdown = fsl_spdif_shutdown,
+};
+
+
+/*
+ * ============================================
+ * FSL SPDIF IEC958 controller(mixer) functions
+ *
+ * Channel status get/put control
+ * User bit value get/put control
+ * Valid bit value get control
+ * DPLL lock status get control
+ * User bit sync mode selection control
+ * ============================================
+ */
+
+static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ uvalue->value.iec958.status[0] = ctrl->ch_status[0];
+ uvalue->value.iec958.status[1] = ctrl->ch_status[1];
+ uvalue->value.iec958.status[2] = ctrl->ch_status[2];
+ uvalue->value.iec958.status[3] = ctrl->ch_status[3];
+
+ return 0;
+}
+
+static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ ctrl->ch_status[0] = uvalue->value.iec958.status[0];
+ ctrl->ch_status[1] = uvalue->value.iec958.status[1];
+ ctrl->ch_status[2] = uvalue->value.iec958.status[2];
+ ctrl->ch_status[3] = uvalue->value.iec958.status[3];
+
+ spdif_write_channel_status(spdif_priv);
+
+ return 0;
+}
+
+/* Get channel status from SPDIF_RX_CCHAN register */
+static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 cstatus, val;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ if (!(val & INT_CNEW)) {
+ return -EAGAIN;
+ }
+
+ regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
+ ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[2] = cstatus & 0xFF;
+
+ regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
+ ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[5] = cstatus & 0xFF;
+
+ /* clear intr */
+ regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
+
+ return 0;
+}
+
+/*
+ * Get User bits (subcode) from chip value which readed out
+ * in UChannel register.
+ */
+static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
+ memcpy(&ucontrol->value.iec958.subcode[0],
+ &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
+static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+ uinfo->count = SPDIF_QSUB_SIZE;
+
+ return 0;
+}
+
+/* Get Q subcode from chip value which readed out in QChannel register */
+static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
+ memcpy(&ucontrol->value.bytes.data[0],
+ &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Valid bit infomation */
+static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/* Get valid good bit from interrupt status register */
+static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ val = regmap_read(regmap, REG_SPDIF_SIS, &val);
+ ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
+ regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
+
+ return 0;
+}
+
+/* DPLL lock infomation */
+static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 16000;
+ uinfo->value.integer.max = 96000;
+
+ return 0;
+}
+
+static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
+ 24, 16, 12, 8, 6, 4, 3,
+};
+
+/* Get RX data clock rate given the SPDIF bus_clk */
+static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u64 tmpval64, busclk_freq = 0;
+ u32 freqmeas, phaseconf;
+ enum spdif_rxclk_src clksrc;
+
+ regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
+ regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
+
+ clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
+ if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
+ /* get bus clock from system */
+ busclk_freq = clk_get_rate(spdif_priv->rxclk);
+ }
+
+ /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
+ tmpval64 = (u64) busclk_freq * freqmeas;
+ do_div(tmpval64, gainsel_multi[gainsel] * 1024);
+ do_div(tmpval64, 128 * 1024);
+
+ dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
+ dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
+ dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
+
+ return (int)tmpval64;
+}
+
+/*
+ * Get DPLL lock or not info from stable interrupt status register.
+ * User application must use this control to get locked,
+ * then can do next PCM operation
+ */
+static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
+
+ if (atomic_read(&spdif_priv->dpll_locked))
+ ucontrol->value.integer.value[0] = rate;
+ else
+ ucontrol->value.integer.value[0] = 0;
+
+ return 0;
+}
+
+/* User bit sync mode info */
+static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ regmap_read(regmap, REG_SPDIF_SRCD, &val);
+ ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
+
+ return 0;
+}
+
+/* FSL SPDIF IEC958 controller defines */
+static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
+ /* status cchanel controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_pb_get,
+ .put = fsl_spdif_pb_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_capture_get,
+ },
+ /* user bits controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_subcode_get,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Q-subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_qinfo,
+ .get = fsl_spdif_qget,
+ },
+ /* valid bit error controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 V-Bit Errors",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_vbit_info,
+ .get = fsl_spdif_vbit_get,
+ },
+ /* DPLL lock info get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "RX Sample Rate",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_rxrate_info,
+ .get = fsl_spdif_rxrate_get,
+ },
+ /* User bit sync mode set/get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 USyncMode CDText",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_usync_info,
+ .get = fsl_spdif_usync_get,
+ .put = fsl_spdif_usync_put,
+ },
+};
+
+static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
+{
+ struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
+
+ dai->playback_dma_data = &spdif_private->dma_params_tx;
+ dai->capture_dma_data = &spdif_private->dma_params_rx;
+
+ snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
+
+ return 0;
+}
+
+struct snd_soc_dai_driver fsl_spdif_dai = {
+ .probe = &fsl_spdif_dai_probe,
+ .playback = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_PLAYBACK,
+ .formats = FSL_SPDIF_FORMATS_PLAYBACK,
+ },
+ .capture = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_CAPTURE,
+ .formats = FSL_SPDIF_FORMATS_CAPTURE,
+ },
+ .ops = &fsl_spdif_dai_ops,
+};
+
+static const struct snd_soc_component_driver fsl_spdif_component = {
+ .name = "fsl-spdif",
+};
+
+/*
+ * ================
+ * FSL SPDIF REGMAP
+ * ================
+ */
+
+static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIS:
+ case REG_SPDIF_SRL:
+ case REG_SPDIF_SRR:
+ case REG_SPDIF_SRCSH:
+ case REG_SPDIF_SRCSL:
+ case REG_SPDIF_SRU:
+ case REG_SPDIF_SRQ:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_SRFM:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIC:
+ case REG_SPDIF_STL:
+ case REG_SPDIF_STR:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /* Sync all registers after reset */
+ return true;
+}
+
+static const struct regmap_config fsl_spdif_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .max_register = REG_SPDIF_STC,
+ .readable_reg = fsl_spdif_readable_reg,
+ .writeable_reg = fsl_spdif_writeable_reg,
+ .volatile_reg = fsl_spdif_volatile_reg,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static void spdif_clksrc_index_lookup(struct fsl_spdif_priv *spdif_priv)
+{
+ const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct device_node *np = pdev->dev.of_node;
+ struct clk *tmpclk;
+ char tmp[16];
+ int i, j;
+
+ /* Start to decide tx/rxclk_src index */
+ spdif_priv->rxclk_src = -1;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ spdif_priv->txclk_src[i] = -1;
+
+ /* Look up the clock source list to find the clock source index */
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
+ sprintf(tmp, "src%d", i);
+ tmpclk = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(tmpclk))
+ continue;
+
+ /* Catch the clksrc identical to configured rxclk */
+ if (tmpclk == spdif_priv->rxclk)
+ spdif_priv->rxclk_src = i;
+
+ for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
+ /* Catch the clksrc identical to configured txclk */
+ if (tmpclk == spdif_priv->txclk[j])
+ spdif_priv->txclk_src[j] = i;
+ }
+ }
+
+ /* Plan B when failed to find the index for rx clock source */
+ if (spdif_priv->rxclk_src == -1) {
+ dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
+ spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ /* Plan B when failed to find the index for tx clock source */
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ if (spdif_priv->txclk_src[i] != -1)
+ continue;
+ dev_warn(&pdev->dev, "force to use core clock as %s clock.\n", rate[i]);
+ spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
+ spdif_priv->txclk[i] = spdif_priv->coreclk;
+ }
+
+ if (i > SRPC_NODPLL_START1) {
+ /* Drop src5 for rxclk src */
+ spdif_priv->rxclk_src -= 1;
+
+ /* Restore the offset to higher rxclk src */
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ }
+
+ /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
+ if (!of_property_read_bool(np, "rx-clksrc-lock")) {
+ if (i < SRPC_NODPLL_START1)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ else if (i < SRPC_NODPLL_START2)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
+ }
+}
+
+static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
+{
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct clk **clk = spdif_priv->txclk;
+ u64 rate_ideal, rate_actual, sub, savesub;
+ u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
+ for (div = 1; div <= 128; div++) {
+ rate_ideal = rate[i] * (div + 1) * 64;
+ rate_actual = clk_round_rate(clk[i], rate_ideal);
+
+ arate = rate_actual / 64;
+ arate /= div;
+ if (arate == rate[i]) {
+ savesub = 0;
+ spdif_priv->txclk_div[i] = div;
+ break;
+ } else if (arate / rate[i] == 1) {
+ sub = (arate - rate[i]) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ } else if (rate[i] / arate == 1) {
+ sub = (rate[i] - arate) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ }
+ }
+ dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
+ rate[i], spdif_priv->txclk_div[i]);
+ }
+}
+
+static int fsl_spdif_probe(struct platform_device *pdev)
+{
+ const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct fsl_spdif_priv *spdif_priv;
+ struct spdif_mixer_control *ctrl;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource res;
+ void __iomem *regs;
+ int ret = 0, i;
+
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ /* The DAI name is the last part of the full name of the node. */
+ p = strrchr(np->full_name, '/') + 1;
+ spdif_priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
+ if (!spdif_priv) {
+ dev_err(&pdev->dev, "could not allocate DAI object\n");
+ return -ENOMEM;
+ }
+
+ strcpy(spdif_priv->name, p);
+
+ spdif_priv->pdev = pdev;
+
+ /* Initialize this copy of the CPU DAI driver structure */
+ memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
+ spdif_priv->cpu_dai_drv.name = spdif_priv->name;
+
+ /* Get the addresses and IRQ */
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(&pdev->dev, "could not determine device resources\n");
+ return ret;
+ }
+
+ regs = of_iomap(np, 0);
+ if (IS_ERR(regs)) {
+ dev_err(&pdev->dev, "could not map device resources\n");
+ return PTR_ERR(regs);
+ }
+
+ spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "core", regs, &fsl_spdif_regmap_config);
+ if (IS_ERR(spdif_priv->regmap)) {
+ dev_err(&pdev->dev, "regmap init failed\n");
+ ret = PTR_ERR(spdif_priv->regmap);
+ return ret;
+ }
+
+ spdif_priv->irq = irq_of_parse_and_map(np, 0);
+ if (spdif_priv->irq == NO_IRQ) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+ ret = -ENXIO;
+ goto error_iomap;
+ }
+
+ /* The 'name' should not have any slashes in it. */
+ ret = request_irq(spdif_priv->irq, spdif_isr, 0,
+ spdif_priv->name, spdif_priv);
+ if (ret) {
+ dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
+ goto error_irqmap;
+ }
+
+ spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(spdif_priv->coreclk)) {
+ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
+ ret = PTR_ERR(spdif_priv->coreclk);
+ goto error_irqreq;
+ }
+
+ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
+ if (IS_ERR(spdif_priv->rxclk)) {
+ dev_warn(&pdev->dev, "using core clock as rx clk\n");
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
+ if (IS_ERR(spdif_priv->txclk_main)) {
+ dev_warn(&pdev->dev, "using core clock as tx clk\n");
+ spdif_priv->txclk_main = spdif_priv->coreclk;
+ }
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
+ if (IS_ERR(spdif_priv->txclk[i])) {
+ dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
+ spdif_priv->txclk[i] = spdif_priv->txclk_main;
+ }
+ }
+
+ spdif_clksrc_index_lookup(spdif_priv);
+
+ /* We use regmap to control core clk, so no need to prepare it */
+ clk_prepare(spdif_priv->rxclk);
+ clk_prepare(spdif_priv->txclk_main);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_prepare(spdif_priv->txclk[i]);
+
+ spdif_clk_cal_txdiv(spdif_priv);
+
+ /* initial spinlock for control data */
+ ctrl = &spdif_priv->fsl_spdif_control;
+ spin_lock_init(&ctrl->ctl_lock);
+
+ /* init tx channel status default value */
+ ctrl->ch_status[0] =
+ IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
+ ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
+ ctrl->ch_status[2] = 0x00;
+ ctrl->ch_status[3] =
+ IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
+
+ atomic_set(&spdif_priv->dpll_locked, 0);
+
+ spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
+ spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
+ spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
+ spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
+
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, spdif_priv);
+
+ ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
+ &spdif_priv->cpu_dai_drv, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+ goto error_dev;
+ }
+
+ ret = imx_pcm_dma_init(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+ goto error_component;
+ }
+
+ return ret;
+
+error_component:
+ snd_soc_unregister_component(&pdev->dev);
+error_dev:
+ dev_set_drvdata(&pdev->dev, NULL);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+error_irqreq:
+ free_irq(spdif_priv->irq, spdif_priv);
+error_irqmap:
+ irq_dispose_mapping(spdif_priv->irq);
+error_iomap:
+ iounmap(regs);
+
+ return ret;
+}
+
+static int fsl_spdif_remove(struct platform_device *pdev)
+{
+ struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
+ int i;
+
+ imx_pcm_dma_exit(pdev);
+ snd_soc_unregister_component(&pdev->dev);
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+
+ free_irq(spdif_priv->irq, spdif_priv);
+ irq_dispose_mapping(spdif_priv->irq);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx35-spdif", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
+
+static struct platform_driver fsl_spdif_driver = {
+ .driver = {
+ .name = "fsl-spdif-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_spdif_dt_ids,
+ },
+ .probe = fsl_spdif_probe,
+ .remove = fsl_spdif_remove,
+};
+
+module_platform_driver(fsl_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:fsl-spdif-dai");
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
new file mode 100644
index 0000000..df183fb
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.h
@@ -0,0 +1,224 @@
+/*
+ * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Nicolin Chen <b42378@freescale.com>
+ *
+ * Based on fsl_ssi.h
+ * Author: Timur Tabi <timur@freescale.com>
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_SPDIF_DAI_H
+#define _FSL_SPDIF_DAI_H
+
+/* S/PDIF Register Map */
+#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
+#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
+#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
+#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
+#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
+#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
+#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
+#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
+#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
+#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
+#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
+#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
+#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
+#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
+#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
+#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
+#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
+#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
+
+
+/* SPDIF Configuration register */
+#define SCR_RXFIFO_CTL_OFFSET 23
+#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_OFF_OFFSET 22
+#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_RST_OFFSET 21
+#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_FSEL_OFFSET 19
+#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
+#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
+#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_FSEL_OFFSET 15
+#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_LOW_POWER (1 << 13)
+#define SCR_SOFT_RESET (1 << 12)
+#define SCR_TXFIFO_CTRL_OFFSET 10
+#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_DMA_RX_EN_OFFSET 9
+#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_TX_EN_OFFSET 8
+#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_VAL_OFFSET 5
+#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
+#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
+#define SCR_TXSEL_OFFSET 2
+#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
+#define SCR_USRC_SEL_OFFSET 0x0
+#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
+
+/* SPDIF CDText control */
+#define SRCD_CD_USER_OFFSET 1
+#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
+
+/* SPDIF Phase Configuration register */
+#define SRPC_DPLL_LOCKED (1 << 6)
+#define SRPC_CLKSRC_SEL_OFFSET 7
+#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
+#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
+#define SRPC_GAINSEL_OFFSET 3
+#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
+#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
+
+/* SPDIF rx clock source */
+enum spdif_rxclk_src {
+ SRPC_CLKSRC_0 = 0,
+ SRPC_CLKSRC_1,
+ SRPC_CLKSRC_2,
+ SRPC_CLKSRC_3,
+ SRPC_CLKSRC_4,
+ SRPC_CLKSRC_5,
+ SRPC_CLKSRC_6,
+ SRPC_CLKSRC_7,
+ SRPC_CLKSRC_8,
+ SRPC_CLKSRC_9,
+ SRPC_CLKSRC_10,
+ SRPC_CLKSRC_11,
+ SRPC_CLKSRC_12,
+ SRPC_CLKSRC_13,
+ SRPC_CLKSRC_14,
+ SRPC_CLKSRC_15,
+};
+#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
+#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
+
+enum spdif_gainsel {
+ GAINSEL_MULTI_24 = 0,
+ GAINSEL_MULTI_16,
+ GAINSEL_MULTI_12,
+ GAINSEL_MULTI_8,
+ GAINSEL_MULTI_6,
+ GAINSEL_MULTI_4,
+ GAINSEL_MULTI_3,
+};
+#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
+#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
+
+/* SPDIF interrupt mask define */
+#define INT_DPLL_LOCKED (1 << 20)
+#define INT_TXFIFO_UNOV (1 << 19)
+#define INT_TXFIFO_RESYNC (1 << 18)
+#define INT_CNEW (1 << 17)
+#define INT_VAL_NOGOOD (1 << 16)
+#define INT_SYM_ERR (1 << 15)
+#define INT_BIT_ERR (1 << 14)
+#define INT_URX_FUL (1 << 10)
+#define INT_URX_OV (1 << 9)
+#define INT_QRX_FUL (1 << 8)
+#define INT_QRX_OV (1 << 7)
+#define INT_UQ_SYNC (1 << 6)
+#define INT_UQ_ERR (1 << 5)
+#define INT_RXFIFO_UNOV (1 << 4)
+#define INT_RXFIFO_RESYNC (1 << 3)
+#define INT_LOSS_LOCK (1 << 2)
+#define INT_TX_EM (1 << 1)
+#define INT_RXFIFO_FUL (1 << 0)
+
+/* SPDIF Clock register */
+#define STC_SYSCLK_DIV_OFFSET 11
+#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
+#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
+#define STC_TXCLK_SRC_OFFSET 8
+#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
+#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
+#define STC_TXCLK_ALL_EN_OFFSET 7
+#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_DIV_OFFSET 0
+#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
+#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
+
+/* SPDIF tx clksrc */
+enum spdif_txclk_src {
+ STC_TXCLK_SRC_0 = 0,
+ STC_TXCLK_SRC_1,
+ STC_TXCLK_SRC_2,
+ STC_TXCLK_SRC_3,
+ STC_TXCLK_SRC_4,
+ STC_TXCLK_SRC_5,
+ STC_TXCLK_SRC_6,
+ STC_TXCLK_SRC_7,
+};
+#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
+#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
+
+/* SPDIF tx rate */
+enum spdif_txrate {
+ SPDIF_TXRATE_32000 = 0,
+ SPDIF_TXRATE_44100,
+ SPDIF_TXRATE_48000,
+};
+#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
+
+
+#define SPDIF_CSTATUS_BYTE 6
+#define SPDIF_UBITS_SIZE 96
+#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
+
+
+#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000)
+
+#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | \
+ SNDRV_PCM_RATE_64000 | \
+ SNDRV_PCM_RATE_96000)
+
+#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
+
+#endif /* _FSL_SPDIF_DAI_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
This patch add S/PDIF controller driver for Freescale SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
sound/soc/fsl/Kconfig | 3 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
5 files changed, 1641 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
new file mode 100644
index 0000000..301b827
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -0,0 +1,76 @@
+Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
+
+The Freescale S/PDIF audio block is a stereo transceiver that allows the
+processor to receive and transmit digital audio via an coaxial cable or
+a fibre cable.
+
+Required properties:
+
+ - compatible : Compatible list, contains "fsl,<chip>-spdif".
+
+ - reg : Offset and length of the register set for the device.
+
+ - interrupts : Contains spdif interrupt.
+
+ - dmas : Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
+
+ - dma-names : Two dmas have to be defined, "tx" and "rx".
+
+ - clocks : Contains an entry for each entry in clock-names.
+
+ - clock-names : Includes the following entries:
+ name type comments
+ "core" Required The core clock of spdif controller
+
+ "rx" Optional Rx clock source for spdif record.
+ If absent, will use core clock.
+
+ "tx" Optional Tx clock source for spdif playback.
+ If absent, will use core clock.
+
+ "tx-32000" Optional Tx clock source for 32000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-44100" Optional Tx clock source for 44100Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-48000" Optional Tx clock source for 48000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "src<0-7>" Optional Clock source list for tx and rx clock
+ to look up their clock source indexes.
+ This clock list should be identical to
+ the list of TxClk_Source bit value of
+ register SPDIF_STC. If absent or failed
+ to look up, tx and rx clock would then
+ ignore the "rx", "tx" "tx-32000",
+ "tx-44100", "tx-48000" clock phandles
+ and select the core clock as default
+ tx and rx clock.
+
+Optional properties:
+
+ - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel bit
+ of SPDIF_SRPC would be set a clock source that cares DPLL locked condition.
+
+Example:
+
+spdif: spdif@02004000 {
+ compatible = "fsl,imx6q-spdif",
+ "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 0x04>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+
+ clocks = <&clks 197>, <&clks 3>, <&clks 197>,
+ <&clks 107>, <&clks 118>, <&clks 62>,
+ <&clks 139>;
+ clock-names = "core", "src0", "src1", "src2",
+ "src4", "src5", "src6";
+ rx-clksrc-lock;
+
+ status = "okay";
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e15f771..2c518db 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
config SND_SOC_FSL_SSI
tristate
+config SND_SOC_FSL_SPDIF
+ tristate
+
config SND_SOC_FSL_UTILS
tristate
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index d4b4aa8..4b5970e 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
# Freescale PowerPC SSI/DMA Platform Support
snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-spdif-objs := fsl_spdif.o
snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
new file mode 100644
index 0000000..173d699
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -0,0 +1,1336 @@
+/*
+ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <sound/asoundef.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "fsl_spdif.h"
+#include "imx-pcm.h"
+
+#define FSL_SPDIF_TXFIFO_WML 0x8
+#define FSL_SPDIF_RXFIFO_WML 0x8
+
+#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
+#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
+ INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
+ INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
+
+/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel bit of SRPC */
+static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb, };
+#define SRPC_NODPLL_START1 0x5
+#define SRPC_NODPLL_START2 0xc
+
+/*
+ * SPDIF control structure
+ * Defines channel status, subcode and Q sub
+ */
+struct spdif_mixer_control {
+ /* spinlock to access control data */
+ spinlock_t ctl_lock;
+
+ /* IEC958 channel tx status bit */
+ unsigned char ch_status[4];
+
+ /* User bits */
+ unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+
+ /* Q subcode part of user bits */
+ unsigned char qsub[2 * SPDIF_QSUB_SIZE];
+
+ /* buffer ptrs for writer */
+ u32 upos;
+ u32 qpos;
+
+ /* ready buffer index of the two buffers */
+ u32 ready_buf;
+};
+
+struct fsl_spdif_priv {
+ struct spdif_mixer_control fsl_spdif_control;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ atomic_t dpll_locked;
+ u32 irq;
+ s8 rxclk_src;
+ s8 txclk_src[SPDIF_TXRATE_MAX];
+ u8 txclk_div[SPDIF_TXRATE_MAX];
+ struct clk *txclk[SPDIF_TXRATE_MAX];
+ struct clk *txclk_main;
+ struct clk *rxclk;
+ struct clk *coreclk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+
+ /* The name space will be allocated dynamically */
+ char name[0];
+};
+
+
+#ifdef DEBUG
+static void dumpregs(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val, i;
+ int ret;
+
+ /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
+ for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
+ ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
+ if (!ret)
+ dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
+ }
+}
+#else
+static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
+#endif
+
+
+/* DPLL locked and lock loss interrupt handler */
+static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 locked;
+
+ regmap_read(regmap, REG_SPDIF_SRPC, &locked);
+ locked &= SRPC_DPLL_LOCKED;
+
+ dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
+ locked ? "locked" : "loss lock");
+
+ atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
+}
+
+/* Receiver found illegal symbol interrupt handler */
+static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
+
+ if (!atomic_read(&spdif_priv->dpll_locked)) {
+ /* dpll unlocked seems no audio stream */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
+ }
+}
+
+/* U/Q Channel receive register full */
+static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 *pos, size, val, reg;
+
+ switch (name) {
+ case 'U':
+ pos = &ctrl->upos;
+ size = SPDIF_UBITS_SIZE;
+ reg = REG_SPDIF_SRU;
+ break;
+ case 'Q':
+ pos = &ctrl->qpos;
+ size = SPDIF_QSUB_SIZE;
+ reg = REG_SPDIF_SRQ;
+ break;
+ default:
+ return;
+ }
+
+ dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
+
+ if (*pos >= size * 2) {
+ *pos = 0;
+ } else if (unlikely((*pos % size) + 3 > size)) {
+ dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
+ return;
+ }
+
+ regmap_read(regmap, reg, &val);
+ ctrl->subcode[*pos++] = val >> 16;
+ ctrl->subcode[*pos++] = val >> 8;
+ ctrl->subcode[*pos++] = val;
+}
+
+/* U/Q Channel sync found */
+static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
+
+ /* U/Q buffer reset */
+ if (ctrl->qpos == 0)
+ return;
+
+ /* set ready to this buffer */
+ ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
+}
+
+/* U/Q Channel framing error */
+static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
+
+ /* read U/Q data and do buffer reset */
+ regmap_read(regmap, REG_SPDIF_SRU, &val);
+ regmap_read(regmap, REG_SPDIF_SRQ, &val);
+
+ /* drop this U/Q buffer */
+ ctrl->ready_buf = 0;
+ ctrl->upos = 0;
+ ctrl->qpos = 0;
+}
+
+/* Get spdif interrupt status and clear the interrupt */
+static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, val2;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ regmap_read(regmap, REG_SPDIF_SIE, &val2);
+
+ regmap_write(regmap, REG_SPDIF_SIC, val & val2);
+
+ return val;
+}
+
+static irqreturn_t spdif_isr(int irq, void *devid)
+{
+ struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sis;
+
+ sis = spdif_intr_status_clear(spdif_priv);
+
+ if (sis & INT_DPLL_LOCKED)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ if (sis & INT_TXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
+
+ if (sis & INT_TXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
+
+ if (sis & INT_CNEW)
+ dev_dbg(&pdev->dev, "isr: cstatus new\n");
+
+ if (sis & INT_VAL_NOGOOD)
+ dev_dbg(&pdev->dev, "isr: validity flag no good\n");
+
+ if (sis & INT_SYM_ERR)
+ spdif_irq_sym_error(spdif_priv);
+
+ if (sis & INT_BIT_ERR)
+ dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
+
+ if (sis & INT_URX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'U');
+
+ if (sis & INT_URX_OV)
+ dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
+
+ if (sis & INT_QRX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'Q');
+
+ if (sis & INT_QRX_OV)
+ dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
+
+ if (sis & INT_UQ_SYNC)
+ spdif_irq_uq_sync(spdif_priv);
+
+ if (sis & INT_UQ_ERR)
+ spdif_irq_uq_err(spdif_priv);
+
+ if (sis & INT_RXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
+
+ if (sis & INT_RXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
+
+ if (sis & INT_LOSS_LOCK)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ /* FIXME: Write Tx FIFO to clear TxEm */
+ if (sis & INT_TX_EM)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
+
+ /* FIXME: Read Rx FIFO to clear RxFIFOFul */
+ if (sis & INT_RXFIFO_FUL)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
+
+ return IRQ_HANDLED;
+}
+
+static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, cycle = 1000;
+
+ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+ regcache_sync(regmap);
+
+ /* RESET bit would be cleared after finishing its reset procedure */
+ do {
+ regmap_read(regmap, REG_SPDIF_SCR, &val);
+ } while ((val & SCR_SOFT_RESET) && cycle--);
+}
+
+static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
+ u8 mask, u8 cstatus)
+{
+ ctrl->ch_status[3] &= ~mask;
+ ctrl->ch_status[3] |= cstatus & mask;
+}
+
+static u8 reverse_bits(u8 input)
+{
+ u8 tmp = input;
+
+ tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
+ tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
+ tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
+
+ return tmp;
+}
+
+static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 ch_status;
+
+ ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
+ (reverse_bits(ctrl->ch_status[1]) << 8) |
+ reverse_bits(ctrl->ch_status[2]);
+ regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
+
+ ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
+ regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
+}
+
+/* Set SPDIF PhaseConfig register for rx clock */
+static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel, int dpll_locked)
+{
+ enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
+ struct regmap *regmap = spdif_priv->regmap;
+
+ if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
+ return -EINVAL;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRPC,
+ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
+ SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
+
+ return 0;
+}
+
+static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long rate_actual;
+
+ rate_actual = clk_round_rate(clk, rate);
+ clk_set_rate(clk, rate_actual);
+
+ return 0;
+}
+
+static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
+ int sample_rate)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ unsigned long clk = -1, div = 1, csfs = 0;
+ u32 stc, mask, rate;
+
+ switch (sample_rate) {
+ case 32000:
+ rate = SPDIF_TXRATE_32000;
+ csfs = IEC958_AES3_CON_FS_32000;
+ break;
+ case 44100:
+ rate = SPDIF_TXRATE_44100;
+ csfs = IEC958_AES3_CON_FS_44100;
+ break;
+ case 48000:
+ rate = SPDIF_TXRATE_48000;
+ csfs = IEC958_AES3_CON_FS_48000;
+ break;
+ default:
+ dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
+ return -EINVAL;
+ }
+
+ clk = spdif_priv->txclk_src[rate];
+ if (clk < 0) {
+ dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
+ return -EINVAL;
+ }
+
+ div = spdif_priv->txclk_div[rate];
+ if (div == 0) {
+ dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
+ return -EINVAL;
+ }
+ /*
+ * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
+ * will divide by (div). So request 64 * fs * (div+1) which will
+ * get rounded.
+ */
+ spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1));
+
+ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
+ (int)(64 * sample_rate * div));
+ dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
+ (int)clk_get_rate(spdif_priv->txclk[rate]));
+
+ /* set fs field in consumer channel status */
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
+
+ /* select clock source and divisor */
+ stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
+ mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MASK;
+ regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
+
+ dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
+
+ return 0;
+}
+
+int fsl_spdif_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ /* Reset module and interrupts only for first initialization */
+ if (!cpu_dai->active) {
+ spdif_softreset(spdif_priv);
+
+ /* disable all the interrupts */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
+ }
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
+ SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
+ SCR_TXFIFO_FSEL_IF8;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_enable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_enable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power up SPDIF module */
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
+
+ return 0;
+}
+
+static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = 0;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_disable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_disable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power down SPDIF module only if tx&rx are both inactive */
+ if (!cpu_dai->active) {
+ spdif_intr_status_clear(spdif_priv);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, SCR_LOW_POWER);
+ }
+}
+
+static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sample_rate = params_rate(params);
+ int ret = 0;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = spdif_set_sample_rate(substream, sample_rate);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
+ __func__, sample_rate);
+ return ret;
+ }
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
+ IEC958_AES3_CON_CLOCK_1000PPM);
+ spdif_write_channel_status(spdif_priv);
+ } else {
+ /* setup rx clock source */
+ ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
+ }
+
+ return ret;
+}
+
+static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+ u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
+ u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
+ dumpregs(spdif_priv);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+struct snd_soc_dai_ops fsl_spdif_dai_ops = {
+ .startup = fsl_spdif_startup,
+ .hw_params = fsl_spdif_hw_params,
+ .trigger = fsl_spdif_trigger,
+ .shutdown = fsl_spdif_shutdown,
+};
+
+
+/*
+ * ============================================
+ * FSL SPDIF IEC958 controller(mixer) functions
+ *
+ * Channel status get/put control
+ * User bit value get/put control
+ * Valid bit value get control
+ * DPLL lock status get control
+ * User bit sync mode selection control
+ * ============================================
+ */
+
+static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ uvalue->value.iec958.status[0] = ctrl->ch_status[0];
+ uvalue->value.iec958.status[1] = ctrl->ch_status[1];
+ uvalue->value.iec958.status[2] = ctrl->ch_status[2];
+ uvalue->value.iec958.status[3] = ctrl->ch_status[3];
+
+ return 0;
+}
+
+static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ ctrl->ch_status[0] = uvalue->value.iec958.status[0];
+ ctrl->ch_status[1] = uvalue->value.iec958.status[1];
+ ctrl->ch_status[2] = uvalue->value.iec958.status[2];
+ ctrl->ch_status[3] = uvalue->value.iec958.status[3];
+
+ spdif_write_channel_status(spdif_priv);
+
+ return 0;
+}
+
+/* Get channel status from SPDIF_RX_CCHAN register */
+static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 cstatus, val;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ if (!(val & INT_CNEW)) {
+ return -EAGAIN;
+ }
+
+ regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
+ ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[2] = cstatus & 0xFF;
+
+ regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
+ ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[5] = cstatus & 0xFF;
+
+ /* clear intr */
+ regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
+
+ return 0;
+}
+
+/*
+ * Get User bits (subcode) from chip value which readed out
+ * in UChannel register.
+ */
+static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
+ memcpy(&ucontrol->value.iec958.subcode[0],
+ &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
+static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+ uinfo->count = SPDIF_QSUB_SIZE;
+
+ return 0;
+}
+
+/* Get Q subcode from chip value which readed out in QChannel register */
+static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
+ memcpy(&ucontrol->value.bytes.data[0],
+ &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Valid bit infomation */
+static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/* Get valid good bit from interrupt status register */
+static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ val = regmap_read(regmap, REG_SPDIF_SIS, &val);
+ ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
+ regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
+
+ return 0;
+}
+
+/* DPLL lock infomation */
+static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 16000;
+ uinfo->value.integer.max = 96000;
+
+ return 0;
+}
+
+static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
+ 24, 16, 12, 8, 6, 4, 3,
+};
+
+/* Get RX data clock rate given the SPDIF bus_clk */
+static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u64 tmpval64, busclk_freq = 0;
+ u32 freqmeas, phaseconf;
+ enum spdif_rxclk_src clksrc;
+
+ regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
+ regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
+
+ clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
+ if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
+ /* get bus clock from system */
+ busclk_freq = clk_get_rate(spdif_priv->rxclk);
+ }
+
+ /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
+ tmpval64 = (u64) busclk_freq * freqmeas;
+ do_div(tmpval64, gainsel_multi[gainsel] * 1024);
+ do_div(tmpval64, 128 * 1024);
+
+ dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
+ dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
+ dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
+
+ return (int)tmpval64;
+}
+
+/*
+ * Get DPLL lock or not info from stable interrupt status register.
+ * User application must use this control to get locked,
+ * then can do next PCM operation
+ */
+static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
+
+ if (atomic_read(&spdif_priv->dpll_locked))
+ ucontrol->value.integer.value[0] = rate;
+ else
+ ucontrol->value.integer.value[0] = 0;
+
+ return 0;
+}
+
+/* User bit sync mode info */
+static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ regmap_read(regmap, REG_SPDIF_SRCD, &val);
+ ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
+
+ return 0;
+}
+
+/* FSL SPDIF IEC958 controller defines */
+static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
+ /* status cchanel controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_pb_get,
+ .put = fsl_spdif_pb_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_capture_get,
+ },
+ /* user bits controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_subcode_get,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Q-subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_qinfo,
+ .get = fsl_spdif_qget,
+ },
+ /* valid bit error controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 V-Bit Errors",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_vbit_info,
+ .get = fsl_spdif_vbit_get,
+ },
+ /* DPLL lock info get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "RX Sample Rate",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_rxrate_info,
+ .get = fsl_spdif_rxrate_get,
+ },
+ /* User bit sync mode set/get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 USyncMode CDText",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_usync_info,
+ .get = fsl_spdif_usync_get,
+ .put = fsl_spdif_usync_put,
+ },
+};
+
+static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
+{
+ struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
+
+ dai->playback_dma_data = &spdif_private->dma_params_tx;
+ dai->capture_dma_data = &spdif_private->dma_params_rx;
+
+ snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
+
+ return 0;
+}
+
+struct snd_soc_dai_driver fsl_spdif_dai = {
+ .probe = &fsl_spdif_dai_probe,
+ .playback = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_PLAYBACK,
+ .formats = FSL_SPDIF_FORMATS_PLAYBACK,
+ },
+ .capture = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_CAPTURE,
+ .formats = FSL_SPDIF_FORMATS_CAPTURE,
+ },
+ .ops = &fsl_spdif_dai_ops,
+};
+
+static const struct snd_soc_component_driver fsl_spdif_component = {
+ .name = "fsl-spdif",
+};
+
+/*
+ * ================
+ * FSL SPDIF REGMAP
+ * ================
+ */
+
+static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIS:
+ case REG_SPDIF_SRL:
+ case REG_SPDIF_SRR:
+ case REG_SPDIF_SRCSH:
+ case REG_SPDIF_SRCSL:
+ case REG_SPDIF_SRU:
+ case REG_SPDIF_SRQ:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_SRFM:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIC:
+ case REG_SPDIF_STL:
+ case REG_SPDIF_STR:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /* Sync all registers after reset */
+ return true;
+}
+
+static const struct regmap_config fsl_spdif_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .max_register = REG_SPDIF_STC,
+ .readable_reg = fsl_spdif_readable_reg,
+ .writeable_reg = fsl_spdif_writeable_reg,
+ .volatile_reg = fsl_spdif_volatile_reg,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static void spdif_clksrc_index_lookup(struct fsl_spdif_priv *spdif_priv)
+{
+ const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct device_node *np = pdev->dev.of_node;
+ struct clk *tmpclk;
+ char tmp[16];
+ int i, j;
+
+ /* Start to decide tx/rxclk_src index */
+ spdif_priv->rxclk_src = -1;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ spdif_priv->txclk_src[i] = -1;
+
+ /* Look up the clock source list to find the clock source index */
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
+ sprintf(tmp, "src%d", i);
+ tmpclk = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(tmpclk))
+ continue;
+
+ /* Catch the clksrc identical to configured rxclk */
+ if (tmpclk == spdif_priv->rxclk)
+ spdif_priv->rxclk_src = i;
+
+ for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
+ /* Catch the clksrc identical to configured txclk */
+ if (tmpclk == spdif_priv->txclk[j])
+ spdif_priv->txclk_src[j] = i;
+ }
+ }
+
+ /* Plan B when failed to find the index for rx clock source */
+ if (spdif_priv->rxclk_src == -1) {
+ dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
+ spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ /* Plan B when failed to find the index for tx clock source */
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ if (spdif_priv->txclk_src[i] != -1)
+ continue;
+ dev_warn(&pdev->dev, "force to use core clock as %s clock.\n", rate[i]);
+ spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
+ spdif_priv->txclk[i] = spdif_priv->coreclk;
+ }
+
+ if (i > SRPC_NODPLL_START1) {
+ /* Drop src5 for rxclk src */
+ spdif_priv->rxclk_src -= 1;
+
+ /* Restore the offset to higher rxclk src */
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ }
+
+ /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
+ if (!of_property_read_bool(np, "rx-clksrc-lock")) {
+ if (i < SRPC_NODPLL_START1)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ else if (i < SRPC_NODPLL_START2)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
+ }
+}
+
+static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
+{
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct clk **clk = spdif_priv->txclk;
+ u64 rate_ideal, rate_actual, sub, savesub;
+ u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
+ for (div = 1; div <= 128; div++) {
+ rate_ideal = rate[i] * (div + 1) * 64;
+ rate_actual = clk_round_rate(clk[i], rate_ideal);
+
+ arate = rate_actual / 64;
+ arate /= div;
+ if (arate == rate[i]) {
+ savesub = 0;
+ spdif_priv->txclk_div[i] = div;
+ break;
+ } else if (arate / rate[i] == 1) {
+ sub = (arate - rate[i]) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ } else if (rate[i] / arate == 1) {
+ sub = (rate[i] - arate) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ }
+ }
+ dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
+ rate[i], spdif_priv->txclk_div[i]);
+ }
+}
+
+static int fsl_spdif_probe(struct platform_device *pdev)
+{
+ const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct fsl_spdif_priv *spdif_priv;
+ struct spdif_mixer_control *ctrl;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource res;
+ void __iomem *regs;
+ int ret = 0, i;
+
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ /* The DAI name is the last part of the full name of the node. */
+ p = strrchr(np->full_name, '/') + 1;
+ spdif_priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
+ if (!spdif_priv) {
+ dev_err(&pdev->dev, "could not allocate DAI object\n");
+ return -ENOMEM;
+ }
+
+ strcpy(spdif_priv->name, p);
+
+ spdif_priv->pdev = pdev;
+
+ /* Initialize this copy of the CPU DAI driver structure */
+ memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
+ spdif_priv->cpu_dai_drv.name = spdif_priv->name;
+
+ /* Get the addresses and IRQ */
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(&pdev->dev, "could not determine device resources\n");
+ return ret;
+ }
+
+ regs = of_iomap(np, 0);
+ if (IS_ERR(regs)) {
+ dev_err(&pdev->dev, "could not map device resources\n");
+ return PTR_ERR(regs);
+ }
+
+ spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "core", regs, &fsl_spdif_regmap_config);
+ if (IS_ERR(spdif_priv->regmap)) {
+ dev_err(&pdev->dev, "regmap init failed\n");
+ ret = PTR_ERR(spdif_priv->regmap);
+ return ret;
+ }
+
+ spdif_priv->irq = irq_of_parse_and_map(np, 0);
+ if (spdif_priv->irq == NO_IRQ) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+ ret = -ENXIO;
+ goto error_iomap;
+ }
+
+ /* The 'name' should not have any slashes in it. */
+ ret = request_irq(spdif_priv->irq, spdif_isr, 0,
+ spdif_priv->name, spdif_priv);
+ if (ret) {
+ dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
+ goto error_irqmap;
+ }
+
+ spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(spdif_priv->coreclk)) {
+ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
+ ret = PTR_ERR(spdif_priv->coreclk);
+ goto error_irqreq;
+ }
+
+ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
+ if (IS_ERR(spdif_priv->rxclk)) {
+ dev_warn(&pdev->dev, "using core clock as rx clk\n");
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
+ if (IS_ERR(spdif_priv->txclk_main)) {
+ dev_warn(&pdev->dev, "using core clock as tx clk\n");
+ spdif_priv->txclk_main = spdif_priv->coreclk;
+ }
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
+ if (IS_ERR(spdif_priv->txclk[i])) {
+ dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
+ spdif_priv->txclk[i] = spdif_priv->txclk_main;
+ }
+ }
+
+ spdif_clksrc_index_lookup(spdif_priv);
+
+ /* We use regmap to control core clk, so no need to prepare it */
+ clk_prepare(spdif_priv->rxclk);
+ clk_prepare(spdif_priv->txclk_main);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_prepare(spdif_priv->txclk[i]);
+
+ spdif_clk_cal_txdiv(spdif_priv);
+
+ /* initial spinlock for control data */
+ ctrl = &spdif_priv->fsl_spdif_control;
+ spin_lock_init(&ctrl->ctl_lock);
+
+ /* init tx channel status default value */
+ ctrl->ch_status[0] =
+ IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
+ ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
+ ctrl->ch_status[2] = 0x00;
+ ctrl->ch_status[3] =
+ IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
+
+ atomic_set(&spdif_priv->dpll_locked, 0);
+
+ spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
+ spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
+ spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
+ spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
+
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, spdif_priv);
+
+ ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
+ &spdif_priv->cpu_dai_drv, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+ goto error_dev;
+ }
+
+ ret = imx_pcm_dma_init(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+ goto error_component;
+ }
+
+ return ret;
+
+error_component:
+ snd_soc_unregister_component(&pdev->dev);
+error_dev:
+ dev_set_drvdata(&pdev->dev, NULL);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+error_irqreq:
+ free_irq(spdif_priv->irq, spdif_priv);
+error_irqmap:
+ irq_dispose_mapping(spdif_priv->irq);
+error_iomap:
+ iounmap(regs);
+
+ return ret;
+}
+
+static int fsl_spdif_remove(struct platform_device *pdev)
+{
+ struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
+ int i;
+
+ imx_pcm_dma_exit(pdev);
+ snd_soc_unregister_component(&pdev->dev);
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+
+ free_irq(spdif_priv->irq, spdif_priv);
+ irq_dispose_mapping(spdif_priv->irq);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx35-spdif", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
+
+static struct platform_driver fsl_spdif_driver = {
+ .driver = {
+ .name = "fsl-spdif-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_spdif_dt_ids,
+ },
+ .probe = fsl_spdif_probe,
+ .remove = fsl_spdif_remove,
+};
+
+module_platform_driver(fsl_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:fsl-spdif-dai");
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
new file mode 100644
index 0000000..df183fb
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.h
@@ -0,0 +1,224 @@
+/*
+ * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Nicolin Chen <b42378@freescale.com>
+ *
+ * Based on fsl_ssi.h
+ * Author: Timur Tabi <timur@freescale.com>
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_SPDIF_DAI_H
+#define _FSL_SPDIF_DAI_H
+
+/* S/PDIF Register Map */
+#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
+#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
+#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
+#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
+#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
+#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
+#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
+#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
+#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
+#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
+#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
+#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
+#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
+#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
+#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
+#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
+#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
+#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
+
+
+/* SPDIF Configuration register */
+#define SCR_RXFIFO_CTL_OFFSET 23
+#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_OFF_OFFSET 22
+#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_RST_OFFSET 21
+#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_FSEL_OFFSET 19
+#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
+#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
+#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_FSEL_OFFSET 15
+#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_LOW_POWER (1 << 13)
+#define SCR_SOFT_RESET (1 << 12)
+#define SCR_TXFIFO_CTRL_OFFSET 10
+#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_DMA_RX_EN_OFFSET 9
+#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_TX_EN_OFFSET 8
+#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_VAL_OFFSET 5
+#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
+#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
+#define SCR_TXSEL_OFFSET 2
+#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
+#define SCR_USRC_SEL_OFFSET 0x0
+#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
+
+/* SPDIF CDText control */
+#define SRCD_CD_USER_OFFSET 1
+#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
+
+/* SPDIF Phase Configuration register */
+#define SRPC_DPLL_LOCKED (1 << 6)
+#define SRPC_CLKSRC_SEL_OFFSET 7
+#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
+#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
+#define SRPC_GAINSEL_OFFSET 3
+#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
+#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
+
+/* SPDIF rx clock source */
+enum spdif_rxclk_src {
+ SRPC_CLKSRC_0 = 0,
+ SRPC_CLKSRC_1,
+ SRPC_CLKSRC_2,
+ SRPC_CLKSRC_3,
+ SRPC_CLKSRC_4,
+ SRPC_CLKSRC_5,
+ SRPC_CLKSRC_6,
+ SRPC_CLKSRC_7,
+ SRPC_CLKSRC_8,
+ SRPC_CLKSRC_9,
+ SRPC_CLKSRC_10,
+ SRPC_CLKSRC_11,
+ SRPC_CLKSRC_12,
+ SRPC_CLKSRC_13,
+ SRPC_CLKSRC_14,
+ SRPC_CLKSRC_15,
+};
+#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
+#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
+
+enum spdif_gainsel {
+ GAINSEL_MULTI_24 = 0,
+ GAINSEL_MULTI_16,
+ GAINSEL_MULTI_12,
+ GAINSEL_MULTI_8,
+ GAINSEL_MULTI_6,
+ GAINSEL_MULTI_4,
+ GAINSEL_MULTI_3,
+};
+#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
+#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
+
+/* SPDIF interrupt mask define */
+#define INT_DPLL_LOCKED (1 << 20)
+#define INT_TXFIFO_UNOV (1 << 19)
+#define INT_TXFIFO_RESYNC (1 << 18)
+#define INT_CNEW (1 << 17)
+#define INT_VAL_NOGOOD (1 << 16)
+#define INT_SYM_ERR (1 << 15)
+#define INT_BIT_ERR (1 << 14)
+#define INT_URX_FUL (1 << 10)
+#define INT_URX_OV (1 << 9)
+#define INT_QRX_FUL (1 << 8)
+#define INT_QRX_OV (1 << 7)
+#define INT_UQ_SYNC (1 << 6)
+#define INT_UQ_ERR (1 << 5)
+#define INT_RXFIFO_UNOV (1 << 4)
+#define INT_RXFIFO_RESYNC (1 << 3)
+#define INT_LOSS_LOCK (1 << 2)
+#define INT_TX_EM (1 << 1)
+#define INT_RXFIFO_FUL (1 << 0)
+
+/* SPDIF Clock register */
+#define STC_SYSCLK_DIV_OFFSET 11
+#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
+#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
+#define STC_TXCLK_SRC_OFFSET 8
+#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
+#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
+#define STC_TXCLK_ALL_EN_OFFSET 7
+#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_DIV_OFFSET 0
+#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
+#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
+
+/* SPDIF tx clksrc */
+enum spdif_txclk_src {
+ STC_TXCLK_SRC_0 = 0,
+ STC_TXCLK_SRC_1,
+ STC_TXCLK_SRC_2,
+ STC_TXCLK_SRC_3,
+ STC_TXCLK_SRC_4,
+ STC_TXCLK_SRC_5,
+ STC_TXCLK_SRC_6,
+ STC_TXCLK_SRC_7,
+};
+#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
+#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
+
+/* SPDIF tx rate */
+enum spdif_txrate {
+ SPDIF_TXRATE_32000 = 0,
+ SPDIF_TXRATE_44100,
+ SPDIF_TXRATE_48000,
+};
+#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
+
+
+#define SPDIF_CSTATUS_BYTE 6
+#define SPDIF_UBITS_SIZE 96
+#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
+
+
+#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000)
+
+#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | \
+ SNDRV_PCM_RATE_64000 | \
+ SNDRV_PCM_RATE_96000)
+
+#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
+
+#endif /* _FSL_SPDIF_DAI_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
This patch add S/PDIF controller driver for Freescale SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
sound/soc/fsl/Kconfig | 3 +
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/fsl_spdif.c | 1336 ++++++++++++++++++++
sound/soc/fsl/fsl_spdif.h | 224 ++++
5 files changed, 1641 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,spdif.txt
create mode 100644 sound/soc/fsl/fsl_spdif.c
create mode 100644 sound/soc/fsl/fsl_spdif.h
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
new file mode 100644
index 0000000..301b827
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -0,0 +1,76 @@
+Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
+
+The Freescale S/PDIF audio block is a stereo transceiver that allows the
+processor to receive and transmit digital audio via an coaxial cable or
+a fibre cable.
+
+Required properties:
+
+ - compatible : Compatible list, contains "fsl,<chip>-spdif".
+
+ - reg : Offset and length of the register set for the device.
+
+ - interrupts : Contains spdif interrupt.
+
+ - dmas : Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
+
+ - dma-names : Two dmas have to be defined, "tx" and "rx".
+
+ - clocks : Contains an entry for each entry in clock-names.
+
+ - clock-names : Includes the following entries:
+ name type comments
+ "core" Required The core clock of spdif controller
+
+ "rx" Optional Rx clock source for spdif record.
+ If absent, will use core clock.
+
+ "tx" Optional Tx clock source for spdif playback.
+ If absent, will use core clock.
+
+ "tx-32000" Optional Tx clock source for 32000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-44100" Optional Tx clock source for 44100Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "tx-48000" Optional Tx clock source for 48000Hz sample rate
+ playback. If absent, will use tx clock.
+
+ "src<0-7>" Optional Clock source list for tx and rx clock
+ to look up their clock source indexes.
+ This clock list should be identical to
+ the list of TxClk_Source bit value of
+ register SPDIF_STC. If absent or failed
+ to look up, tx and rx clock would then
+ ignore the "rx", "tx" "tx-32000",
+ "tx-44100", "tx-48000" clock phandles
+ and select the core clock as default
+ tx and rx clock.
+
+Optional properties:
+
+ - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel bit
+ of SPDIF_SRPC would be set a clock source that cares DPLL locked condition.
+
+Example:
+
+spdif: spdif@02004000 {
+ compatible = "fsl,imx6q-spdif",
+ "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 0x04>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+
+ clocks = <&clks 197>, <&clks 3>, <&clks 197>,
+ <&clks 107>, <&clks 118>, <&clks 62>,
+ <&clks 139>;
+ clock-names = "core", "src0", "src1", "src2",
+ "src4", "src5", "src6";
+ rx-clksrc-lock;
+
+ status = "okay";
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e15f771..2c518db 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
config SND_SOC_FSL_SSI
tristate
+config SND_SOC_FSL_SPDIF
+ tristate
+
config SND_SOC_FSL_UTILS
tristate
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index d4b4aa8..4b5970e 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
# Freescale PowerPC SSI/DMA Platform Support
snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-spdif-objs := fsl_spdif.o
snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
new file mode 100644
index 0000000..173d699
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -0,0 +1,1336 @@
+/*
+ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Based on stmp3xxx_spdif_dai.c
+ * Vladimir Barinov <vbarinov@embeddedalley.com>
+ * Copyright 2008 SigmaTel, Inc
+ * Copyright 2008 Embedded Alley Solutions, Inc
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <sound/asoundef.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "fsl_spdif.h"
+#include "imx-pcm.h"
+
+#define FSL_SPDIF_TXFIFO_WML 0x8
+#define FSL_SPDIF_RXFIFO_WML 0x8
+
+#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
+#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
+ INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
+ INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
+
+/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel bit of SRPC */
+static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb, };
+#define SRPC_NODPLL_START1 0x5
+#define SRPC_NODPLL_START2 0xc
+
+/*
+ * SPDIF control structure
+ * Defines channel status, subcode and Q sub
+ */
+struct spdif_mixer_control {
+ /* spinlock to access control data */
+ spinlock_t ctl_lock;
+
+ /* IEC958 channel tx status bit */
+ unsigned char ch_status[4];
+
+ /* User bits */
+ unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+
+ /* Q subcode part of user bits */
+ unsigned char qsub[2 * SPDIF_QSUB_SIZE];
+
+ /* buffer ptrs for writer */
+ u32 upos;
+ u32 qpos;
+
+ /* ready buffer index of the two buffers */
+ u32 ready_buf;
+};
+
+struct fsl_spdif_priv {
+ struct spdif_mixer_control fsl_spdif_control;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ atomic_t dpll_locked;
+ u32 irq;
+ s8 rxclk_src;
+ s8 txclk_src[SPDIF_TXRATE_MAX];
+ u8 txclk_div[SPDIF_TXRATE_MAX];
+ struct clk *txclk[SPDIF_TXRATE_MAX];
+ struct clk *txclk_main;
+ struct clk *rxclk;
+ struct clk *coreclk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+
+ /* The name space will be allocated dynamically */
+ char name[0];
+};
+
+
+#ifdef DEBUG
+static void dumpregs(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val, i;
+ int ret;
+
+ /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
+ for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
+ ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
+ if (!ret)
+ dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
+ }
+}
+#else
+static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
+#endif
+
+
+/* DPLL locked and lock loss interrupt handler */
+static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 locked;
+
+ regmap_read(regmap, REG_SPDIF_SRPC, &locked);
+ locked &= SRPC_DPLL_LOCKED;
+
+ dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
+ locked ? "locked" : "loss lock");
+
+ atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
+}
+
+/* Receiver found illegal symbol interrupt handler */
+static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
+
+ if (!atomic_read(&spdif_priv->dpll_locked)) {
+ /* dpll unlocked seems no audio stream */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
+ }
+}
+
+/* U/Q Channel receive register full */
+static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 *pos, size, val, reg;
+
+ switch (name) {
+ case 'U':
+ pos = &ctrl->upos;
+ size = SPDIF_UBITS_SIZE;
+ reg = REG_SPDIF_SRU;
+ break;
+ case 'Q':
+ pos = &ctrl->qpos;
+ size = SPDIF_QSUB_SIZE;
+ reg = REG_SPDIF_SRQ;
+ break;
+ default:
+ return;
+ }
+
+ dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
+
+ if (*pos >= size * 2) {
+ *pos = 0;
+ } else if (unlikely((*pos % size) + 3 > size)) {
+ dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
+ return;
+ }
+
+ regmap_read(regmap, reg, &val);
+ ctrl->subcode[*pos++] = val >> 16;
+ ctrl->subcode[*pos++] = val >> 8;
+ ctrl->subcode[*pos++] = val;
+}
+
+/* U/Q Channel sync found */
+static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
+
+ /* U/Q buffer reset */
+ if (ctrl->qpos == 0)
+ return;
+
+ /* set ready to this buffer */
+ ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
+}
+
+/* U/Q Channel framing error */
+static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 val;
+
+ dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
+
+ /* read U/Q data and do buffer reset */
+ regmap_read(regmap, REG_SPDIF_SRU, &val);
+ regmap_read(regmap, REG_SPDIF_SRQ, &val);
+
+ /* drop this U/Q buffer */
+ ctrl->ready_buf = 0;
+ ctrl->upos = 0;
+ ctrl->qpos = 0;
+}
+
+/* Get spdif interrupt status and clear the interrupt */
+static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, val2;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ regmap_read(regmap, REG_SPDIF_SIE, &val2);
+
+ regmap_write(regmap, REG_SPDIF_SIC, val & val2);
+
+ return val;
+}
+
+static irqreturn_t spdif_isr(int irq, void *devid)
+{
+ struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sis;
+
+ sis = spdif_intr_status_clear(spdif_priv);
+
+ if (sis & INT_DPLL_LOCKED)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ if (sis & INT_TXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
+
+ if (sis & INT_TXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
+
+ if (sis & INT_CNEW)
+ dev_dbg(&pdev->dev, "isr: cstatus new\n");
+
+ if (sis & INT_VAL_NOGOOD)
+ dev_dbg(&pdev->dev, "isr: validity flag no good\n");
+
+ if (sis & INT_SYM_ERR)
+ spdif_irq_sym_error(spdif_priv);
+
+ if (sis & INT_BIT_ERR)
+ dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
+
+ if (sis & INT_URX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'U');
+
+ if (sis & INT_URX_OV)
+ dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
+
+ if (sis & INT_QRX_FUL)
+ spdif_irq_uqrx_full(spdif_priv, 'Q');
+
+ if (sis & INT_QRX_OV)
+ dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
+
+ if (sis & INT_UQ_SYNC)
+ spdif_irq_uq_sync(spdif_priv);
+
+ if (sis & INT_UQ_ERR)
+ spdif_irq_uq_err(spdif_priv);
+
+ if (sis & INT_RXFIFO_UNOV)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
+
+ if (sis & INT_RXFIFO_RESYNC)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
+
+ if (sis & INT_LOSS_LOCK)
+ spdif_irq_dpll_lock(spdif_priv);
+
+ /* FIXME: Write Tx FIFO to clear TxEm */
+ if (sis & INT_TX_EM)
+ dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
+
+ /* FIXME: Read Rx FIFO to clear RxFIFOFul */
+ if (sis & INT_RXFIFO_FUL)
+ dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
+
+ return IRQ_HANDLED;
+}
+
+static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, cycle = 1000;
+
+ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+ regcache_sync(regmap);
+
+ /* RESET bit would be cleared after finishing its reset procedure */
+ do {
+ regmap_read(regmap, REG_SPDIF_SCR, &val);
+ } while ((val & SCR_SOFT_RESET) && cycle--);
+}
+
+static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
+ u8 mask, u8 cstatus)
+{
+ ctrl->ch_status[3] &= ~mask;
+ ctrl->ch_status[3] |= cstatus & mask;
+}
+
+static u8 reverse_bits(u8 input)
+{
+ u8 tmp = input;
+
+ tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
+ tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
+ tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
+
+ return tmp;
+}
+
+static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
+{
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 ch_status;
+
+ ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
+ (reverse_bits(ctrl->ch_status[1]) << 8) |
+ reverse_bits(ctrl->ch_status[2]);
+ regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
+
+ ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
+ regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
+}
+
+/* Set SPDIF PhaseConfig register for rx clock */
+static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel, int dpll_locked)
+{
+ enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
+ struct regmap *regmap = spdif_priv->regmap;
+
+ if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
+ return -EINVAL;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRPC,
+ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
+ SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
+
+ return 0;
+}
+
+static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long rate_actual;
+
+ rate_actual = clk_round_rate(clk, rate);
+ clk_set_rate(clk, rate_actual);
+
+ return 0;
+}
+
+static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
+ int sample_rate)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ unsigned long clk = -1, div = 1, csfs = 0;
+ u32 stc, mask, rate;
+
+ switch (sample_rate) {
+ case 32000:
+ rate = SPDIF_TXRATE_32000;
+ csfs = IEC958_AES3_CON_FS_32000;
+ break;
+ case 44100:
+ rate = SPDIF_TXRATE_44100;
+ csfs = IEC958_AES3_CON_FS_44100;
+ break;
+ case 48000:
+ rate = SPDIF_TXRATE_48000;
+ csfs = IEC958_AES3_CON_FS_48000;
+ break;
+ default:
+ dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
+ return -EINVAL;
+ }
+
+ clk = spdif_priv->txclk_src[rate];
+ if (clk < 0) {
+ dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
+ return -EINVAL;
+ }
+
+ div = spdif_priv->txclk_div[rate];
+ if (div == 0) {
+ dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
+ return -EINVAL;
+ }
+ /*
+ * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
+ * will divide by (div). So request 64 * fs * (div+1) which will
+ * get rounded.
+ */
+ spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1));
+
+ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
+ (int)(64 * sample_rate * div));
+ dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
+ (int)clk_get_rate(spdif_priv->txclk[rate]));
+
+ /* set fs field in consumer channel status */
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
+
+ /* select clock source and divisor */
+ stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
+ mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MASK;
+ regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
+
+ dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
+
+ return 0;
+}
+
+int fsl_spdif_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ /* Reset module and interrupts only for first initialization */
+ if (!cpu_dai->active) {
+ spdif_softreset(spdif_priv);
+
+ /* disable all the interrupts */
+ regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
+ }
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
+ SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
+ SCR_TXFIFO_FSEL_IF8;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_enable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_enable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power up SPDIF module */
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
+
+ return 0;
+}
+
+static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 scr, mask, i;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ scr = 0;
+ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
+ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
+ SCR_TXFIFO_FSEL_MASK;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_disable(spdif_priv->txclk[i]);
+ } else {
+ scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
+ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
+ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
+ clk_disable(spdif_priv->rxclk);
+ }
+ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
+
+ /* Power down SPDIF module only if tx&rx are both inactive */
+ if (!cpu_dai->active) {
+ spdif_intr_status_clear(spdif_priv);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, SCR_LOW_POWER);
+ }
+}
+
+static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u32 sample_rate = params_rate(params);
+ int ret = 0;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ ret = spdif_set_sample_rate(substream, sample_rate);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
+ __func__, sample_rate);
+ return ret;
+ }
+ spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
+ IEC958_AES3_CON_CLOCK_1000PPM);
+ spdif_write_channel_status(spdif_priv);
+ } else {
+ /* setup rx clock source */
+ ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
+ }
+
+ return ret;
+}
+
+static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+ u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
+ u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
+ dumpregs(spdif_priv);
+ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
+ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+struct snd_soc_dai_ops fsl_spdif_dai_ops = {
+ .startup = fsl_spdif_startup,
+ .hw_params = fsl_spdif_hw_params,
+ .trigger = fsl_spdif_trigger,
+ .shutdown = fsl_spdif_shutdown,
+};
+
+
+/*
+ * ============================================
+ * FSL SPDIF IEC958 controller(mixer) functions
+ *
+ * Channel status get/put control
+ * User bit value get/put control
+ * Valid bit value get control
+ * DPLL lock status get control
+ * User bit sync mode selection control
+ * ============================================
+ */
+
+static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
+ uinfo->count = 1;
+
+ return 0;
+}
+
+static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ uvalue->value.iec958.status[0] = ctrl->ch_status[0];
+ uvalue->value.iec958.status[1] = ctrl->ch_status[1];
+ uvalue->value.iec958.status[2] = ctrl->ch_status[2];
+ uvalue->value.iec958.status[3] = ctrl->ch_status[3];
+
+ return 0;
+}
+
+static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+ ctrl->ch_status[0] = uvalue->value.iec958.status[0];
+ ctrl->ch_status[1] = uvalue->value.iec958.status[1];
+ ctrl->ch_status[2] = uvalue->value.iec958.status[2];
+ ctrl->ch_status[3] = uvalue->value.iec958.status[3];
+
+ spdif_write_channel_status(spdif_priv);
+
+ return 0;
+}
+
+/* Get channel status from SPDIF_RX_CCHAN register */
+static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 cstatus, val;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ if (!(val & INT_CNEW)) {
+ return -EAGAIN;
+ }
+
+ regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
+ ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[2] = cstatus & 0xFF;
+
+ regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
+ ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
+ ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
+ ucontrol->value.iec958.status[5] = cstatus & 0xFF;
+
+ /* clear intr */
+ regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
+
+ return 0;
+}
+
+/*
+ * Get User bits (subcode) from chip value which readed out
+ * in UChannel register.
+ */
+static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
+ memcpy(&ucontrol->value.iec958.subcode[0],
+ &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
+static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+ uinfo->count = SPDIF_QSUB_SIZE;
+
+ return 0;
+}
+
+/* Get Q subcode from chip value which readed out in QChannel register */
+static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
+ memcpy(&ucontrol->value.bytes.data[0],
+ &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
+ } else {
+ ret = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+ return ret;
+}
+
+/* Valid bit infomation */
+static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/* Get valid good bit from interrupt status register */
+static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ val = regmap_read(regmap, REG_SPDIF_SIS, &val);
+ ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
+ regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
+
+ return 0;
+}
+
+/* DPLL lock infomation */
+static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 16000;
+ uinfo->value.integer.max = 96000;
+
+ return 0;
+}
+
+static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
+ 24, 16, 12, 8, 6, 4, 3,
+};
+
+/* Get RX data clock rate given the SPDIF bus_clk */
+static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_gainsel gainsel)
+{
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+ u64 tmpval64, busclk_freq = 0;
+ u32 freqmeas, phaseconf;
+ enum spdif_rxclk_src clksrc;
+
+ regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
+ regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
+
+ clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
+ if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
+ /* get bus clock from system */
+ busclk_freq = clk_get_rate(spdif_priv->rxclk);
+ }
+
+ /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
+ tmpval64 = (u64) busclk_freq * freqmeas;
+ do_div(tmpval64, gainsel_multi[gainsel] * 1024);
+ do_div(tmpval64, 128 * 1024);
+
+ dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
+ dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
+ dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
+
+ return (int)tmpval64;
+}
+
+/*
+ * Get DPLL lock or not info from stable interrupt status register.
+ * User application must use this control to get locked,
+ * then can do next PCM operation
+ */
+static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
+
+ if (atomic_read(&spdif_priv->dpll_locked))
+ ucontrol->value.integer.value[0] = rate;
+ else
+ ucontrol->value.integer.value[0] = 0;
+
+ return 0;
+}
+
+/* User bit sync mode info */
+static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+ regmap_read(regmap, REG_SPDIF_SRCD, &val);
+ ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
+
+ return 0;
+}
+
+/*
+ * User bit sync mode:
+ * 1 CD User channel subcode
+ * 0 Non-CD data
+ */
+static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
+
+ regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
+
+ return 0;
+}
+
+/* FSL SPDIF IEC958 controller defines */
+static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
+ /* status cchanel controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_pb_get,
+ .put = fsl_spdif_pb_put,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_capture_get,
+ },
+ /* user bits controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_info,
+ .get = fsl_spdif_subcode_get,
+ },
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 Q-subcode Capture Default",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_qinfo,
+ .get = fsl_spdif_qget,
+ },
+ /* valid bit error controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 V-Bit Errors",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_vbit_info,
+ .get = fsl_spdif_vbit_get,
+ },
+ /* DPLL lock info get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "RX Sample Rate",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_rxrate_info,
+ .get = fsl_spdif_rxrate_get,
+ },
+ /* User bit sync mode set/get controller */
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
+ .name = "IEC958 USyncMode CDText",
+ .access = SNDRV_CTL_ELEM_ACCESS_READ |
+ SNDRV_CTL_ELEM_ACCESS_WRITE |
+ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+ .info = fsl_spdif_usync_info,
+ .get = fsl_spdif_usync_get,
+ .put = fsl_spdif_usync_put,
+ },
+};
+
+static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
+{
+ struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
+
+ dai->playback_dma_data = &spdif_private->dma_params_tx;
+ dai->capture_dma_data = &spdif_private->dma_params_rx;
+
+ snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
+
+ return 0;
+}
+
+struct snd_soc_dai_driver fsl_spdif_dai = {
+ .probe = &fsl_spdif_dai_probe,
+ .playback = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_PLAYBACK,
+ .formats = FSL_SPDIF_FORMATS_PLAYBACK,
+ },
+ .capture = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_CAPTURE,
+ .formats = FSL_SPDIF_FORMATS_CAPTURE,
+ },
+ .ops = &fsl_spdif_dai_ops,
+};
+
+static const struct snd_soc_component_driver fsl_spdif_component = {
+ .name = "fsl-spdif",
+};
+
+/*
+ * ================
+ * FSL SPDIF REGMAP
+ * ================
+ */
+
+static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIS:
+ case REG_SPDIF_SRL:
+ case REG_SPDIF_SRR:
+ case REG_SPDIF_SRCSH:
+ case REG_SPDIF_SRCSL:
+ case REG_SPDIF_SRU:
+ case REG_SPDIF_SRQ:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_SRFM:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case REG_SPDIF_SCR:
+ case REG_SPDIF_SRCD:
+ case REG_SPDIF_SRPC:
+ case REG_SPDIF_SIE:
+ case REG_SPDIF_SIC:
+ case REG_SPDIF_STL:
+ case REG_SPDIF_STR:
+ case REG_SPDIF_STCSCH:
+ case REG_SPDIF_STCSCL:
+ case REG_SPDIF_STC:
+ return true;
+ default:
+ return false;
+ };
+}
+
+static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /* Sync all registers after reset */
+ return true;
+}
+
+static const struct regmap_config fsl_spdif_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .max_register = REG_SPDIF_STC,
+ .readable_reg = fsl_spdif_readable_reg,
+ .writeable_reg = fsl_spdif_writeable_reg,
+ .volatile_reg = fsl_spdif_volatile_reg,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static void spdif_clksrc_index_lookup(struct fsl_spdif_priv *spdif_priv)
+{
+ const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct device_node *np = pdev->dev.of_node;
+ struct clk *tmpclk;
+ char tmp[16];
+ int i, j;
+
+ /* Start to decide tx/rxclk_src index */
+ spdif_priv->rxclk_src = -1;
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ spdif_priv->txclk_src[i] = -1;
+
+ /* Look up the clock source list to find the clock source index */
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
+ sprintf(tmp, "src%d", i);
+ tmpclk = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(tmpclk))
+ continue;
+
+ /* Catch the clksrc identical to configured rxclk */
+ if (tmpclk == spdif_priv->rxclk)
+ spdif_priv->rxclk_src = i;
+
+ for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
+ /* Catch the clksrc identical to configured txclk */
+ if (tmpclk == spdif_priv->txclk[j])
+ spdif_priv->txclk_src[j] = i;
+ }
+ }
+
+ /* Plan B when failed to find the index for rx clock source */
+ if (spdif_priv->rxclk_src == -1) {
+ dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
+ spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ /* Plan B when failed to find the index for tx clock source */
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ if (spdif_priv->txclk_src[i] != -1)
+ continue;
+ dev_warn(&pdev->dev, "force to use core clock as %s clock.\n", rate[i]);
+ spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
+ spdif_priv->txclk[i] = spdif_priv->coreclk;
+ }
+
+ if (i > SRPC_NODPLL_START1) {
+ /* Drop src5 for rxclk src */
+ spdif_priv->rxclk_src -= 1;
+
+ /* Restore the offset to higher rxclk src */
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ }
+
+ /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
+ if (!of_property_read_bool(np, "rx-clksrc-lock")) {
+ if (i < SRPC_NODPLL_START1)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
+ else if (i < SRPC_NODPLL_START2)
+ spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
+ }
+}
+
+static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
+{
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct clk **clk = spdif_priv->txclk;
+ u64 rate_ideal, rate_actual, sub, savesub;
+ u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
+ for (div = 1; div <= 128; div++) {
+ rate_ideal = rate[i] * (div + 1) * 64;
+ rate_actual = clk_round_rate(clk[i], rate_ideal);
+
+ arate = rate_actual / 64;
+ arate /= div;
+ if (arate == rate[i]) {
+ savesub = 0;
+ spdif_priv->txclk_div[i] = div;
+ break;
+ } else if (arate / rate[i] == 1) {
+ sub = (arate - rate[i]) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ } else if (rate[i] / arate == 1) {
+ sub = (rate[i] - arate) * 100000;
+ do_div(sub, rate[i]);
+ if (sub < savesub) {
+ savesub = sub;
+ spdif_priv->txclk_div[i] = div;
+ }
+ }
+ }
+ dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
+ rate[i], spdif_priv->txclk_div[i]);
+ }
+}
+
+static int fsl_spdif_probe(struct platform_device *pdev)
+{
+ const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
+ struct fsl_spdif_priv *spdif_priv;
+ struct spdif_mixer_control *ctrl;
+ struct device_node *np = pdev->dev.of_node;
+ struct resource res;
+ void __iomem *regs;
+ int ret = 0, i;
+
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ /* The DAI name is the last part of the full name of the node. */
+ p = strrchr(np->full_name, '/') + 1;
+ spdif_priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
+ if (!spdif_priv) {
+ dev_err(&pdev->dev, "could not allocate DAI object\n");
+ return -ENOMEM;
+ }
+
+ strcpy(spdif_priv->name, p);
+
+ spdif_priv->pdev = pdev;
+
+ /* Initialize this copy of the CPU DAI driver structure */
+ memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
+ spdif_priv->cpu_dai_drv.name = spdif_priv->name;
+
+ /* Get the addresses and IRQ */
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(&pdev->dev, "could not determine device resources\n");
+ return ret;
+ }
+
+ regs = of_iomap(np, 0);
+ if (IS_ERR(regs)) {
+ dev_err(&pdev->dev, "could not map device resources\n");
+ return PTR_ERR(regs);
+ }
+
+ spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "core", regs, &fsl_spdif_regmap_config);
+ if (IS_ERR(spdif_priv->regmap)) {
+ dev_err(&pdev->dev, "regmap init failed\n");
+ ret = PTR_ERR(spdif_priv->regmap);
+ return ret;
+ }
+
+ spdif_priv->irq = irq_of_parse_and_map(np, 0);
+ if (spdif_priv->irq == NO_IRQ) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+ ret = -ENXIO;
+ goto error_iomap;
+ }
+
+ /* The 'name' should not have any slashes in it. */
+ ret = request_irq(spdif_priv->irq, spdif_isr, 0,
+ spdif_priv->name, spdif_priv);
+ if (ret) {
+ dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
+ goto error_irqmap;
+ }
+
+ spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(spdif_priv->coreclk)) {
+ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
+ ret = PTR_ERR(spdif_priv->coreclk);
+ goto error_irqreq;
+ }
+
+ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
+ if (IS_ERR(spdif_priv->rxclk)) {
+ dev_warn(&pdev->dev, "using core clock as rx clk\n");
+ spdif_priv->rxclk = spdif_priv->coreclk;
+ }
+
+ spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
+ if (IS_ERR(spdif_priv->txclk_main)) {
+ dev_warn(&pdev->dev, "using core clock as tx clk\n");
+ spdif_priv->txclk_main = spdif_priv->coreclk;
+ }
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
+ if (IS_ERR(spdif_priv->txclk[i])) {
+ dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
+ spdif_priv->txclk[i] = spdif_priv->txclk_main;
+ }
+ }
+
+ spdif_clksrc_index_lookup(spdif_priv);
+
+ /* We use regmap to control core clk, so no need to prepare it */
+ clk_prepare(spdif_priv->rxclk);
+ clk_prepare(spdif_priv->txclk_main);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_prepare(spdif_priv->txclk[i]);
+
+ spdif_clk_cal_txdiv(spdif_priv);
+
+ /* initial spinlock for control data */
+ ctrl = &spdif_priv->fsl_spdif_control;
+ spin_lock_init(&ctrl->ctl_lock);
+
+ /* init tx channel status default value */
+ ctrl->ch_status[0] =
+ IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
+ ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
+ ctrl->ch_status[2] = 0x00;
+ ctrl->ch_status[3] =
+ IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
+
+ atomic_set(&spdif_priv->dpll_locked, 0);
+
+ spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
+ spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
+ spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
+ spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
+
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, spdif_priv);
+
+ ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
+ &spdif_priv->cpu_dai_drv, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+ goto error_dev;
+ }
+
+ ret = imx_pcm_dma_init(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+ goto error_component;
+ }
+
+ return ret;
+
+error_component:
+ snd_soc_unregister_component(&pdev->dev);
+error_dev:
+ dev_set_drvdata(&pdev->dev, NULL);
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+error_irqreq:
+ free_irq(spdif_priv->irq, spdif_priv);
+error_irqmap:
+ irq_dispose_mapping(spdif_priv->irq);
+error_iomap:
+ iounmap(regs);
+
+ return ret;
+}
+
+static int fsl_spdif_remove(struct platform_device *pdev)
+{
+ struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
+ int i;
+
+ imx_pcm_dma_exit(pdev);
+ snd_soc_unregister_component(&pdev->dev);
+
+ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ clk_unprepare(spdif_priv->txclk[i]);
+ clk_unprepare(spdif_priv->txclk_main);
+ clk_unprepare(spdif_priv->rxclk);
+
+ free_irq(spdif_priv->irq, spdif_priv);
+ irq_dispose_mapping(spdif_priv->irq);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id fsl_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx35-spdif", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
+
+static struct platform_driver fsl_spdif_driver = {
+ .driver = {
+ .name = "fsl-spdif-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_spdif_dt_ids,
+ },
+ .probe = fsl_spdif_probe,
+ .remove = fsl_spdif_remove,
+};
+
+module_platform_driver(fsl_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:fsl-spdif-dai");
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
new file mode 100644
index 0000000..df183fb
--- /dev/null
+++ b/sound/soc/fsl/fsl_spdif.h
@@ -0,0 +1,224 @@
+/*
+ * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Nicolin Chen <b42378@freescale.com>
+ *
+ * Based on fsl_ssi.h
+ * Author: Timur Tabi <timur@freescale.com>
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_SPDIF_DAI_H
+#define _FSL_SPDIF_DAI_H
+
+/* S/PDIF Register Map */
+#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
+#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
+#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
+#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
+#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
+#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
+#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
+#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
+#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
+#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
+#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
+#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
+#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
+#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
+#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
+#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
+#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
+#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
+
+
+/* SPDIF Configuration register */
+#define SCR_RXFIFO_CTL_OFFSET 23
+#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
+#define SCR_RXFIFO_OFF_OFFSET 22
+#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
+#define SCR_RXFIFO_RST_OFFSET 21
+#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
+#define SCR_RXFIFO_FSEL_OFFSET 19
+#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
+#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
+#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
+#define SCR_TXFIFO_FSEL_OFFSET 15
+#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
+#define SCR_LOW_POWER (1 << 13)
+#define SCR_SOFT_RESET (1 << 12)
+#define SCR_TXFIFO_CTRL_OFFSET 10
+#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
+#define SCR_DMA_RX_EN_OFFSET 9
+#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
+#define SCR_DMA_TX_EN_OFFSET 8
+#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
+#define SCR_VAL_OFFSET 5
+#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
+#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
+#define SCR_TXSEL_OFFSET 2
+#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
+#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
+#define SCR_USRC_SEL_OFFSET 0x0
+#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
+#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
+
+/* SPDIF CDText control */
+#define SRCD_CD_USER_OFFSET 1
+#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
+
+/* SPDIF Phase Configuration register */
+#define SRPC_DPLL_LOCKED (1 << 6)
+#define SRPC_CLKSRC_SEL_OFFSET 7
+#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
+#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
+#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
+#define SRPC_GAINSEL_OFFSET 3
+#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
+#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
+
+/* SPDIF rx clock source */
+enum spdif_rxclk_src {
+ SRPC_CLKSRC_0 = 0,
+ SRPC_CLKSRC_1,
+ SRPC_CLKSRC_2,
+ SRPC_CLKSRC_3,
+ SRPC_CLKSRC_4,
+ SRPC_CLKSRC_5,
+ SRPC_CLKSRC_6,
+ SRPC_CLKSRC_7,
+ SRPC_CLKSRC_8,
+ SRPC_CLKSRC_9,
+ SRPC_CLKSRC_10,
+ SRPC_CLKSRC_11,
+ SRPC_CLKSRC_12,
+ SRPC_CLKSRC_13,
+ SRPC_CLKSRC_14,
+ SRPC_CLKSRC_15,
+};
+#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
+#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
+
+enum spdif_gainsel {
+ GAINSEL_MULTI_24 = 0,
+ GAINSEL_MULTI_16,
+ GAINSEL_MULTI_12,
+ GAINSEL_MULTI_8,
+ GAINSEL_MULTI_6,
+ GAINSEL_MULTI_4,
+ GAINSEL_MULTI_3,
+};
+#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
+#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
+
+/* SPDIF interrupt mask define */
+#define INT_DPLL_LOCKED (1 << 20)
+#define INT_TXFIFO_UNOV (1 << 19)
+#define INT_TXFIFO_RESYNC (1 << 18)
+#define INT_CNEW (1 << 17)
+#define INT_VAL_NOGOOD (1 << 16)
+#define INT_SYM_ERR (1 << 15)
+#define INT_BIT_ERR (1 << 14)
+#define INT_URX_FUL (1 << 10)
+#define INT_URX_OV (1 << 9)
+#define INT_QRX_FUL (1 << 8)
+#define INT_QRX_OV (1 << 7)
+#define INT_UQ_SYNC (1 << 6)
+#define INT_UQ_ERR (1 << 5)
+#define INT_RXFIFO_UNOV (1 << 4)
+#define INT_RXFIFO_RESYNC (1 << 3)
+#define INT_LOSS_LOCK (1 << 2)
+#define INT_TX_EM (1 << 1)
+#define INT_RXFIFO_FUL (1 << 0)
+
+/* SPDIF Clock register */
+#define STC_SYSCLK_DIV_OFFSET 11
+#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
+#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
+#define STC_TXCLK_SRC_OFFSET 8
+#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
+#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
+#define STC_TXCLK_ALL_EN_OFFSET 7
+#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
+#define STC_TXCLK_DIV_OFFSET 0
+#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
+#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
+
+/* SPDIF tx clksrc */
+enum spdif_txclk_src {
+ STC_TXCLK_SRC_0 = 0,
+ STC_TXCLK_SRC_1,
+ STC_TXCLK_SRC_2,
+ STC_TXCLK_SRC_3,
+ STC_TXCLK_SRC_4,
+ STC_TXCLK_SRC_5,
+ STC_TXCLK_SRC_6,
+ STC_TXCLK_SRC_7,
+};
+#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
+#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
+
+/* SPDIF tx rate */
+enum spdif_txrate {
+ SPDIF_TXRATE_32000 = 0,
+ SPDIF_TXRATE_44100,
+ SPDIF_TXRATE_48000,
+};
+#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
+
+
+#define SPDIF_CSTATUS_BYTE 6
+#define SPDIF_UBITS_SIZE 96
+#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
+
+
+#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000)
+
+#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+ SNDRV_PCM_RATE_48000 | \
+ SNDRV_PCM_RATE_64000 | \
+ SNDRV_PCM_RATE_96000)
+
+#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
+
+#endif /* _FSL_SPDIF_DAI_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* [PATCH v5 2/2] ASoC: fsl: Add S/PDIF machine driver
2013-08-15 11:26 ` Nicolin Chen
(?)
@ 2013-08-15 11:26 ` Nicolin Chen
-1 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: linuxppc-dev, alsa-devel, devicetree, timur, rob.herring,
shawn.guo, festevam
Add S/PDIF machine driver for Freescale i.MX series SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +++++
sound/soc/fsl/Kconfig | 11 ++
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-spdif.c | 134 ++++++++++++++++++++
4 files changed, 176 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/imx-spdif.c
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
new file mode 100644
index 0000000..9a3fa26
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
@@ -0,0 +1,29 @@
+Freescale i.MX audio complex with S/PDIF transceiver
+
+Required properties:
+
+ - compatible : "fsl,imx-audio-spdif"
+
+ - model : The user-visible name of this sound complex
+
+ - spdif-controller : The phandle of the i.MX S/PDIF controller
+
+
+Optional properties:
+
+ - spdif-transmitter : The phandle of the spdif-transmitter dummy codec
+
+ - spdif-receiver : The phandle of the spdif-receiver dummy codec
+
+* Note: At least one of these two properties should be set in the DT binding.
+
+
+Example:
+
+sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-transmitter = <&spdif_tx_codec>;
+ spdif-receiver = <&spdif_rx_codec>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 2c518db..4cc118c 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -195,6 +195,17 @@ config SND_SOC_IMX_SGTL5000
Say Y if you want to add support for SoC audio on an i.MX board with
a sgtl5000 codec.
+config SND_SOC_IMX_SPDIF
+ tristate "SoC Audio support for i.MX boards with S/PDIF"
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SPDIF
+ select SND_SOC_FSL_UTILS
+ select SND_SOC_SPDIF
+ help
+ SoC Audio support for i.MX boards with S/PDIF
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a S/DPDIF.
+
config SND_SOC_IMX_MC13783
tristate "SoC Audio support for I.MX boards with mc13783"
depends on MFD_MC13783 && ARM
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 4b5970e..e2aaff7 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -45,6 +45,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
snd-soc-wm1133-ev1-objs := wm1133-ev1.o
snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
snd-soc-imx-wm8962-objs := imx-wm8962.o
+snd-soc-imx-spdif-objs :=imx-spdif.o
snd-soc-imx-mc13783-objs := imx-mc13783.o
obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
@@ -53,4 +54,5 @@ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
+obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
diff --git a/sound/soc/fsl/imx-spdif.c b/sound/soc/fsl/imx-spdif.c
new file mode 100644
index 0000000..893f3d1
--- /dev/null
+++ b/sound/soc/fsl/imx-spdif.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+struct imx_spdif_data {
+ struct snd_soc_dai_link dai[2];
+ struct snd_soc_card card;
+};
+
+static int imx_spdif_audio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *spdif_np, *codec_tx_np, *codec_rx_np;
+ struct platform_device *spdif_pdev;
+ struct imx_spdif_data *data;
+ int ret = 0, num_links = 0;
+
+ spdif_np = of_parse_phandle(np, "spdif-controller", 0);
+ if (!spdif_np) {
+ dev_err(&pdev->dev, "failed to find spdif-controller\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ spdif_pdev = of_find_device_by_node(spdif_np);
+ if (!spdif_pdev) {
+ dev_err(&pdev->dev, "failed to find S/PDIF device\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ codec_tx_np = of_parse_phandle(np, "spdif-transmitter", 0);
+ if (codec_tx_np) {
+ data->dai[num_links].name = "S/PDIF TX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Playback";
+ data->dai[num_links].codec_dai_name = "dit-hifi";
+ data->dai[num_links].codec_of_node = codec_tx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ codec_rx_np = of_parse_phandle(np, "spdif-receiver", 0);
+ if (codec_rx_np) {
+ data->dai[num_links].name = "S/PDIF RX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Capture";
+ data->dai[num_links].codec_dai_name = "dir-hifi";
+ data->dai[num_links].codec_of_node = codec_rx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ if (!num_links) {
+ dev_err(&pdev->dev, "no enabled S/PDIF DAI link\n");
+ goto fail;
+ }
+
+ data->card.dev = &pdev->dev;
+ data->card.num_links = num_links;
+ data->card.dai_link = data->dai;
+
+ ret = snd_soc_of_parse_card_name(&data->card, "model");
+ if (ret)
+ goto fail;
+
+ ret = snd_soc_register_card(&data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+ goto fail;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+fail:
+ if (codec_tx_np)
+ of_node_put(codec_tx_np);
+ if (codec_rx_np)
+ of_node_put(codec_rx_np);
+ if (spdif_np)
+ of_node_put(spdif_np);
+
+ return ret;
+}
+
+static int imx_spdif_audio_remove(struct platform_device *pdev)
+{
+ struct imx_spdif_data *data = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(&data->card);
+
+ return 0;
+}
+
+static const struct of_device_id imx_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx-audio-spdif", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_spdif_dt_ids);
+
+static struct platform_driver imx_spdif_driver = {
+ .driver = {
+ .name = "imx-spdif",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_spdif_dt_ids,
+ },
+ .probe = imx_spdif_audio_probe,
+ .remove = imx_spdif_audio_remove,
+};
+
+module_platform_driver(imx_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale i.MX S/PDIF machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-spdif");
--
1.7.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* [PATCH v5 2/2] ASoC: fsl: Add S/PDIF machine driver
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
Add S/PDIF machine driver for Freescale i.MX series SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +++++
sound/soc/fsl/Kconfig | 11 ++
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-spdif.c | 134 ++++++++++++++++++++
4 files changed, 176 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/imx-spdif.c
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
new file mode 100644
index 0000000..9a3fa26
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
@@ -0,0 +1,29 @@
+Freescale i.MX audio complex with S/PDIF transceiver
+
+Required properties:
+
+ - compatible : "fsl,imx-audio-spdif"
+
+ - model : The user-visible name of this sound complex
+
+ - spdif-controller : The phandle of the i.MX S/PDIF controller
+
+
+Optional properties:
+
+ - spdif-transmitter : The phandle of the spdif-transmitter dummy codec
+
+ - spdif-receiver : The phandle of the spdif-receiver dummy codec
+
+* Note: At least one of these two properties should be set in the DT binding.
+
+
+Example:
+
+sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-transmitter = <&spdif_tx_codec>;
+ spdif-receiver = <&spdif_rx_codec>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 2c518db..4cc118c 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -195,6 +195,17 @@ config SND_SOC_IMX_SGTL5000
Say Y if you want to add support for SoC audio on an i.MX board with
a sgtl5000 codec.
+config SND_SOC_IMX_SPDIF
+ tristate "SoC Audio support for i.MX boards with S/PDIF"
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SPDIF
+ select SND_SOC_FSL_UTILS
+ select SND_SOC_SPDIF
+ help
+ SoC Audio support for i.MX boards with S/PDIF
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a S/DPDIF.
+
config SND_SOC_IMX_MC13783
tristate "SoC Audio support for I.MX boards with mc13783"
depends on MFD_MC13783 && ARM
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 4b5970e..e2aaff7 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -45,6 +45,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
snd-soc-wm1133-ev1-objs := wm1133-ev1.o
snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
snd-soc-imx-wm8962-objs := imx-wm8962.o
+snd-soc-imx-spdif-objs :=imx-spdif.o
snd-soc-imx-mc13783-objs := imx-mc13783.o
obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
@@ -53,4 +54,5 @@ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
+obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
diff --git a/sound/soc/fsl/imx-spdif.c b/sound/soc/fsl/imx-spdif.c
new file mode 100644
index 0000000..893f3d1
--- /dev/null
+++ b/sound/soc/fsl/imx-spdif.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+struct imx_spdif_data {
+ struct snd_soc_dai_link dai[2];
+ struct snd_soc_card card;
+};
+
+static int imx_spdif_audio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *spdif_np, *codec_tx_np, *codec_rx_np;
+ struct platform_device *spdif_pdev;
+ struct imx_spdif_data *data;
+ int ret = 0, num_links = 0;
+
+ spdif_np = of_parse_phandle(np, "spdif-controller", 0);
+ if (!spdif_np) {
+ dev_err(&pdev->dev, "failed to find spdif-controller\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ spdif_pdev = of_find_device_by_node(spdif_np);
+ if (!spdif_pdev) {
+ dev_err(&pdev->dev, "failed to find S/PDIF device\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ codec_tx_np = of_parse_phandle(np, "spdif-transmitter", 0);
+ if (codec_tx_np) {
+ data->dai[num_links].name = "S/PDIF TX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Playback";
+ data->dai[num_links].codec_dai_name = "dit-hifi";
+ data->dai[num_links].codec_of_node = codec_tx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ codec_rx_np = of_parse_phandle(np, "spdif-receiver", 0);
+ if (codec_rx_np) {
+ data->dai[num_links].name = "S/PDIF RX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Capture";
+ data->dai[num_links].codec_dai_name = "dir-hifi";
+ data->dai[num_links].codec_of_node = codec_rx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ if (!num_links) {
+ dev_err(&pdev->dev, "no enabled S/PDIF DAI link\n");
+ goto fail;
+ }
+
+ data->card.dev = &pdev->dev;
+ data->card.num_links = num_links;
+ data->card.dai_link = data->dai;
+
+ ret = snd_soc_of_parse_card_name(&data->card, "model");
+ if (ret)
+ goto fail;
+
+ ret = snd_soc_register_card(&data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+ goto fail;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+fail:
+ if (codec_tx_np)
+ of_node_put(codec_tx_np);
+ if (codec_rx_np)
+ of_node_put(codec_rx_np);
+ if (spdif_np)
+ of_node_put(spdif_np);
+
+ return ret;
+}
+
+static int imx_spdif_audio_remove(struct platform_device *pdev)
+{
+ struct imx_spdif_data *data = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(&data->card);
+
+ return 0;
+}
+
+static const struct of_device_id imx_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx-audio-spdif", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_spdif_dt_ids);
+
+static struct platform_driver imx_spdif_driver = {
+ .driver = {
+ .name = "imx-spdif",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_spdif_dt_ids,
+ },
+ .probe = imx_spdif_audio_probe,
+ .remove = imx_spdif_audio_remove,
+};
+
+module_platform_driver(imx_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale i.MX S/PDIF machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-spdif");
--
1.7.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* [PATCH v5 2/2] ASoC: fsl: Add S/PDIF machine driver
@ 2013-08-15 11:26 ` Nicolin Chen
0 siblings, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-15 11:26 UTC (permalink / raw)
To: broonie, lars, p.zabel, s.hauer
Cc: devicetree, alsa-devel, festevam, timur, rob.herring, shawn.guo,
linuxppc-dev
Add S/PDIF machine driver for Freescale i.MX series SoC.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
---
.../devicetree/bindings/sound/imx-audio-spdif.txt | 29 +++++
sound/soc/fsl/Kconfig | 11 ++
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-spdif.c | 134 ++++++++++++++++++++
4 files changed, 176 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
create mode 100644 sound/soc/fsl/imx-spdif.c
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
new file mode 100644
index 0000000..9a3fa26
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
@@ -0,0 +1,29 @@
+Freescale i.MX audio complex with S/PDIF transceiver
+
+Required properties:
+
+ - compatible : "fsl,imx-audio-spdif"
+
+ - model : The user-visible name of this sound complex
+
+ - spdif-controller : The phandle of the i.MX S/PDIF controller
+
+
+Optional properties:
+
+ - spdif-transmitter : The phandle of the spdif-transmitter dummy codec
+
+ - spdif-receiver : The phandle of the spdif-receiver dummy codec
+
+* Note: At least one of these two properties should be set in the DT binding.
+
+
+Example:
+
+sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-transmitter = <&spdif_tx_codec>;
+ spdif-receiver = <&spdif_rx_codec>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 2c518db..4cc118c 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -195,6 +195,17 @@ config SND_SOC_IMX_SGTL5000
Say Y if you want to add support for SoC audio on an i.MX board with
a sgtl5000 codec.
+config SND_SOC_IMX_SPDIF
+ tristate "SoC Audio support for i.MX boards with S/PDIF"
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SPDIF
+ select SND_SOC_FSL_UTILS
+ select SND_SOC_SPDIF
+ help
+ SoC Audio support for i.MX boards with S/PDIF
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a S/DPDIF.
+
config SND_SOC_IMX_MC13783
tristate "SoC Audio support for I.MX boards with mc13783"
depends on MFD_MC13783 && ARM
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 4b5970e..e2aaff7 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -45,6 +45,7 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
snd-soc-wm1133-ev1-objs := wm1133-ev1.o
snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
snd-soc-imx-wm8962-objs := imx-wm8962.o
+snd-soc-imx-spdif-objs :=imx-spdif.o
snd-soc-imx-mc13783-objs := imx-mc13783.o
obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
@@ -53,4 +54,5 @@ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
+obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
diff --git a/sound/soc/fsl/imx-spdif.c b/sound/soc/fsl/imx-spdif.c
new file mode 100644
index 0000000..893f3d1
--- /dev/null
+++ b/sound/soc/fsl/imx-spdif.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+struct imx_spdif_data {
+ struct snd_soc_dai_link dai[2];
+ struct snd_soc_card card;
+};
+
+static int imx_spdif_audio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *spdif_np, *codec_tx_np, *codec_rx_np;
+ struct platform_device *spdif_pdev;
+ struct imx_spdif_data *data;
+ int ret = 0, num_links = 0;
+
+ spdif_np = of_parse_phandle(np, "spdif-controller", 0);
+ if (!spdif_np) {
+ dev_err(&pdev->dev, "failed to find spdif-controller\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ spdif_pdev = of_find_device_by_node(spdif_np);
+ if (!spdif_pdev) {
+ dev_err(&pdev->dev, "failed to find S/PDIF device\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&pdev->dev, "failed to allocate memory\n");
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ codec_tx_np = of_parse_phandle(np, "spdif-transmitter", 0);
+ if (codec_tx_np) {
+ data->dai[num_links].name = "S/PDIF TX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Playback";
+ data->dai[num_links].codec_dai_name = "dit-hifi";
+ data->dai[num_links].codec_of_node = codec_tx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ codec_rx_np = of_parse_phandle(np, "spdif-receiver", 0);
+ if (codec_rx_np) {
+ data->dai[num_links].name = "S/PDIF RX";
+ data->dai[num_links].stream_name = "S/PDIF PCM Capture";
+ data->dai[num_links].codec_dai_name = "dir-hifi";
+ data->dai[num_links].codec_of_node = codec_rx_np;
+ data->dai[num_links].cpu_of_node = spdif_np;
+ data->dai[num_links].platform_of_node = spdif_np;
+ num_links++;
+ }
+
+ if (!num_links) {
+ dev_err(&pdev->dev, "no enabled S/PDIF DAI link\n");
+ goto fail;
+ }
+
+ data->card.dev = &pdev->dev;
+ data->card.num_links = num_links;
+ data->card.dai_link = data->dai;
+
+ ret = snd_soc_of_parse_card_name(&data->card, "model");
+ if (ret)
+ goto fail;
+
+ ret = snd_soc_register_card(&data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+ goto fail;
+ }
+
+ platform_set_drvdata(pdev, data);
+
+fail:
+ if (codec_tx_np)
+ of_node_put(codec_tx_np);
+ if (codec_rx_np)
+ of_node_put(codec_rx_np);
+ if (spdif_np)
+ of_node_put(spdif_np);
+
+ return ret;
+}
+
+static int imx_spdif_audio_remove(struct platform_device *pdev)
+{
+ struct imx_spdif_data *data = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(&data->card);
+
+ return 0;
+}
+
+static const struct of_device_id imx_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx-audio-spdif", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_spdif_dt_ids);
+
+static struct platform_driver imx_spdif_driver = {
+ .driver = {
+ .name = "imx-spdif",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_spdif_dt_ids,
+ },
+ .probe = imx_spdif_audio_probe,
+ .remove = imx_spdif_audio_remove,
+};
+
+module_platform_driver(imx_spdif_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale i.MX S/PDIF machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-spdif");
--
1.7.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-15 11:26 ` Nicolin Chen
(?)
@ 2013-08-15 12:18 ` Tomasz Figa
-1 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-15 12:18 UTC (permalink / raw)
To: Nicolin Chen, ian.campbell, pawel.moll, galak
Cc: broonie, lars, p.zabel, s.hauer, linuxppc-dev, alsa-devel,
devicetree, timur, rob.herring, shawn.guo, festevam, swarren,
mark.rutland
[-- Attachment #1: Type: text/plain, Size: 56452 bytes --]
Hi Nicolin,
[Ccing DT bindings maintainers]
On Thursday 15 of August 2013 19:26:39 Nicolin Chen wrote:
> This patch add S/PDIF controller driver for Freescale SoC.
>
> Signed-off-by: Nicolin Chen <b42378@freescale.com>
> ---
> .../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
> sound/soc/fsl/Kconfig | 3 +
> sound/soc/fsl/Makefile | 2 +
> sound/soc/fsl/fsl_spdif.c | 1336
> ++++++++++++++++++++ sound/soc/fsl/fsl_spdif.h
> | 224 ++++ 5 files changed, 1641 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/sound/fsl,spdif.txt create mode
> 100644 sound/soc/fsl/fsl_spdif.c
> create mode 100644 sound/soc/fsl/fsl_spdif.h
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> b/Documentation/devicetree/bindings/sound/fsl,spdif.txt new file mode
> 100644
> index 0000000..301b827
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> @@ -0,0 +1,76 @@
> +Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
> +
> +The Freescale S/PDIF audio block is a stereo transceiver that allows
> the +processor to receive and transmit digital audio via an coaxial
> cable or +a fibre cable.
> +
> +Required properties:
> +
> + - compatible : Compatible list, contains "fsl,<chip>-spdif".
> +
> + - reg : Offset and length of the register set for the device.
> +
> + - interrupts : Contains spdif interrupt.
> +
> + - dmas : Generic dma devicetree binding as described in
> + Documentation/devicetree/bindings/dma/dma.txt.
> +
> + - dma-names : Two dmas have to be defined, "tx" and "rx".
> +
> + - clocks : Contains an entry for each entry in clock-names.
> +
> + - clock-names : Includes the following entries:
> + name type comments
> + "core" Required The core clock of spdif controller
> +
> + "rx" Optional Rx clock source for spdif record.
> + If absent, will use core clock.
> +
> + "tx" Optional Tx clock source for spdif playback.
> + If absent, will use core clock.
> +
> + "tx-32000" Optional Tx clock source for 32000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-44100" Optional Tx clock source for 44100Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-48000" Optional Tx clock source for 48000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "src<0-7>" Optional Clock source list for tx and rx clock
> + to look up their clock source indexes.
> + This clock list should be identical to
> + the list of TxClk_Source bit value of
> + register SPDIF_STC. If absent or failed
> + to look up, tx and rx clock would then
> + ignore the "rx", "tx" "tx-32000",
> + "tx-44100", "tx-48000" clock phandles
> + and select the core clock as default
> + tx and rx clock.
I suspect a little abuse of clocks property here. From the description of
"core" and "src<0-7>" clocks I assume that the IP can have up to 9 clock
inputs - core clock and up to 8 extra source clocks. Is it correct?
If yes, this makes the "tx", "rx" and "tx-*" clocks describe
configuration, not hardware. IMHO it should be up to the driver which
source clocks to use for tx and rx channels and for each sampling rate.
> +Optional properties:
> +
> + - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel
> bit + of SPDIF_SRPC would be set a clock source that cares DPLL locked
> condition. +
This again looks like software configuration, not hardware description.
Could you elaborate a bit more on meaning of this property?
> +Example:
> +
> +spdif: spdif@02004000 {
> + compatible = "fsl,imx6q-spdif",
> + "fsl,imx35-spdif";
> + reg = <0x02004000 0x4000>;
> + interrupts = <0 52 0x04>;
> + dmas = <&sdma 14 18 0>,
> + <&sdma 15 18 0>;
> + dma-names = "rx", "tx";
> +
> + clocks = <&clks 197>, <&clks 3>, <&clks 197>,
> + <&clks 107>, <&clks 118>, <&clks 62>,
> + <&clks 139>;
> + clock-names = "core", "src0", "src1", "src2",
> + "src4", "src5", "src6";
> + rx-clksrc-lock;
> +
> + status = "okay";
> +};
> diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
> index e15f771..2c518db 100644
> --- a/sound/soc/fsl/Kconfig
> +++ b/sound/soc/fsl/Kconfig
> @@ -1,6 +1,9 @@
> config SND_SOC_FSL_SSI
> tristate
>
> +config SND_SOC_FSL_SPDIF
> + tristate
> +
> config SND_SOC_FSL_UTILS
> tristate
>
> diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
> index d4b4aa8..4b5970e 100644
> --- a/sound/soc/fsl/Makefile
> +++ b/sound/soc/fsl/Makefile
> @@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) +=
> snd-soc-p1022-rdk.o
>
> # Freescale PowerPC SSI/DMA Platform Support
> snd-soc-fsl-ssi-objs := fsl_ssi.o
> +snd-soc-fsl-spdif-objs := fsl_spdif.o
> snd-soc-fsl-utils-objs := fsl_utils.o
> snd-soc-fsl-dma-objs := fsl_dma.o
> obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
> +obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
> obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
> obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
>
> diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
> new file mode 100644
> index 0000000..173d699
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.c
> @@ -0,0 +1,1336 @@
> +/*
> + * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Based on stmp3xxx_spdif_dai.c
> + * Vladimir Barinov <vbarinov@embeddedalley.com>
> + * Copyright 2008 SigmaTel, Inc
> + * Copyright 2008 Embedded Alley Solutions, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +
> +#include <sound/asoundef.h>
> +#include <sound/soc.h>
> +#include <sound/dmaengine_pcm.h>
> +
> +#include "fsl_spdif.h"
> +#include "imx-pcm.h"
> +
> +#define FSL_SPDIF_TXFIFO_WML 0x8
> +#define FSL_SPDIF_RXFIFO_WML 0x8
> +
> +#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
> +#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |
> INT_URX_OV|\ + INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
> + INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
> +
> +/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel
> bit of SRPC */ +static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3,
> 0x4, 0xa, 0xb, }; +#define SRPC_NODPLL_START1 0x5
> +#define SRPC_NODPLL_START2 0xc
> +
> +/*
> + * SPDIF control structure
> + * Defines channel status, subcode and Q sub
> + */
> +struct spdif_mixer_control {
> + /* spinlock to access control data */
> + spinlock_t ctl_lock;
> +
> + /* IEC958 channel tx status bit */
> + unsigned char ch_status[4];
> +
> + /* User bits */
> + unsigned char subcode[2 * SPDIF_UBITS_SIZE];
> +
> + /* Q subcode part of user bits */
> + unsigned char qsub[2 * SPDIF_QSUB_SIZE];
> +
> + /* buffer ptrs for writer */
> + u32 upos;
> + u32 qpos;
> +
> + /* ready buffer index of the two buffers */
> + u32 ready_buf;
> +};
> +
> +struct fsl_spdif_priv {
> + struct spdif_mixer_control fsl_spdif_control;
> + struct snd_soc_dai_driver cpu_dai_drv;
> + struct platform_device *pdev;
> + struct regmap *regmap;
> + atomic_t dpll_locked;
> + u32 irq;
> + s8 rxclk_src;
> + s8 txclk_src[SPDIF_TXRATE_MAX];
> + u8 txclk_div[SPDIF_TXRATE_MAX];
> + struct clk *txclk[SPDIF_TXRATE_MAX];
> + struct clk *txclk_main;
> + struct clk *rxclk;
> + struct clk *coreclk;
> + struct snd_dmaengine_dai_dma_data dma_params_tx;
> + struct snd_dmaengine_dai_dma_data dma_params_rx;
> +
> + /* The name space will be allocated dynamically */
> + char name[0];
> +};
> +
> +
> +#ifdef DEBUG
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val, i;
> + int ret;
> +
> + /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
> + for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
> + ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
> + if (!ret)
> + dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
> + }
> +}
> +#else
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
> +#endif
> +
> +
> +/* DPLL locked and lock loss interrupt handler */
> +static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 locked;
> +
> + regmap_read(regmap, REG_SPDIF_SRPC, &locked);
> + locked &= SRPC_DPLL_LOCKED;
> +
> + dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
> + locked ? "locked" : "loss lock");
> +
> + atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
> +}
> +
> +/* Receiver found illegal symbol interrupt handler */
> +static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
> +
> + if (!atomic_read(&spdif_priv->dpll_locked)) {
> + /* dpll unlocked seems no audio stream */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
> + }
> +}
> +
> +/* U/Q Channel receive register full */
> +static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char
> name) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 *pos, size, val, reg;
> +
> + switch (name) {
> + case 'U':
> + pos = &ctrl->upos;
> + size = SPDIF_UBITS_SIZE;
> + reg = REG_SPDIF_SRU;
> + break;
> + case 'Q':
> + pos = &ctrl->qpos;
> + size = SPDIF_QSUB_SIZE;
> + reg = REG_SPDIF_SRQ;
> + break;
> + default:
> + return;
> + }
> +
> + dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
> +
> + if (*pos >= size * 2) {
> + *pos = 0;
> + } else if (unlikely((*pos % size) + 3 > size)) {
> + dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
> + return;
> + }
> +
> + regmap_read(regmap, reg, &val);
> + ctrl->subcode[*pos++] = val >> 16;
> + ctrl->subcode[*pos++] = val >> 8;
> + ctrl->subcode[*pos++] = val;
> +}
> +
> +/* U/Q Channel sync found */
> +static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
> +
> + /* U/Q buffer reset */
> + if (ctrl->qpos == 0)
> + return;
> +
> + /* set ready to this buffer */
> + ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
> +}
> +
> +/* U/Q Channel framing error */
> +static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
> +
> + /* read U/Q data and do buffer reset */
> + regmap_read(regmap, REG_SPDIF_SRU, &val);
> + regmap_read(regmap, REG_SPDIF_SRQ, &val);
> +
> + /* drop this U/Q buffer */
> + ctrl->ready_buf = 0;
> + ctrl->upos = 0;
> + ctrl->qpos = 0;
> +}
> +
> +/* Get spdif interrupt status and clear the interrupt */
> +static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, val2;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + regmap_read(regmap, REG_SPDIF_SIE, &val2);
> +
> + regmap_write(regmap, REG_SPDIF_SIC, val & val2);
> +
> + return val;
> +}
> +
> +static irqreturn_t spdif_isr(int irq, void *devid)
> +{
> + struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 sis;
> +
> + sis = spdif_intr_status_clear(spdif_priv);
> +
> + if (sis & INT_DPLL_LOCKED)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + if (sis & INT_TXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
> +
> + if (sis & INT_TXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
> +
> + if (sis & INT_CNEW)
> + dev_dbg(&pdev->dev, "isr: cstatus new\n");
> +
> + if (sis & INT_VAL_NOGOOD)
> + dev_dbg(&pdev->dev, "isr: validity flag no good\n");
> +
> + if (sis & INT_SYM_ERR)
> + spdif_irq_sym_error(spdif_priv);
> +
> + if (sis & INT_BIT_ERR)
> + dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
> +
> + if (sis & INT_URX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'U');
> +
> + if (sis & INT_URX_OV)
> + dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
> +
> + if (sis & INT_QRX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'Q');
> +
> + if (sis & INT_QRX_OV)
> + dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
> +
> + if (sis & INT_UQ_SYNC)
> + spdif_irq_uq_sync(spdif_priv);
> +
> + if (sis & INT_UQ_ERR)
> + spdif_irq_uq_err(spdif_priv);
> +
> + if (sis & INT_RXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
> +
> + if (sis & INT_RXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
> +
> + if (sis & INT_LOSS_LOCK)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + /* FIXME: Write Tx FIFO to clear TxEm */
> + if (sis & INT_TX_EM)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
> +
> + /* FIXME: Read Rx FIFO to clear RxFIFOFul */
> + if (sis & INT_RXFIFO_FUL)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, cycle = 1000;
> +
> + regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
> + regcache_sync(regmap);
> +
> + /* RESET bit would be cleared after finishing its reset procedure */
> + do {
> + regmap_read(regmap, REG_SPDIF_SCR, &val);
> + } while ((val & SCR_SOFT_RESET) && cycle--);
> +}
> +
> +static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
> + u8 mask, u8 cstatus)
> +{
> + ctrl->ch_status[3] &= ~mask;
> + ctrl->ch_status[3] |= cstatus & mask;
> +}
> +
> +static u8 reverse_bits(u8 input)
> +{
> + u8 tmp = input;
> +
> + tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
> + tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
> + tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
> +
> + return tmp;
> +}
> +
> +static void spdif_write_channel_status(struct fsl_spdif_priv
> *spdif_priv) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 ch_status;
> +
> + ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
> + (reverse_bits(ctrl->ch_status[1]) << 8) |
> + reverse_bits(ctrl->ch_status[2]);
> + regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
> +
> + ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
> + regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
> +}
> +
> +/* Set SPDIF PhaseConfig register for rx clock */
> +static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel, int dpll_locked)
> +{
> + enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
> + struct regmap *regmap = spdif_priv->regmap;
> +
> + if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
> + return -EINVAL;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRPC,
> + SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
> + SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
> +
> + return 0;
> +}
> +
> +static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + unsigned long rate_actual;
> +
> + rate_actual = clk_round_rate(clk, rate);
> + clk_set_rate(clk, rate_actual);
> +
> + return 0;
> +}
> +
> +static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
> + int sample_rate)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct regmap *regmap =
> spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + unsigned long clk = -1, div = 1, csfs = 0;
> + u32 stc, mask, rate;
> +
> + switch (sample_rate) {
> + case 32000:
> + rate = SPDIF_TXRATE_32000;
> + csfs = IEC958_AES3_CON_FS_32000;
> + break;
> + case 44100:
> + rate = SPDIF_TXRATE_44100;
> + csfs = IEC958_AES3_CON_FS_44100;
> + break;
> + case 48000:
> + rate = SPDIF_TXRATE_48000;
> + csfs = IEC958_AES3_CON_FS_48000;
> + break;
> + default:
> + dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + clk = spdif_priv->txclk_src[rate];
> + if (clk < 0) {
> + dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + div = spdif_priv->txclk_div[rate];
> + if (div == 0) {
> + dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
> + return -EINVAL;
> + }
> + /*
> + * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
> + * will divide by (div). So request 64 * fs * (div+1) which will
> + * get rounded.
> + */
> + spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div +
> 1)); +
> + dev_dbg(&pdev->dev, "expected clock rate = %d\n",
> + (int)(64 * sample_rate * div));
> + dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
> + (int)clk_get_rate(spdif_priv->txclk[rate]));
> +
> + /* set fs field in consumer channel status */
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
> +
> + /* select clock source and divisor */
> + stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
> + mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
> STC_TXCLK_DIV_MASK; + regmap_update_bits(regmap, REG_SPDIF_STC, mask,
> stc);
> +
> + dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
> +
> + return 0;
> +}
> +
> +int fsl_spdif_startup(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + /* Reset module and interrupts only for first initialization */
> + if (!cpu_dai->active) {
> + spdif_softreset(spdif_priv);
> +
> + /* disable all the interrupts */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
> + }
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
> + SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
> + SCR_TXFIFO_FSEL_IF8;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_enable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_enable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power up SPDIF module */
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
> +
> + return 0;
> +}
> +
> +static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = 0;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_disable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_disable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power down SPDIF module only if tx&rx are both inactive */
> + if (!cpu_dai->active) {
> + spdif_intr_status_clear(spdif_priv);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER,
> SCR_LOW_POWER); + }
> +}
> +
> +static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct platform_device *pdev
> = spdif_priv->pdev;
> + u32 sample_rate = params_rate(params);
> + int ret = 0;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + ret = spdif_set_sample_rate(substream, sample_rate);
> + if (ret) {
> + dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
> + __func__, sample_rate);
> + return ret;
> + }
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
> + IEC958_AES3_CON_CLOCK_1000PPM);
> + spdif_write_channel_status(spdif_priv);
> + } else {
> + /* setup rx clock source */
> + ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
> + }
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
> + int cmd, struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
> + u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
> + u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
> +
> + switch (cmd) {
> + case SNDRV_PCM_TRIGGER_START:
> + case SNDRV_PCM_TRIGGER_RESUME:
> + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
> + dumpregs(spdif_priv);
> + break;
> + case SNDRV_PCM_TRIGGER_STOP:
> + case SNDRV_PCM_TRIGGER_SUSPEND:
> + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +struct snd_soc_dai_ops fsl_spdif_dai_ops = {
> + .startup = fsl_spdif_startup,
> + .hw_params = fsl_spdif_hw_params,
> + .trigger = fsl_spdif_trigger,
> + .shutdown = fsl_spdif_shutdown,
> +};
> +
> +
> +/*
> + * ============================================
> + * FSL SPDIF IEC958 controller(mixer) functions
> + *
> + * Channel status get/put control
> + * User bit value get/put control
> + * Valid bit value get control
> + * DPLL lock status get control
> + * User bit sync mode selection control
> + * ============================================
> + */
> +
> +static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
> + uinfo->count = 1;
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + uvalue->value.iec958.status[0] = ctrl->ch_status[0];
> + uvalue->value.iec958.status[1] = ctrl->ch_status[1];
> + uvalue->value.iec958.status[2] = ctrl->ch_status[2];
> + uvalue->value.iec958.status[3] = ctrl->ch_status[3];
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + ctrl->ch_status[0] = uvalue->value.iec958.status[0];
> + ctrl->ch_status[1] = uvalue->value.iec958.status[1];
> + ctrl->ch_status[2] = uvalue->value.iec958.status[2];
> + ctrl->ch_status[3] = uvalue->value.iec958.status[3];
> +
> + spdif_write_channel_status(spdif_priv);
> +
> + return 0;
> +}
> +
> +/* Get channel status from SPDIF_RX_CCHAN register */
> +static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 cstatus, val;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + if (!(val & INT_CNEW)) {
> + return -EAGAIN;
> + }
> +
> + regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
> + ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[2] = cstatus & 0xFF;
> +
> + regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
> + ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[5] = cstatus & 0xFF;
> +
> + /* clear intr */
> + regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
> +
> + return 0;
> +}
> +
> +/*
> + * Get User bits (subcode) from chip value which readed out
> + * in UChannel register.
> + */
> +static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
> + memcpy(&ucontrol->value.iec958.subcode[0],
> + &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
> +static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
> + uinfo->count = SPDIF_QSUB_SIZE;
> +
> + return 0;
> +}
> +
> +/* Get Q subcode from chip value which readed out in QChannel register
> */ +static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
> + memcpy(&ucontrol->value.bytes.data[0],
> + &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Valid bit infomation */
> +static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/* Get valid good bit from interrupt status register */
> +static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + val = regmap_read(regmap, REG_SPDIF_SIS, &val);
> + ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
> + regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
> +
> + return 0;
> +}
> +
> +/* DPLL lock infomation */
> +static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 16000;
> + uinfo->value.integer.max = 96000;
> +
> + return 0;
> +}
> +
> +static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
> + 24, 16, 12, 8, 6, 4, 3,
> +};
> +
> +/* Get RX data clock rate given the SPDIF bus_clk */
> +static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u64 tmpval64, busclk_freq = 0;
> + u32 freqmeas, phaseconf;
> + enum spdif_rxclk_src clksrc;
> +
> + regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
> + regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
> +
> + clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
> + if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
> + /* get bus clock from system */
> + busclk_freq = clk_get_rate(spdif_priv->rxclk);
> + }
> +
> + /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
> + tmpval64 = (u64) busclk_freq * freqmeas;
> + do_div(tmpval64, gainsel_multi[gainsel] * 1024);
> + do_div(tmpval64, 128 * 1024);
> +
> + dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
> + dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
> + dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
> +
> + return (int)tmpval64;
> +}
> +
> +/*
> + * Get DPLL lock or not info from stable interrupt status register.
> + * User application must use this control to get locked,
> + * then can do next PCM operation
> + */
> +static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
> +
> + if (atomic_read(&spdif_priv->dpll_locked))
> + ucontrol->value.integer.value[0] = rate;
> + else
> + ucontrol->value.integer.value[0] = 0;
> +
> + return 0;
> +}
> +
> +/* User bit sync mode info */
> +static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + regmap_read(regmap, REG_SPDIF_SRCD, &val);
> + ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
> +
> + return 0;
> +}
> +
> +/* FSL SPDIF IEC958 controller defines */
> +static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
> + /* status cchanel controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
> + .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_pb_get,
> + .put = fsl_spdif_pb_put,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_capture_get,
> + },
> + /* user bits controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_subcode_get,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Q-subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_qinfo,
> + .get = fsl_spdif_qget,
> + },
> + /* valid bit error controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 V-Bit Errors",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_vbit_info,
> + .get = fsl_spdif_vbit_get,
> + },
> + /* DPLL lock info get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "RX Sample Rate",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_rxrate_info,
> + .get = fsl_spdif_rxrate_get,
> + },
> + /* User bit sync mode set/get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 USyncMode CDText",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_usync_info,
> + .get = fsl_spdif_usync_get,
> + .put = fsl_spdif_usync_put,
> + },
> +};
> +
> +static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
> +{
> + struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
> +
> + dai->playback_dma_data = &spdif_private->dma_params_tx;
> + dai->capture_dma_data = &spdif_private->dma_params_rx;
> +
> + snd_soc_add_dai_controls(dai, fsl_spdif_ctrls,
> ARRAY_SIZE(fsl_spdif_ctrls)); +
> + return 0;
> +}
> +
> +struct snd_soc_dai_driver fsl_spdif_dai = {
> + .probe = &fsl_spdif_dai_probe,
> + .playback = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_PLAYBACK,
> + .formats = FSL_SPDIF_FORMATS_PLAYBACK,
> + },
> + .capture = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_CAPTURE,
> + .formats = FSL_SPDIF_FORMATS_CAPTURE,
> + },
> + .ops = &fsl_spdif_dai_ops,
> +};
> +
> +static const struct snd_soc_component_driver fsl_spdif_component = {
> + .name = "fsl-spdif",
> +};
> +
> +/*
> + * ================
> + * FSL SPDIF REGMAP
> + * ================
> + */
> +
> +static bool fsl_spdif_readable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIS:
> + case REG_SPDIF_SRL:
> + case REG_SPDIF_SRR:
> + case REG_SPDIF_SRCSH:
> + case REG_SPDIF_SRCSL:
> + case REG_SPDIF_SRU:
> + case REG_SPDIF_SRQ:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_SRFM:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIC:
> + case REG_SPDIF_STL:
> + case REG_SPDIF_STR:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int
> reg) +{
> + /* Sync all registers after reset */
> + return true;
> +}
> +
> +static const struct regmap_config fsl_spdif_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> +
> + .max_register = REG_SPDIF_STC,
> + .readable_reg = fsl_spdif_readable_reg,
> + .writeable_reg = fsl_spdif_writeable_reg,
> + .volatile_reg = fsl_spdif_volatile_reg,
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
> +static void spdif_clksrc_index_lookup(struct fsl_spdif_priv
> *spdif_priv) +{
> + const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct device_node *np = pdev->dev.of_node;
> + struct clk *tmpclk;
> + char tmp[16];
> + int i, j;
> +
> + /* Start to decide tx/rxclk_src index */
> + spdif_priv->rxclk_src = -1;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + spdif_priv->txclk_src[i] = -1;
> +
> + /* Look up the clock source list to find the clock source index */
> + for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> + sprintf(tmp, "src%d", i);
> + tmpclk = devm_clk_get(&pdev->dev, tmp);
> + if (IS_ERR(tmpclk))
> + continue;
> +
> + /* Catch the clksrc identical to configured rxclk */
> + if (tmpclk == spdif_priv->rxclk)
> + spdif_priv->rxclk_src = i;
> +
> + for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
> + /* Catch the clksrc identical to configured txclk */
> + if (tmpclk == spdif_priv->txclk[j])
> + spdif_priv->txclk_src[j] = i;
> + }
> + }
> +
> + /* Plan B when failed to find the index for rx clock source */
> + if (spdif_priv->rxclk_src == -1) {
> + dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
> + spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + /* Plan B when failed to find the index for tx clock source */
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + if (spdif_priv->txclk_src[i] != -1)
> + continue;
> + dev_warn(&pdev->dev, "force to use core clock as %s clock.\n",
> rate[i]); + spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
> + spdif_priv->txclk[i] = spdif_priv->coreclk;
> + }
> +
> + if (i > SRPC_NODPLL_START1) {
> + /* Drop src5 for rxclk src */
> + spdif_priv->rxclk_src -= 1;
> +
> + /* Restore the offset to higher rxclk src */
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + }
> +
> + /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
> + if (!of_property_read_bool(np, "rx-clksrc-lock")) {
> + if (i < SRPC_NODPLL_START1)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + else if (i < SRPC_NODPLL_START2)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
> + }
> +}
> +
> +static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct clk **clk = spdif_priv->txclk;
> + u64 rate_ideal, rate_actual, sub, savesub;
> + u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
> + for (div = 1; div <= 128; div++) {
> + rate_ideal = rate[i] * (div + 1) * 64;
> + rate_actual = clk_round_rate(clk[i], rate_ideal);
> +
> + arate = rate_actual / 64;
> + arate /= div;
> + if (arate == rate[i]) {
> + savesub = 0;
> + spdif_priv->txclk_div[i] = div;
> + break;
> + } else if (arate / rate[i] == 1) {
> + sub = (arate - rate[i]) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + } else if (rate[i] / arate == 1) {
> + sub = (rate[i] - arate) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + }
> + }
> + dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
> + rate[i], spdif_priv->txclk_div[i]);
> + }
> +}
> +
> +static int fsl_spdif_probe(struct platform_device *pdev)
> +{
> + const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct fsl_spdif_priv *spdif_priv;
> + struct spdif_mixer_control *ctrl;
> + struct device_node *np = pdev->dev.of_node;
> + struct resource res;
> + void __iomem *regs;
> + int ret = 0, i;
> +
> + if (!of_device_is_available(np))
> + return -ENODEV;
I'm not sure your probe function will be ever called if the device is
unavailable. A simple check for !np would be enough.
> + /* The DAI name is the last part of the full name of the node. */
This has not been mentioned in binding documentation and I'm not sure this
is correct.
> + p = strrchr(np->full_name, '/') + 1;
You should be able to use np->name directly.
> + spdif_priv = devm_kzalloc(&pdev->dev,
> + sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
> + if (!spdif_priv) {
> + dev_err(&pdev->dev, "could not allocate DAI object\n");
> + return -ENOMEM;
> + }
> +
> + strcpy(spdif_priv->name, p);
> +
> + spdif_priv->pdev = pdev;
> +
> + /* Initialize this copy of the CPU DAI driver structure */
> + memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai,
> sizeof(fsl_spdif_dai)); + spdif_priv->cpu_dai_drv.name =
> spdif_priv->name;
> +
> + /* Get the addresses and IRQ */
> + ret = of_address_to_resource(np, 0, &res);
This has been already done for you by platform driver core. You can just
use platform_get_resource() to retrieve the already parsed resource.
> + if (ret) {
> + dev_err(&pdev->dev, "could not determine device resources\n");
> + return ret;
> + }
> +
> + regs = of_iomap(np, 0);
devm_ioremap_resource() would be better here.
> + if (IS_ERR(regs)) {
> + dev_err(&pdev->dev, "could not map device resources\n");
> + return PTR_ERR(regs);
> + }
> +
> + spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> + "core", regs, &fsl_spdif_regmap_config);
> + if (IS_ERR(spdif_priv->regmap)) {
> + dev_err(&pdev->dev, "regmap init failed\n");
> + ret = PTR_ERR(spdif_priv->regmap);
> + return ret;
> + }
> +
> + spdif_priv->irq = irq_of_parse_and_map(np, 0);
platform_get_resource()
> + if (spdif_priv->irq == NO_IRQ) {
> + dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
> + ret = -ENXIO;
> + goto error_iomap;
> + }
> +
> + /* The 'name' should not have any slashes in it. */
> + ret = request_irq(spdif_priv->irq, spdif_isr, 0,
> + spdif_priv->name, spdif_priv);
> + if (ret) {
> + dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
> + goto error_irqmap;
> + }
> +
> + spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
I'm not sure this is correct. You have not specified the order of clocks
in your DT bindings, so it is not guaranteed that "core" clock will be
always first.
IMHO it won't hurt to simply call devm_clk_get() with "core" as clock
name and will be much safer.
Best regards,
Tomasz
> + if (IS_ERR(spdif_priv->coreclk)) {
> + dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
> + ret = PTR_ERR(spdif_priv->coreclk);
> + goto error_irqreq;
> + }
> +
> + spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
> + if (IS_ERR(spdif_priv->rxclk)) {
> + dev_warn(&pdev->dev, "using core clock as rx clk\n");
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
> + if (IS_ERR(spdif_priv->txclk_main)) {
> + dev_warn(&pdev->dev, "using core clock as tx clk\n");
> + spdif_priv->txclk_main = spdif_priv->coreclk;
> + }
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
> + if (IS_ERR(spdif_priv->txclk[i])) {
> + dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
> + spdif_priv->txclk[i] = spdif_priv->txclk_main;
> + }
> + }
> +
> + spdif_clksrc_index_lookup(spdif_priv);
> +
> + /* We use regmap to control core clk, so no need to prepare it */
> + clk_prepare(spdif_priv->rxclk);
> + clk_prepare(spdif_priv->txclk_main);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_prepare(spdif_priv->txclk[i]);
> +
> + spdif_clk_cal_txdiv(spdif_priv);
> +
> + /* initial spinlock for control data */
> + ctrl = &spdif_priv->fsl_spdif_control;
> + spin_lock_init(&ctrl->ctl_lock);
> +
> + /* init tx channel status default value */
> + ctrl->ch_status[0] =
> + IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
> + ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
> + ctrl->ch_status[2] = 0x00;
> + ctrl->ch_status[3] =
> + IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
> +
> + atomic_set(&spdif_priv->dpll_locked, 0);
> +
> + spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
> + spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
> + spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
> + spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
> +
> + /* Register with ASoC */
> + dev_set_drvdata(&pdev->dev, spdif_priv);
> +
> + ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
> + &spdif_priv->cpu_dai_drv, 1);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
> + goto error_dev;
> + }
> +
> + ret = imx_pcm_dma_init(pdev);
> + if (ret) {
> + dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
> + goto error_component;
> + }
> +
> + return ret;
> +
> +error_component:
> + snd_soc_unregister_component(&pdev->dev);
> +error_dev:
> + dev_set_drvdata(&pdev->dev, NULL);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +error_irqreq:
> + free_irq(spdif_priv->irq, spdif_priv);
> +error_irqmap:
> + irq_dispose_mapping(spdif_priv->irq);
> +error_iomap:
> + iounmap(regs);
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_remove(struct platform_device *pdev)
> +{
> + struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
> + int i;
> +
> + imx_pcm_dma_exit(pdev);
> + snd_soc_unregister_component(&pdev->dev);
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +
> + free_irq(spdif_priv->irq, spdif_priv);
> + irq_dispose_mapping(spdif_priv->irq);
> +
> + dev_set_drvdata(&pdev->dev, NULL);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id fsl_spdif_dt_ids[] = {
> + { .compatible = "fsl,imx35-spdif", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
> +
> +static struct platform_driver fsl_spdif_driver = {
> + .driver = {
> + .name = "fsl-spdif-dai",
> + .owner = THIS_MODULE,
> + .of_match_table = fsl_spdif_dt_ids,
> + },
> + .probe = fsl_spdif_probe,
> + .remove = fsl_spdif_remove,
> +};
> +
> +module_platform_driver(fsl_spdif_driver);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:fsl-spdif-dai");
> diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
> new file mode 100644
> index 0000000..df183fb
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.h
> @@ -0,0 +1,224 @@
> +/*
> + * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Author: Nicolin Chen <b42378@freescale.com>
> + *
> + * Based on fsl_ssi.h
> + * Author: Timur Tabi <timur@freescale.com>
> + * Copyright 2007-2008 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#ifndef _FSL_SPDIF_DAI_H
> +#define _FSL_SPDIF_DAI_H
> +
> +/* S/PDIF Register Map */
> +#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
> +#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
> +#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
> +#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
> +#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
> +#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
> +#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
> +#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
> +#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
> +#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
> +#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
> +#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
> +#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
> +#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
> +#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
> +#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
> +#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
> +#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
> +
> +
> +/* SPDIF Configuration register */
> +#define SCR_RXFIFO_CTL_OFFSET 23
> +#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_OFF_OFFSET 22
> +#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_RST_OFFSET 21
> +#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_FSEL_OFFSET 19
> +#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
> +#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
> +#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_FSEL_OFFSET 15
> +#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_LOW_POWER (1 << 13)
> +#define SCR_SOFT_RESET (1 << 12)
> +#define SCR_TXFIFO_CTRL_OFFSET 10
> +#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_DMA_RX_EN_OFFSET 9
> +#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_TX_EN_OFFSET 8
> +#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_VAL_OFFSET 5
> +#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
> +#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
> +#define SCR_TXSEL_OFFSET 2
> +#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
> +#define SCR_USRC_SEL_OFFSET 0x0
> +#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
> +
> +/* SPDIF CDText control */
> +#define SRCD_CD_USER_OFFSET 1
> +#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
> +
> +/* SPDIF Phase Configuration register */
> +#define SRPC_DPLL_LOCKED (1 << 6)
> +#define SRPC_CLKSRC_SEL_OFFSET 7
> +#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
> +#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) &
> SRPC_CLKSRC_SEL_MASK) +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
> +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
> +#define SRPC_GAINSEL_OFFSET 3
> +#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
> +#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) &
> SRPC_GAINSEL_MASK) +
> +/* SPDIF rx clock source */
> +enum spdif_rxclk_src {
> + SRPC_CLKSRC_0 = 0,
> + SRPC_CLKSRC_1,
> + SRPC_CLKSRC_2,
> + SRPC_CLKSRC_3,
> + SRPC_CLKSRC_4,
> + SRPC_CLKSRC_5,
> + SRPC_CLKSRC_6,
> + SRPC_CLKSRC_7,
> + SRPC_CLKSRC_8,
> + SRPC_CLKSRC_9,
> + SRPC_CLKSRC_10,
> + SRPC_CLKSRC_11,
> + SRPC_CLKSRC_12,
> + SRPC_CLKSRC_13,
> + SRPC_CLKSRC_14,
> + SRPC_CLKSRC_15,
> +};
> +#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
> +#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
> +
> +enum spdif_gainsel {
> + GAINSEL_MULTI_24 = 0,
> + GAINSEL_MULTI_16,
> + GAINSEL_MULTI_12,
> + GAINSEL_MULTI_8,
> + GAINSEL_MULTI_6,
> + GAINSEL_MULTI_4,
> + GAINSEL_MULTI_3,
> +};
> +#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
> +#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
> +
> +/* SPDIF interrupt mask define */
> +#define INT_DPLL_LOCKED (1 << 20)
> +#define INT_TXFIFO_UNOV (1 << 19)
> +#define INT_TXFIFO_RESYNC (1 << 18)
> +#define INT_CNEW (1 << 17)
> +#define INT_VAL_NOGOOD (1 << 16)
> +#define INT_SYM_ERR (1 << 15)
> +#define INT_BIT_ERR (1 << 14)
> +#define INT_URX_FUL (1 << 10)
> +#define INT_URX_OV (1 << 9)
> +#define INT_QRX_FUL (1 << 8)
> +#define INT_QRX_OV (1 << 7)
> +#define INT_UQ_SYNC (1 << 6)
> +#define INT_UQ_ERR (1 << 5)
> +#define INT_RXFIFO_UNOV (1 << 4)
> +#define INT_RXFIFO_RESYNC (1 << 3)
> +#define INT_LOSS_LOCK (1 << 2)
> +#define INT_TX_EM (1 << 1)
> +#define INT_RXFIFO_FUL (1 << 0)
> +
> +/* SPDIF Clock register */
> +#define STC_SYSCLK_DIV_OFFSET 11
> +#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
> +#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_SYSCLK_DIV_MASK) +#define STC_TXCLK_SRC_OFFSET 8
> +#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
> +#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) &
> STC_TXCLK_SRC_MASK) +#define STC_TXCLK_ALL_EN_OFFSET 7
> +#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_DIV_OFFSET 0
> +#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
> +#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_TXCLK_DIV_MASK) +
> +/* SPDIF tx clksrc */
> +enum spdif_txclk_src {
> + STC_TXCLK_SRC_0 = 0,
> + STC_TXCLK_SRC_1,
> + STC_TXCLK_SRC_2,
> + STC_TXCLK_SRC_3,
> + STC_TXCLK_SRC_4,
> + STC_TXCLK_SRC_5,
> + STC_TXCLK_SRC_6,
> + STC_TXCLK_SRC_7,
> +};
> +#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
> +#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
> +
> +/* SPDIF tx rate */
> +enum spdif_txrate {
> + SPDIF_TXRATE_32000 = 0,
> + SPDIF_TXRATE_44100,
> + SPDIF_TXRATE_48000,
> +};
> +#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
> +
> +
> +#define SPDIF_CSTATUS_BYTE 6
> +#define SPDIF_UBITS_SIZE 96
> +#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
> +
> +
> +#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000)
> +
> +#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
> + SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000 | \
> + SNDRV_PCM_RATE_64000 | \
> + SNDRV_PCM_RATE_96000)
> +
> +#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
> + SNDRV_PCM_FMTBIT_S20_3LE | \
> + SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#endif /* _FSL_SPDIF_DAI_H */
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^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-15 12:18 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-15 12:18 UTC (permalink / raw)
To: Nicolin Chen, ian.campbell, pawel.moll, galak
Cc: mark.rutland, devicetree, alsa-devel, lars, swarren, festevam,
s.hauer, timur, rob.herring, broonie, p.zabel, shawn.guo,
linuxppc-dev
[-- Attachment #1.1: Type: text/plain, Size: 56452 bytes --]
Hi Nicolin,
[Ccing DT bindings maintainers]
On Thursday 15 of August 2013 19:26:39 Nicolin Chen wrote:
> This patch add S/PDIF controller driver for Freescale SoC.
>
> Signed-off-by: Nicolin Chen <b42378@freescale.com>
> ---
> .../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
> sound/soc/fsl/Kconfig | 3 +
> sound/soc/fsl/Makefile | 2 +
> sound/soc/fsl/fsl_spdif.c | 1336
> ++++++++++++++++++++ sound/soc/fsl/fsl_spdif.h
> | 224 ++++ 5 files changed, 1641 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/sound/fsl,spdif.txt create mode
> 100644 sound/soc/fsl/fsl_spdif.c
> create mode 100644 sound/soc/fsl/fsl_spdif.h
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> b/Documentation/devicetree/bindings/sound/fsl,spdif.txt new file mode
> 100644
> index 0000000..301b827
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> @@ -0,0 +1,76 @@
> +Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
> +
> +The Freescale S/PDIF audio block is a stereo transceiver that allows
> the +processor to receive and transmit digital audio via an coaxial
> cable or +a fibre cable.
> +
> +Required properties:
> +
> + - compatible : Compatible list, contains "fsl,<chip>-spdif".
> +
> + - reg : Offset and length of the register set for the device.
> +
> + - interrupts : Contains spdif interrupt.
> +
> + - dmas : Generic dma devicetree binding as described in
> + Documentation/devicetree/bindings/dma/dma.txt.
> +
> + - dma-names : Two dmas have to be defined, "tx" and "rx".
> +
> + - clocks : Contains an entry for each entry in clock-names.
> +
> + - clock-names : Includes the following entries:
> + name type comments
> + "core" Required The core clock of spdif controller
> +
> + "rx" Optional Rx clock source for spdif record.
> + If absent, will use core clock.
> +
> + "tx" Optional Tx clock source for spdif playback.
> + If absent, will use core clock.
> +
> + "tx-32000" Optional Tx clock source for 32000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-44100" Optional Tx clock source for 44100Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-48000" Optional Tx clock source for 48000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "src<0-7>" Optional Clock source list for tx and rx clock
> + to look up their clock source indexes.
> + This clock list should be identical to
> + the list of TxClk_Source bit value of
> + register SPDIF_STC. If absent or failed
> + to look up, tx and rx clock would then
> + ignore the "rx", "tx" "tx-32000",
> + "tx-44100", "tx-48000" clock phandles
> + and select the core clock as default
> + tx and rx clock.
I suspect a little abuse of clocks property here. From the description of
"core" and "src<0-7>" clocks I assume that the IP can have up to 9 clock
inputs - core clock and up to 8 extra source clocks. Is it correct?
If yes, this makes the "tx", "rx" and "tx-*" clocks describe
configuration, not hardware. IMHO it should be up to the driver which
source clocks to use for tx and rx channels and for each sampling rate.
> +Optional properties:
> +
> + - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel
> bit + of SPDIF_SRPC would be set a clock source that cares DPLL locked
> condition. +
This again looks like software configuration, not hardware description.
Could you elaborate a bit more on meaning of this property?
> +Example:
> +
> +spdif: spdif@02004000 {
> + compatible = "fsl,imx6q-spdif",
> + "fsl,imx35-spdif";
> + reg = <0x02004000 0x4000>;
> + interrupts = <0 52 0x04>;
> + dmas = <&sdma 14 18 0>,
> + <&sdma 15 18 0>;
> + dma-names = "rx", "tx";
> +
> + clocks = <&clks 197>, <&clks 3>, <&clks 197>,
> + <&clks 107>, <&clks 118>, <&clks 62>,
> + <&clks 139>;
> + clock-names = "core", "src0", "src1", "src2",
> + "src4", "src5", "src6";
> + rx-clksrc-lock;
> +
> + status = "okay";
> +};
> diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
> index e15f771..2c518db 100644
> --- a/sound/soc/fsl/Kconfig
> +++ b/sound/soc/fsl/Kconfig
> @@ -1,6 +1,9 @@
> config SND_SOC_FSL_SSI
> tristate
>
> +config SND_SOC_FSL_SPDIF
> + tristate
> +
> config SND_SOC_FSL_UTILS
> tristate
>
> diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
> index d4b4aa8..4b5970e 100644
> --- a/sound/soc/fsl/Makefile
> +++ b/sound/soc/fsl/Makefile
> @@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) +=
> snd-soc-p1022-rdk.o
>
> # Freescale PowerPC SSI/DMA Platform Support
> snd-soc-fsl-ssi-objs := fsl_ssi.o
> +snd-soc-fsl-spdif-objs := fsl_spdif.o
> snd-soc-fsl-utils-objs := fsl_utils.o
> snd-soc-fsl-dma-objs := fsl_dma.o
> obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
> +obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
> obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
> obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
>
> diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
> new file mode 100644
> index 0000000..173d699
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.c
> @@ -0,0 +1,1336 @@
> +/*
> + * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Based on stmp3xxx_spdif_dai.c
> + * Vladimir Barinov <vbarinov@embeddedalley.com>
> + * Copyright 2008 SigmaTel, Inc
> + * Copyright 2008 Embedded Alley Solutions, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +
> +#include <sound/asoundef.h>
> +#include <sound/soc.h>
> +#include <sound/dmaengine_pcm.h>
> +
> +#include "fsl_spdif.h"
> +#include "imx-pcm.h"
> +
> +#define FSL_SPDIF_TXFIFO_WML 0x8
> +#define FSL_SPDIF_RXFIFO_WML 0x8
> +
> +#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
> +#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |
> INT_URX_OV|\ + INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
> + INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
> +
> +/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel
> bit of SRPC */ +static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3,
> 0x4, 0xa, 0xb, }; +#define SRPC_NODPLL_START1 0x5
> +#define SRPC_NODPLL_START2 0xc
> +
> +/*
> + * SPDIF control structure
> + * Defines channel status, subcode and Q sub
> + */
> +struct spdif_mixer_control {
> + /* spinlock to access control data */
> + spinlock_t ctl_lock;
> +
> + /* IEC958 channel tx status bit */
> + unsigned char ch_status[4];
> +
> + /* User bits */
> + unsigned char subcode[2 * SPDIF_UBITS_SIZE];
> +
> + /* Q subcode part of user bits */
> + unsigned char qsub[2 * SPDIF_QSUB_SIZE];
> +
> + /* buffer ptrs for writer */
> + u32 upos;
> + u32 qpos;
> +
> + /* ready buffer index of the two buffers */
> + u32 ready_buf;
> +};
> +
> +struct fsl_spdif_priv {
> + struct spdif_mixer_control fsl_spdif_control;
> + struct snd_soc_dai_driver cpu_dai_drv;
> + struct platform_device *pdev;
> + struct regmap *regmap;
> + atomic_t dpll_locked;
> + u32 irq;
> + s8 rxclk_src;
> + s8 txclk_src[SPDIF_TXRATE_MAX];
> + u8 txclk_div[SPDIF_TXRATE_MAX];
> + struct clk *txclk[SPDIF_TXRATE_MAX];
> + struct clk *txclk_main;
> + struct clk *rxclk;
> + struct clk *coreclk;
> + struct snd_dmaengine_dai_dma_data dma_params_tx;
> + struct snd_dmaengine_dai_dma_data dma_params_rx;
> +
> + /* The name space will be allocated dynamically */
> + char name[0];
> +};
> +
> +
> +#ifdef DEBUG
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val, i;
> + int ret;
> +
> + /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
> + for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
> + ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
> + if (!ret)
> + dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
> + }
> +}
> +#else
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
> +#endif
> +
> +
> +/* DPLL locked and lock loss interrupt handler */
> +static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 locked;
> +
> + regmap_read(regmap, REG_SPDIF_SRPC, &locked);
> + locked &= SRPC_DPLL_LOCKED;
> +
> + dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
> + locked ? "locked" : "loss lock");
> +
> + atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
> +}
> +
> +/* Receiver found illegal symbol interrupt handler */
> +static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
> +
> + if (!atomic_read(&spdif_priv->dpll_locked)) {
> + /* dpll unlocked seems no audio stream */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
> + }
> +}
> +
> +/* U/Q Channel receive register full */
> +static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char
> name) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 *pos, size, val, reg;
> +
> + switch (name) {
> + case 'U':
> + pos = &ctrl->upos;
> + size = SPDIF_UBITS_SIZE;
> + reg = REG_SPDIF_SRU;
> + break;
> + case 'Q':
> + pos = &ctrl->qpos;
> + size = SPDIF_QSUB_SIZE;
> + reg = REG_SPDIF_SRQ;
> + break;
> + default:
> + return;
> + }
> +
> + dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
> +
> + if (*pos >= size * 2) {
> + *pos = 0;
> + } else if (unlikely((*pos % size) + 3 > size)) {
> + dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
> + return;
> + }
> +
> + regmap_read(regmap, reg, &val);
> + ctrl->subcode[*pos++] = val >> 16;
> + ctrl->subcode[*pos++] = val >> 8;
> + ctrl->subcode[*pos++] = val;
> +}
> +
> +/* U/Q Channel sync found */
> +static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
> +
> + /* U/Q buffer reset */
> + if (ctrl->qpos == 0)
> + return;
> +
> + /* set ready to this buffer */
> + ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
> +}
> +
> +/* U/Q Channel framing error */
> +static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
> +
> + /* read U/Q data and do buffer reset */
> + regmap_read(regmap, REG_SPDIF_SRU, &val);
> + regmap_read(regmap, REG_SPDIF_SRQ, &val);
> +
> + /* drop this U/Q buffer */
> + ctrl->ready_buf = 0;
> + ctrl->upos = 0;
> + ctrl->qpos = 0;
> +}
> +
> +/* Get spdif interrupt status and clear the interrupt */
> +static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, val2;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + regmap_read(regmap, REG_SPDIF_SIE, &val2);
> +
> + regmap_write(regmap, REG_SPDIF_SIC, val & val2);
> +
> + return val;
> +}
> +
> +static irqreturn_t spdif_isr(int irq, void *devid)
> +{
> + struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 sis;
> +
> + sis = spdif_intr_status_clear(spdif_priv);
> +
> + if (sis & INT_DPLL_LOCKED)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + if (sis & INT_TXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
> +
> + if (sis & INT_TXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
> +
> + if (sis & INT_CNEW)
> + dev_dbg(&pdev->dev, "isr: cstatus new\n");
> +
> + if (sis & INT_VAL_NOGOOD)
> + dev_dbg(&pdev->dev, "isr: validity flag no good\n");
> +
> + if (sis & INT_SYM_ERR)
> + spdif_irq_sym_error(spdif_priv);
> +
> + if (sis & INT_BIT_ERR)
> + dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
> +
> + if (sis & INT_URX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'U');
> +
> + if (sis & INT_URX_OV)
> + dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
> +
> + if (sis & INT_QRX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'Q');
> +
> + if (sis & INT_QRX_OV)
> + dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
> +
> + if (sis & INT_UQ_SYNC)
> + spdif_irq_uq_sync(spdif_priv);
> +
> + if (sis & INT_UQ_ERR)
> + spdif_irq_uq_err(spdif_priv);
> +
> + if (sis & INT_RXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
> +
> + if (sis & INT_RXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
> +
> + if (sis & INT_LOSS_LOCK)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + /* FIXME: Write Tx FIFO to clear TxEm */
> + if (sis & INT_TX_EM)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
> +
> + /* FIXME: Read Rx FIFO to clear RxFIFOFul */
> + if (sis & INT_RXFIFO_FUL)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, cycle = 1000;
> +
> + regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
> + regcache_sync(regmap);
> +
> + /* RESET bit would be cleared after finishing its reset procedure */
> + do {
> + regmap_read(regmap, REG_SPDIF_SCR, &val);
> + } while ((val & SCR_SOFT_RESET) && cycle--);
> +}
> +
> +static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
> + u8 mask, u8 cstatus)
> +{
> + ctrl->ch_status[3] &= ~mask;
> + ctrl->ch_status[3] |= cstatus & mask;
> +}
> +
> +static u8 reverse_bits(u8 input)
> +{
> + u8 tmp = input;
> +
> + tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
> + tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
> + tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
> +
> + return tmp;
> +}
> +
> +static void spdif_write_channel_status(struct fsl_spdif_priv
> *spdif_priv) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 ch_status;
> +
> + ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
> + (reverse_bits(ctrl->ch_status[1]) << 8) |
> + reverse_bits(ctrl->ch_status[2]);
> + regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
> +
> + ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
> + regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
> +}
> +
> +/* Set SPDIF PhaseConfig register for rx clock */
> +static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel, int dpll_locked)
> +{
> + enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
> + struct regmap *regmap = spdif_priv->regmap;
> +
> + if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
> + return -EINVAL;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRPC,
> + SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
> + SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
> +
> + return 0;
> +}
> +
> +static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + unsigned long rate_actual;
> +
> + rate_actual = clk_round_rate(clk, rate);
> + clk_set_rate(clk, rate_actual);
> +
> + return 0;
> +}
> +
> +static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
> + int sample_rate)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct regmap *regmap =
> spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + unsigned long clk = -1, div = 1, csfs = 0;
> + u32 stc, mask, rate;
> +
> + switch (sample_rate) {
> + case 32000:
> + rate = SPDIF_TXRATE_32000;
> + csfs = IEC958_AES3_CON_FS_32000;
> + break;
> + case 44100:
> + rate = SPDIF_TXRATE_44100;
> + csfs = IEC958_AES3_CON_FS_44100;
> + break;
> + case 48000:
> + rate = SPDIF_TXRATE_48000;
> + csfs = IEC958_AES3_CON_FS_48000;
> + break;
> + default:
> + dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + clk = spdif_priv->txclk_src[rate];
> + if (clk < 0) {
> + dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + div = spdif_priv->txclk_div[rate];
> + if (div == 0) {
> + dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
> + return -EINVAL;
> + }
> + /*
> + * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
> + * will divide by (div). So request 64 * fs * (div+1) which will
> + * get rounded.
> + */
> + spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div +
> 1)); +
> + dev_dbg(&pdev->dev, "expected clock rate = %d\n",
> + (int)(64 * sample_rate * div));
> + dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
> + (int)clk_get_rate(spdif_priv->txclk[rate]));
> +
> + /* set fs field in consumer channel status */
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
> +
> + /* select clock source and divisor */
> + stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
> + mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
> STC_TXCLK_DIV_MASK; + regmap_update_bits(regmap, REG_SPDIF_STC, mask,
> stc);
> +
> + dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
> +
> + return 0;
> +}
> +
> +int fsl_spdif_startup(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + /* Reset module and interrupts only for first initialization */
> + if (!cpu_dai->active) {
> + spdif_softreset(spdif_priv);
> +
> + /* disable all the interrupts */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
> + }
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
> + SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
> + SCR_TXFIFO_FSEL_IF8;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_enable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_enable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power up SPDIF module */
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
> +
> + return 0;
> +}
> +
> +static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = 0;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_disable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_disable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power down SPDIF module only if tx&rx are both inactive */
> + if (!cpu_dai->active) {
> + spdif_intr_status_clear(spdif_priv);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER,
> SCR_LOW_POWER); + }
> +}
> +
> +static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct platform_device *pdev
> = spdif_priv->pdev;
> + u32 sample_rate = params_rate(params);
> + int ret = 0;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + ret = spdif_set_sample_rate(substream, sample_rate);
> + if (ret) {
> + dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
> + __func__, sample_rate);
> + return ret;
> + }
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
> + IEC958_AES3_CON_CLOCK_1000PPM);
> + spdif_write_channel_status(spdif_priv);
> + } else {
> + /* setup rx clock source */
> + ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
> + }
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
> + int cmd, struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
> + u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
> + u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
> +
> + switch (cmd) {
> + case SNDRV_PCM_TRIGGER_START:
> + case SNDRV_PCM_TRIGGER_RESUME:
> + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
> + dumpregs(spdif_priv);
> + break;
> + case SNDRV_PCM_TRIGGER_STOP:
> + case SNDRV_PCM_TRIGGER_SUSPEND:
> + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +struct snd_soc_dai_ops fsl_spdif_dai_ops = {
> + .startup = fsl_spdif_startup,
> + .hw_params = fsl_spdif_hw_params,
> + .trigger = fsl_spdif_trigger,
> + .shutdown = fsl_spdif_shutdown,
> +};
> +
> +
> +/*
> + * ============================================
> + * FSL SPDIF IEC958 controller(mixer) functions
> + *
> + * Channel status get/put control
> + * User bit value get/put control
> + * Valid bit value get control
> + * DPLL lock status get control
> + * User bit sync mode selection control
> + * ============================================
> + */
> +
> +static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
> + uinfo->count = 1;
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + uvalue->value.iec958.status[0] = ctrl->ch_status[0];
> + uvalue->value.iec958.status[1] = ctrl->ch_status[1];
> + uvalue->value.iec958.status[2] = ctrl->ch_status[2];
> + uvalue->value.iec958.status[3] = ctrl->ch_status[3];
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + ctrl->ch_status[0] = uvalue->value.iec958.status[0];
> + ctrl->ch_status[1] = uvalue->value.iec958.status[1];
> + ctrl->ch_status[2] = uvalue->value.iec958.status[2];
> + ctrl->ch_status[3] = uvalue->value.iec958.status[3];
> +
> + spdif_write_channel_status(spdif_priv);
> +
> + return 0;
> +}
> +
> +/* Get channel status from SPDIF_RX_CCHAN register */
> +static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 cstatus, val;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + if (!(val & INT_CNEW)) {
> + return -EAGAIN;
> + }
> +
> + regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
> + ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[2] = cstatus & 0xFF;
> +
> + regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
> + ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[5] = cstatus & 0xFF;
> +
> + /* clear intr */
> + regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
> +
> + return 0;
> +}
> +
> +/*
> + * Get User bits (subcode) from chip value which readed out
> + * in UChannel register.
> + */
> +static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
> + memcpy(&ucontrol->value.iec958.subcode[0],
> + &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
> +static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
> + uinfo->count = SPDIF_QSUB_SIZE;
> +
> + return 0;
> +}
> +
> +/* Get Q subcode from chip value which readed out in QChannel register
> */ +static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
> + memcpy(&ucontrol->value.bytes.data[0],
> + &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Valid bit infomation */
> +static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/* Get valid good bit from interrupt status register */
> +static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + val = regmap_read(regmap, REG_SPDIF_SIS, &val);
> + ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
> + regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
> +
> + return 0;
> +}
> +
> +/* DPLL lock infomation */
> +static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 16000;
> + uinfo->value.integer.max = 96000;
> +
> + return 0;
> +}
> +
> +static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
> + 24, 16, 12, 8, 6, 4, 3,
> +};
> +
> +/* Get RX data clock rate given the SPDIF bus_clk */
> +static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u64 tmpval64, busclk_freq = 0;
> + u32 freqmeas, phaseconf;
> + enum spdif_rxclk_src clksrc;
> +
> + regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
> + regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
> +
> + clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
> + if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
> + /* get bus clock from system */
> + busclk_freq = clk_get_rate(spdif_priv->rxclk);
> + }
> +
> + /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
> + tmpval64 = (u64) busclk_freq * freqmeas;
> + do_div(tmpval64, gainsel_multi[gainsel] * 1024);
> + do_div(tmpval64, 128 * 1024);
> +
> + dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
> + dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
> + dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
> +
> + return (int)tmpval64;
> +}
> +
> +/*
> + * Get DPLL lock or not info from stable interrupt status register.
> + * User application must use this control to get locked,
> + * then can do next PCM operation
> + */
> +static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
> +
> + if (atomic_read(&spdif_priv->dpll_locked))
> + ucontrol->value.integer.value[0] = rate;
> + else
> + ucontrol->value.integer.value[0] = 0;
> +
> + return 0;
> +}
> +
> +/* User bit sync mode info */
> +static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + regmap_read(regmap, REG_SPDIF_SRCD, &val);
> + ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
> +
> + return 0;
> +}
> +
> +/* FSL SPDIF IEC958 controller defines */
> +static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
> + /* status cchanel controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
> + .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_pb_get,
> + .put = fsl_spdif_pb_put,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_capture_get,
> + },
> + /* user bits controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_subcode_get,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Q-subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_qinfo,
> + .get = fsl_spdif_qget,
> + },
> + /* valid bit error controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 V-Bit Errors",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_vbit_info,
> + .get = fsl_spdif_vbit_get,
> + },
> + /* DPLL lock info get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "RX Sample Rate",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_rxrate_info,
> + .get = fsl_spdif_rxrate_get,
> + },
> + /* User bit sync mode set/get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 USyncMode CDText",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_usync_info,
> + .get = fsl_spdif_usync_get,
> + .put = fsl_spdif_usync_put,
> + },
> +};
> +
> +static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
> +{
> + struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
> +
> + dai->playback_dma_data = &spdif_private->dma_params_tx;
> + dai->capture_dma_data = &spdif_private->dma_params_rx;
> +
> + snd_soc_add_dai_controls(dai, fsl_spdif_ctrls,
> ARRAY_SIZE(fsl_spdif_ctrls)); +
> + return 0;
> +}
> +
> +struct snd_soc_dai_driver fsl_spdif_dai = {
> + .probe = &fsl_spdif_dai_probe,
> + .playback = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_PLAYBACK,
> + .formats = FSL_SPDIF_FORMATS_PLAYBACK,
> + },
> + .capture = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_CAPTURE,
> + .formats = FSL_SPDIF_FORMATS_CAPTURE,
> + },
> + .ops = &fsl_spdif_dai_ops,
> +};
> +
> +static const struct snd_soc_component_driver fsl_spdif_component = {
> + .name = "fsl-spdif",
> +};
> +
> +/*
> + * ================
> + * FSL SPDIF REGMAP
> + * ================
> + */
> +
> +static bool fsl_spdif_readable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIS:
> + case REG_SPDIF_SRL:
> + case REG_SPDIF_SRR:
> + case REG_SPDIF_SRCSH:
> + case REG_SPDIF_SRCSL:
> + case REG_SPDIF_SRU:
> + case REG_SPDIF_SRQ:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_SRFM:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIC:
> + case REG_SPDIF_STL:
> + case REG_SPDIF_STR:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int
> reg) +{
> + /* Sync all registers after reset */
> + return true;
> +}
> +
> +static const struct regmap_config fsl_spdif_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> +
> + .max_register = REG_SPDIF_STC,
> + .readable_reg = fsl_spdif_readable_reg,
> + .writeable_reg = fsl_spdif_writeable_reg,
> + .volatile_reg = fsl_spdif_volatile_reg,
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
> +static void spdif_clksrc_index_lookup(struct fsl_spdif_priv
> *spdif_priv) +{
> + const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct device_node *np = pdev->dev.of_node;
> + struct clk *tmpclk;
> + char tmp[16];
> + int i, j;
> +
> + /* Start to decide tx/rxclk_src index */
> + spdif_priv->rxclk_src = -1;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + spdif_priv->txclk_src[i] = -1;
> +
> + /* Look up the clock source list to find the clock source index */
> + for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> + sprintf(tmp, "src%d", i);
> + tmpclk = devm_clk_get(&pdev->dev, tmp);
> + if (IS_ERR(tmpclk))
> + continue;
> +
> + /* Catch the clksrc identical to configured rxclk */
> + if (tmpclk == spdif_priv->rxclk)
> + spdif_priv->rxclk_src = i;
> +
> + for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
> + /* Catch the clksrc identical to configured txclk */
> + if (tmpclk == spdif_priv->txclk[j])
> + spdif_priv->txclk_src[j] = i;
> + }
> + }
> +
> + /* Plan B when failed to find the index for rx clock source */
> + if (spdif_priv->rxclk_src == -1) {
> + dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
> + spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + /* Plan B when failed to find the index for tx clock source */
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + if (spdif_priv->txclk_src[i] != -1)
> + continue;
> + dev_warn(&pdev->dev, "force to use core clock as %s clock.\n",
> rate[i]); + spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
> + spdif_priv->txclk[i] = spdif_priv->coreclk;
> + }
> +
> + if (i > SRPC_NODPLL_START1) {
> + /* Drop src5 for rxclk src */
> + spdif_priv->rxclk_src -= 1;
> +
> + /* Restore the offset to higher rxclk src */
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + }
> +
> + /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
> + if (!of_property_read_bool(np, "rx-clksrc-lock")) {
> + if (i < SRPC_NODPLL_START1)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + else if (i < SRPC_NODPLL_START2)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
> + }
> +}
> +
> +static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct clk **clk = spdif_priv->txclk;
> + u64 rate_ideal, rate_actual, sub, savesub;
> + u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
> + for (div = 1; div <= 128; div++) {
> + rate_ideal = rate[i] * (div + 1) * 64;
> + rate_actual = clk_round_rate(clk[i], rate_ideal);
> +
> + arate = rate_actual / 64;
> + arate /= div;
> + if (arate == rate[i]) {
> + savesub = 0;
> + spdif_priv->txclk_div[i] = div;
> + break;
> + } else if (arate / rate[i] == 1) {
> + sub = (arate - rate[i]) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + } else if (rate[i] / arate == 1) {
> + sub = (rate[i] - arate) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + }
> + }
> + dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
> + rate[i], spdif_priv->txclk_div[i]);
> + }
> +}
> +
> +static int fsl_spdif_probe(struct platform_device *pdev)
> +{
> + const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct fsl_spdif_priv *spdif_priv;
> + struct spdif_mixer_control *ctrl;
> + struct device_node *np = pdev->dev.of_node;
> + struct resource res;
> + void __iomem *regs;
> + int ret = 0, i;
> +
> + if (!of_device_is_available(np))
> + return -ENODEV;
I'm not sure your probe function will be ever called if the device is
unavailable. A simple check for !np would be enough.
> + /* The DAI name is the last part of the full name of the node. */
This has not been mentioned in binding documentation and I'm not sure this
is correct.
> + p = strrchr(np->full_name, '/') + 1;
You should be able to use np->name directly.
> + spdif_priv = devm_kzalloc(&pdev->dev,
> + sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
> + if (!spdif_priv) {
> + dev_err(&pdev->dev, "could not allocate DAI object\n");
> + return -ENOMEM;
> + }
> +
> + strcpy(spdif_priv->name, p);
> +
> + spdif_priv->pdev = pdev;
> +
> + /* Initialize this copy of the CPU DAI driver structure */
> + memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai,
> sizeof(fsl_spdif_dai)); + spdif_priv->cpu_dai_drv.name =
> spdif_priv->name;
> +
> + /* Get the addresses and IRQ */
> + ret = of_address_to_resource(np, 0, &res);
This has been already done for you by platform driver core. You can just
use platform_get_resource() to retrieve the already parsed resource.
> + if (ret) {
> + dev_err(&pdev->dev, "could not determine device resources\n");
> + return ret;
> + }
> +
> + regs = of_iomap(np, 0);
devm_ioremap_resource() would be better here.
> + if (IS_ERR(regs)) {
> + dev_err(&pdev->dev, "could not map device resources\n");
> + return PTR_ERR(regs);
> + }
> +
> + spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> + "core", regs, &fsl_spdif_regmap_config);
> + if (IS_ERR(spdif_priv->regmap)) {
> + dev_err(&pdev->dev, "regmap init failed\n");
> + ret = PTR_ERR(spdif_priv->regmap);
> + return ret;
> + }
> +
> + spdif_priv->irq = irq_of_parse_and_map(np, 0);
platform_get_resource()
> + if (spdif_priv->irq == NO_IRQ) {
> + dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
> + ret = -ENXIO;
> + goto error_iomap;
> + }
> +
> + /* The 'name' should not have any slashes in it. */
> + ret = request_irq(spdif_priv->irq, spdif_isr, 0,
> + spdif_priv->name, spdif_priv);
> + if (ret) {
> + dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
> + goto error_irqmap;
> + }
> +
> + spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
I'm not sure this is correct. You have not specified the order of clocks
in your DT bindings, so it is not guaranteed that "core" clock will be
always first.
IMHO it won't hurt to simply call devm_clk_get() with "core" as clock
name and will be much safer.
Best regards,
Tomasz
> + if (IS_ERR(spdif_priv->coreclk)) {
> + dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
> + ret = PTR_ERR(spdif_priv->coreclk);
> + goto error_irqreq;
> + }
> +
> + spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
> + if (IS_ERR(spdif_priv->rxclk)) {
> + dev_warn(&pdev->dev, "using core clock as rx clk\n");
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
> + if (IS_ERR(spdif_priv->txclk_main)) {
> + dev_warn(&pdev->dev, "using core clock as tx clk\n");
> + spdif_priv->txclk_main = spdif_priv->coreclk;
> + }
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
> + if (IS_ERR(spdif_priv->txclk[i])) {
> + dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
> + spdif_priv->txclk[i] = spdif_priv->txclk_main;
> + }
> + }
> +
> + spdif_clksrc_index_lookup(spdif_priv);
> +
> + /* We use regmap to control core clk, so no need to prepare it */
> + clk_prepare(spdif_priv->rxclk);
> + clk_prepare(spdif_priv->txclk_main);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_prepare(spdif_priv->txclk[i]);
> +
> + spdif_clk_cal_txdiv(spdif_priv);
> +
> + /* initial spinlock for control data */
> + ctrl = &spdif_priv->fsl_spdif_control;
> + spin_lock_init(&ctrl->ctl_lock);
> +
> + /* init tx channel status default value */
> + ctrl->ch_status[0] =
> + IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
> + ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
> + ctrl->ch_status[2] = 0x00;
> + ctrl->ch_status[3] =
> + IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
> +
> + atomic_set(&spdif_priv->dpll_locked, 0);
> +
> + spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
> + spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
> + spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
> + spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
> +
> + /* Register with ASoC */
> + dev_set_drvdata(&pdev->dev, spdif_priv);
> +
> + ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
> + &spdif_priv->cpu_dai_drv, 1);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
> + goto error_dev;
> + }
> +
> + ret = imx_pcm_dma_init(pdev);
> + if (ret) {
> + dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
> + goto error_component;
> + }
> +
> + return ret;
> +
> +error_component:
> + snd_soc_unregister_component(&pdev->dev);
> +error_dev:
> + dev_set_drvdata(&pdev->dev, NULL);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +error_irqreq:
> + free_irq(spdif_priv->irq, spdif_priv);
> +error_irqmap:
> + irq_dispose_mapping(spdif_priv->irq);
> +error_iomap:
> + iounmap(regs);
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_remove(struct platform_device *pdev)
> +{
> + struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
> + int i;
> +
> + imx_pcm_dma_exit(pdev);
> + snd_soc_unregister_component(&pdev->dev);
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +
> + free_irq(spdif_priv->irq, spdif_priv);
> + irq_dispose_mapping(spdif_priv->irq);
> +
> + dev_set_drvdata(&pdev->dev, NULL);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id fsl_spdif_dt_ids[] = {
> + { .compatible = "fsl,imx35-spdif", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
> +
> +static struct platform_driver fsl_spdif_driver = {
> + .driver = {
> + .name = "fsl-spdif-dai",
> + .owner = THIS_MODULE,
> + .of_match_table = fsl_spdif_dt_ids,
> + },
> + .probe = fsl_spdif_probe,
> + .remove = fsl_spdif_remove,
> +};
> +
> +module_platform_driver(fsl_spdif_driver);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:fsl-spdif-dai");
> diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
> new file mode 100644
> index 0000000..df183fb
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.h
> @@ -0,0 +1,224 @@
> +/*
> + * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Author: Nicolin Chen <b42378@freescale.com>
> + *
> + * Based on fsl_ssi.h
> + * Author: Timur Tabi <timur@freescale.com>
> + * Copyright 2007-2008 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#ifndef _FSL_SPDIF_DAI_H
> +#define _FSL_SPDIF_DAI_H
> +
> +/* S/PDIF Register Map */
> +#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
> +#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
> +#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
> +#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
> +#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
> +#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
> +#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
> +#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
> +#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
> +#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
> +#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
> +#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
> +#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
> +#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
> +#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
> +#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
> +#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
> +#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
> +
> +
> +/* SPDIF Configuration register */
> +#define SCR_RXFIFO_CTL_OFFSET 23
> +#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_OFF_OFFSET 22
> +#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_RST_OFFSET 21
> +#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_FSEL_OFFSET 19
> +#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
> +#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
> +#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_FSEL_OFFSET 15
> +#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_LOW_POWER (1 << 13)
> +#define SCR_SOFT_RESET (1 << 12)
> +#define SCR_TXFIFO_CTRL_OFFSET 10
> +#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_DMA_RX_EN_OFFSET 9
> +#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_TX_EN_OFFSET 8
> +#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_VAL_OFFSET 5
> +#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
> +#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
> +#define SCR_TXSEL_OFFSET 2
> +#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
> +#define SCR_USRC_SEL_OFFSET 0x0
> +#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
> +
> +/* SPDIF CDText control */
> +#define SRCD_CD_USER_OFFSET 1
> +#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
> +
> +/* SPDIF Phase Configuration register */
> +#define SRPC_DPLL_LOCKED (1 << 6)
> +#define SRPC_CLKSRC_SEL_OFFSET 7
> +#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
> +#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) &
> SRPC_CLKSRC_SEL_MASK) +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
> +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
> +#define SRPC_GAINSEL_OFFSET 3
> +#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
> +#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) &
> SRPC_GAINSEL_MASK) +
> +/* SPDIF rx clock source */
> +enum spdif_rxclk_src {
> + SRPC_CLKSRC_0 = 0,
> + SRPC_CLKSRC_1,
> + SRPC_CLKSRC_2,
> + SRPC_CLKSRC_3,
> + SRPC_CLKSRC_4,
> + SRPC_CLKSRC_5,
> + SRPC_CLKSRC_6,
> + SRPC_CLKSRC_7,
> + SRPC_CLKSRC_8,
> + SRPC_CLKSRC_9,
> + SRPC_CLKSRC_10,
> + SRPC_CLKSRC_11,
> + SRPC_CLKSRC_12,
> + SRPC_CLKSRC_13,
> + SRPC_CLKSRC_14,
> + SRPC_CLKSRC_15,
> +};
> +#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
> +#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
> +
> +enum spdif_gainsel {
> + GAINSEL_MULTI_24 = 0,
> + GAINSEL_MULTI_16,
> + GAINSEL_MULTI_12,
> + GAINSEL_MULTI_8,
> + GAINSEL_MULTI_6,
> + GAINSEL_MULTI_4,
> + GAINSEL_MULTI_3,
> +};
> +#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
> +#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
> +
> +/* SPDIF interrupt mask define */
> +#define INT_DPLL_LOCKED (1 << 20)
> +#define INT_TXFIFO_UNOV (1 << 19)
> +#define INT_TXFIFO_RESYNC (1 << 18)
> +#define INT_CNEW (1 << 17)
> +#define INT_VAL_NOGOOD (1 << 16)
> +#define INT_SYM_ERR (1 << 15)
> +#define INT_BIT_ERR (1 << 14)
> +#define INT_URX_FUL (1 << 10)
> +#define INT_URX_OV (1 << 9)
> +#define INT_QRX_FUL (1 << 8)
> +#define INT_QRX_OV (1 << 7)
> +#define INT_UQ_SYNC (1 << 6)
> +#define INT_UQ_ERR (1 << 5)
> +#define INT_RXFIFO_UNOV (1 << 4)
> +#define INT_RXFIFO_RESYNC (1 << 3)
> +#define INT_LOSS_LOCK (1 << 2)
> +#define INT_TX_EM (1 << 1)
> +#define INT_RXFIFO_FUL (1 << 0)
> +
> +/* SPDIF Clock register */
> +#define STC_SYSCLK_DIV_OFFSET 11
> +#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
> +#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_SYSCLK_DIV_MASK) +#define STC_TXCLK_SRC_OFFSET 8
> +#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
> +#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) &
> STC_TXCLK_SRC_MASK) +#define STC_TXCLK_ALL_EN_OFFSET 7
> +#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_DIV_OFFSET 0
> +#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
> +#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_TXCLK_DIV_MASK) +
> +/* SPDIF tx clksrc */
> +enum spdif_txclk_src {
> + STC_TXCLK_SRC_0 = 0,
> + STC_TXCLK_SRC_1,
> + STC_TXCLK_SRC_2,
> + STC_TXCLK_SRC_3,
> + STC_TXCLK_SRC_4,
> + STC_TXCLK_SRC_5,
> + STC_TXCLK_SRC_6,
> + STC_TXCLK_SRC_7,
> +};
> +#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
> +#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
> +
> +/* SPDIF tx rate */
> +enum spdif_txrate {
> + SPDIF_TXRATE_32000 = 0,
> + SPDIF_TXRATE_44100,
> + SPDIF_TXRATE_48000,
> +};
> +#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
> +
> +
> +#define SPDIF_CSTATUS_BYTE 6
> +#define SPDIF_UBITS_SIZE 96
> +#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
> +
> +
> +#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000)
> +
> +#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
> + SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000 | \
> + SNDRV_PCM_RATE_64000 | \
> + SNDRV_PCM_RATE_96000)
> +
> +#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
> + SNDRV_PCM_FMTBIT_S20_3LE | \
> + SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#endif /* _FSL_SPDIF_DAI_H */
[-- Attachment #1.2: This is a digitally signed message part. --]
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^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-15 12:18 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-15 12:18 UTC (permalink / raw)
To: Nicolin Chen, ian.campbell, pawel.moll, galak
Cc: mark.rutland, devicetree, alsa-devel, lars, swarren, festevam,
s.hauer, timur, rob.herring, broonie, p.zabel, shawn.guo,
linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 56452 bytes --]
Hi Nicolin,
[Ccing DT bindings maintainers]
On Thursday 15 of August 2013 19:26:39 Nicolin Chen wrote:
> This patch add S/PDIF controller driver for Freescale SoC.
>
> Signed-off-by: Nicolin Chen <b42378@freescale.com>
> ---
> .../devicetree/bindings/sound/fsl,spdif.txt | 76 ++
> sound/soc/fsl/Kconfig | 3 +
> sound/soc/fsl/Makefile | 2 +
> sound/soc/fsl/fsl_spdif.c | 1336
> ++++++++++++++++++++ sound/soc/fsl/fsl_spdif.h
> | 224 ++++ 5 files changed, 1641 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/sound/fsl,spdif.txt create mode
> 100644 sound/soc/fsl/fsl_spdif.c
> create mode 100644 sound/soc/fsl/fsl_spdif.h
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> b/Documentation/devicetree/bindings/sound/fsl,spdif.txt new file mode
> 100644
> index 0000000..301b827
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
> @@ -0,0 +1,76 @@
> +Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
> +
> +The Freescale S/PDIF audio block is a stereo transceiver that allows
> the +processor to receive and transmit digital audio via an coaxial
> cable or +a fibre cable.
> +
> +Required properties:
> +
> + - compatible : Compatible list, contains "fsl,<chip>-spdif".
> +
> + - reg : Offset and length of the register set for the device.
> +
> + - interrupts : Contains spdif interrupt.
> +
> + - dmas : Generic dma devicetree binding as described in
> + Documentation/devicetree/bindings/dma/dma.txt.
> +
> + - dma-names : Two dmas have to be defined, "tx" and "rx".
> +
> + - clocks : Contains an entry for each entry in clock-names.
> +
> + - clock-names : Includes the following entries:
> + name type comments
> + "core" Required The core clock of spdif controller
> +
> + "rx" Optional Rx clock source for spdif record.
> + If absent, will use core clock.
> +
> + "tx" Optional Tx clock source for spdif playback.
> + If absent, will use core clock.
> +
> + "tx-32000" Optional Tx clock source for 32000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-44100" Optional Tx clock source for 44100Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "tx-48000" Optional Tx clock source for 48000Hz sample rate
> + playback. If absent, will use tx clock.
> +
> + "src<0-7>" Optional Clock source list for tx and rx clock
> + to look up their clock source indexes.
> + This clock list should be identical to
> + the list of TxClk_Source bit value of
> + register SPDIF_STC. If absent or failed
> + to look up, tx and rx clock would then
> + ignore the "rx", "tx" "tx-32000",
> + "tx-44100", "tx-48000" clock phandles
> + and select the core clock as default
> + tx and rx clock.
I suspect a little abuse of clocks property here. From the description of
"core" and "src<0-7>" clocks I assume that the IP can have up to 9 clock
inputs - core clock and up to 8 extra source clocks. Is it correct?
If yes, this makes the "tx", "rx" and "tx-*" clocks describe
configuration, not hardware. IMHO it should be up to the driver which
source clocks to use for tx and rx channels and for each sampling rate.
> +Optional properties:
> +
> + - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel
> bit + of SPDIF_SRPC would be set a clock source that cares DPLL locked
> condition. +
This again looks like software configuration, not hardware description.
Could you elaborate a bit more on meaning of this property?
> +Example:
> +
> +spdif: spdif@02004000 {
> + compatible = "fsl,imx6q-spdif",
> + "fsl,imx35-spdif";
> + reg = <0x02004000 0x4000>;
> + interrupts = <0 52 0x04>;
> + dmas = <&sdma 14 18 0>,
> + <&sdma 15 18 0>;
> + dma-names = "rx", "tx";
> +
> + clocks = <&clks 197>, <&clks 3>, <&clks 197>,
> + <&clks 107>, <&clks 118>, <&clks 62>,
> + <&clks 139>;
> + clock-names = "core", "src0", "src1", "src2",
> + "src4", "src5", "src6";
> + rx-clksrc-lock;
> +
> + status = "okay";
> +};
> diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
> index e15f771..2c518db 100644
> --- a/sound/soc/fsl/Kconfig
> +++ b/sound/soc/fsl/Kconfig
> @@ -1,6 +1,9 @@
> config SND_SOC_FSL_SSI
> tristate
>
> +config SND_SOC_FSL_SPDIF
> + tristate
> +
> config SND_SOC_FSL_UTILS
> tristate
>
> diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
> index d4b4aa8..4b5970e 100644
> --- a/sound/soc/fsl/Makefile
> +++ b/sound/soc/fsl/Makefile
> @@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) +=
> snd-soc-p1022-rdk.o
>
> # Freescale PowerPC SSI/DMA Platform Support
> snd-soc-fsl-ssi-objs := fsl_ssi.o
> +snd-soc-fsl-spdif-objs := fsl_spdif.o
> snd-soc-fsl-utils-objs := fsl_utils.o
> snd-soc-fsl-dma-objs := fsl_dma.o
> obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
> +obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
> obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
> obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
>
> diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
> new file mode 100644
> index 0000000..173d699
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.c
> @@ -0,0 +1,1336 @@
> +/*
> + * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Based on stmp3xxx_spdif_dai.c
> + * Vladimir Barinov <vbarinov@embeddedalley.com>
> + * Copyright 2008 SigmaTel, Inc
> + * Copyright 2008 Embedded Alley Solutions, Inc
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/clk-private.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +
> +#include <sound/asoundef.h>
> +#include <sound/soc.h>
> +#include <sound/dmaengine_pcm.h>
> +
> +#include "fsl_spdif.h"
> +#include "imx-pcm.h"
> +
> +#define FSL_SPDIF_TXFIFO_WML 0x8
> +#define FSL_SPDIF_RXFIFO_WML 0x8
> +
> +#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
> +#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |
> INT_URX_OV|\ + INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
> + INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
> +
> +/* Index list for the values that has if (DPLL Locked) in ClkSrc_Sel
> bit of SRPC */ +static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3,
> 0x4, 0xa, 0xb, }; +#define SRPC_NODPLL_START1 0x5
> +#define SRPC_NODPLL_START2 0xc
> +
> +/*
> + * SPDIF control structure
> + * Defines channel status, subcode and Q sub
> + */
> +struct spdif_mixer_control {
> + /* spinlock to access control data */
> + spinlock_t ctl_lock;
> +
> + /* IEC958 channel tx status bit */
> + unsigned char ch_status[4];
> +
> + /* User bits */
> + unsigned char subcode[2 * SPDIF_UBITS_SIZE];
> +
> + /* Q subcode part of user bits */
> + unsigned char qsub[2 * SPDIF_QSUB_SIZE];
> +
> + /* buffer ptrs for writer */
> + u32 upos;
> + u32 qpos;
> +
> + /* ready buffer index of the two buffers */
> + u32 ready_buf;
> +};
> +
> +struct fsl_spdif_priv {
> + struct spdif_mixer_control fsl_spdif_control;
> + struct snd_soc_dai_driver cpu_dai_drv;
> + struct platform_device *pdev;
> + struct regmap *regmap;
> + atomic_t dpll_locked;
> + u32 irq;
> + s8 rxclk_src;
> + s8 txclk_src[SPDIF_TXRATE_MAX];
> + u8 txclk_div[SPDIF_TXRATE_MAX];
> + struct clk *txclk[SPDIF_TXRATE_MAX];
> + struct clk *txclk_main;
> + struct clk *rxclk;
> + struct clk *coreclk;
> + struct snd_dmaengine_dai_dma_data dma_params_tx;
> + struct snd_dmaengine_dai_dma_data dma_params_rx;
> +
> + /* The name space will be allocated dynamically */
> + char name[0];
> +};
> +
> +
> +#ifdef DEBUG
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val, i;
> + int ret;
> +
> + /* Valid address set of SPDIF is {[0x0-0x38], 0x44, 0x50} */
> + for (i = 0 ; i <= REG_SPDIF_STC; i += 4) {
> + ret = regmap_read(regmap, REG_SPDIF_SCR + i, &val);
> + if (!ret)
> + dev_dbg(&pdev->dev, "REG 0x%02x = 0x%06x\n", i, val);
> + }
> +}
> +#else
> +static void dumpregs(struct fsl_spdif_priv *spdif_priv) {}
> +#endif
> +
> +
> +/* DPLL locked and lock loss interrupt handler */
> +static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 locked;
> +
> + regmap_read(regmap, REG_SPDIF_SRPC, &locked);
> + locked &= SRPC_DPLL_LOCKED;
> +
> + dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
> + locked ? "locked" : "loss lock");
> +
> + atomic_set(&spdif_priv->dpll_locked, locked ? 1 : 0);
> +}
> +
> +/* Receiver found illegal symbol interrupt handler */
> +static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
> +
> + if (!atomic_read(&spdif_priv->dpll_locked)) {
> + /* dpll unlocked seems no audio stream */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
> + }
> +}
> +
> +/* U/Q Channel receive register full */
> +static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char
> name) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 *pos, size, val, reg;
> +
> + switch (name) {
> + case 'U':
> + pos = &ctrl->upos;
> + size = SPDIF_UBITS_SIZE;
> + reg = REG_SPDIF_SRU;
> + break;
> + case 'Q':
> + pos = &ctrl->qpos;
> + size = SPDIF_QSUB_SIZE;
> + reg = REG_SPDIF_SRQ;
> + break;
> + default:
> + return;
> + }
> +
> + dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
> +
> + if (*pos >= size * 2) {
> + *pos = 0;
> + } else if (unlikely((*pos % size) + 3 > size)) {
> + dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
> + return;
> + }
> +
> + regmap_read(regmap, reg, &val);
> + ctrl->subcode[*pos++] = val >> 16;
> + ctrl->subcode[*pos++] = val >> 8;
> + ctrl->subcode[*pos++] = val;
> +}
> +
> +/* U/Q Channel sync found */
> +static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct platform_device *pdev = spdif_priv->pdev;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
> +
> + /* U/Q buffer reset */
> + if (ctrl->qpos == 0)
> + return;
> +
> + /* set ready to this buffer */
> + ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
> +}
> +
> +/* U/Q Channel framing error */
> +static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 val;
> +
> + dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
> +
> + /* read U/Q data and do buffer reset */
> + regmap_read(regmap, REG_SPDIF_SRU, &val);
> + regmap_read(regmap, REG_SPDIF_SRQ, &val);
> +
> + /* drop this U/Q buffer */
> + ctrl->ready_buf = 0;
> + ctrl->upos = 0;
> + ctrl->qpos = 0;
> +}
> +
> +/* Get spdif interrupt status and clear the interrupt */
> +static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, val2;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + regmap_read(regmap, REG_SPDIF_SIE, &val2);
> +
> + regmap_write(regmap, REG_SPDIF_SIC, val & val2);
> +
> + return val;
> +}
> +
> +static irqreturn_t spdif_isr(int irq, void *devid)
> +{
> + struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 sis;
> +
> + sis = spdif_intr_status_clear(spdif_priv);
> +
> + if (sis & INT_DPLL_LOCKED)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + if (sis & INT_TXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
> +
> + if (sis & INT_TXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
> +
> + if (sis & INT_CNEW)
> + dev_dbg(&pdev->dev, "isr: cstatus new\n");
> +
> + if (sis & INT_VAL_NOGOOD)
> + dev_dbg(&pdev->dev, "isr: validity flag no good\n");
> +
> + if (sis & INT_SYM_ERR)
> + spdif_irq_sym_error(spdif_priv);
> +
> + if (sis & INT_BIT_ERR)
> + dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
> +
> + if (sis & INT_URX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'U');
> +
> + if (sis & INT_URX_OV)
> + dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
> +
> + if (sis & INT_QRX_FUL)
> + spdif_irq_uqrx_full(spdif_priv, 'Q');
> +
> + if (sis & INT_QRX_OV)
> + dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
> +
> + if (sis & INT_UQ_SYNC)
> + spdif_irq_uq_sync(spdif_priv);
> +
> + if (sis & INT_UQ_ERR)
> + spdif_irq_uq_err(spdif_priv);
> +
> + if (sis & INT_RXFIFO_UNOV)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
> +
> + if (sis & INT_RXFIFO_RESYNC)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
> +
> + if (sis & INT_LOSS_LOCK)
> + spdif_irq_dpll_lock(spdif_priv);
> +
> + /* FIXME: Write Tx FIFO to clear TxEm */
> + if (sis & INT_TX_EM)
> + dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
> +
> + /* FIXME: Read Rx FIFO to clear RxFIFOFul */
> + if (sis & INT_RXFIFO_FUL)
> + dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void spdif_softreset(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val, cycle = 1000;
> +
> + regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
> + regcache_sync(regmap);
> +
> + /* RESET bit would be cleared after finishing its reset procedure */
> + do {
> + regmap_read(regmap, REG_SPDIF_SCR, &val);
> + } while ((val & SCR_SOFT_RESET) && cycle--);
> +}
> +
> +static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
> + u8 mask, u8 cstatus)
> +{
> + ctrl->ch_status[3] &= ~mask;
> + ctrl->ch_status[3] |= cstatus & mask;
> +}
> +
> +static u8 reverse_bits(u8 input)
> +{
> + u8 tmp = input;
> +
> + tmp = ((tmp & 0b10101010) >> 1) | ((tmp << 1) & 0b10101010);
> + tmp = ((tmp & 0b11001100) >> 2) | ((tmp << 2) & 0b11001100);
> + tmp = ((tmp & 0b11110000) >> 4) | ((tmp << 4) & 0b11110000);
> +
> + return tmp;
> +}
> +
> +static void spdif_write_channel_status(struct fsl_spdif_priv
> *spdif_priv) +{
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u32 ch_status;
> +
> + ch_status = (reverse_bits(ctrl->ch_status[0]) << 16) |
> + (reverse_bits(ctrl->ch_status[1]) << 8) |
> + reverse_bits(ctrl->ch_status[2]);
> + regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
> +
> + ch_status = reverse_bits(ctrl->ch_status[3]) << 16;
> + regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
> +
> + dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
> +}
> +
> +/* Set SPDIF PhaseConfig register for rx clock */
> +static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel, int dpll_locked)
> +{
> + enum spdif_rxclk_src clksrc = spdif_priv->rxclk_src;
> + struct regmap *regmap = spdif_priv->regmap;
> +
> + if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
> + return -EINVAL;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRPC,
> + SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
> + SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
> +
> + return 0;
> +}
> +
> +static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> + unsigned long rate_actual;
> +
> + rate_actual = clk_round_rate(clk, rate);
> + clk_set_rate(clk, rate_actual);
> +
> + return 0;
> +}
> +
> +static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
> + int sample_rate)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct regmap *regmap =
> spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + unsigned long clk = -1, div = 1, csfs = 0;
> + u32 stc, mask, rate;
> +
> + switch (sample_rate) {
> + case 32000:
> + rate = SPDIF_TXRATE_32000;
> + csfs = IEC958_AES3_CON_FS_32000;
> + break;
> + case 44100:
> + rate = SPDIF_TXRATE_44100;
> + csfs = IEC958_AES3_CON_FS_44100;
> + break;
> + case 48000:
> + rate = SPDIF_TXRATE_48000;
> + csfs = IEC958_AES3_CON_FS_48000;
> + break;
> + default:
> + dev_err(&pdev->dev, "unsupported samplerate %d\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + clk = spdif_priv->txclk_src[rate];
> + if (clk < 0) {
> + dev_err(&pdev->dev, "no defined %d clk src\n", sample_rate);
> + return -EINVAL;
> + }
> +
> + div = spdif_priv->txclk_div[rate];
> + if (div == 0) {
> + dev_err(&pdev->dev, "tx clock source is dividing by zero\n");
> + return -EINVAL;
> + }
> + /*
> + * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
> + * will divide by (div). So request 64 * fs * (div+1) which will
> + * get rounded.
> + */
> + spdif_clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div +
> 1)); +
> + dev_dbg(&pdev->dev, "expected clock rate = %d\n",
> + (int)(64 * sample_rate * div));
> + dev_dbg(&pdev->dev, "acutal clock rate = %d\n",
> + (int)clk_get_rate(spdif_priv->txclk[rate]));
> +
> + /* set fs field in consumer channel status */
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
> +
> + /* select clock source and divisor */
> + stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
> + mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
> STC_TXCLK_DIV_MASK; + regmap_update_bits(regmap, REG_SPDIF_STC, mask,
> stc);
> +
> + dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
> +
> + return 0;
> +}
> +
> +int fsl_spdif_startup(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + /* Reset module and interrupts only for first initialization */
> + if (!cpu_dai->active) {
> + spdif_softreset(spdif_priv);
> +
> + /* disable all the interrupts */
> + regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
> + }
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
> + SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
> + SCR_TXFIFO_FSEL_IF8;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_enable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_enable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power up SPDIF module */
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
> +
> + return 0;
> +}
> +
> +static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *cpu_dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + u32 scr, mask, i;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + scr = 0;
> + mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
> + SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
> + SCR_TXFIFO_FSEL_MASK;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_disable(spdif_priv->txclk[i]);
> + } else {
> + scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
> + mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
> + SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
> + clk_disable(spdif_priv->rxclk);
> + }
> + regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
> +
> + /* Power down SPDIF module only if tx&rx are both inactive */
> + if (!cpu_dai->active) {
> + spdif_intr_status_clear(spdif_priv);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER,
> SCR_LOW_POWER); + }
> +}
> +
> +static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct spdif_mixer_control
> *ctrl = &spdif_priv->fsl_spdif_control; + struct platform_device *pdev
> = spdif_priv->pdev;
> + u32 sample_rate = params_rate(params);
> + int ret = 0;
> +
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + ret = spdif_set_sample_rate(substream, sample_rate);
> + if (ret) {
> + dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
> + __func__, sample_rate);
> + return ret;
> + }
> + spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
> + IEC958_AES3_CON_CLOCK_1000PPM);
> + spdif_write_channel_status(spdif_priv);
> + } else {
> + /* setup rx clock source */
> + ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
> + }
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
> + int cmd, struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_spdif_priv *spdif_priv =
> snd_soc_dai_get_drvdata(rtd->cpu_dai); + struct regmap *regmap =
> spdif_priv->regmap;
> + int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
> + u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
> + u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
> +
> + switch (cmd) {
> + case SNDRV_PCM_TRIGGER_START:
> + case SNDRV_PCM_TRIGGER_RESUME:
> + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
> + dumpregs(spdif_priv);
> + break;
> + case SNDRV_PCM_TRIGGER_STOP:
> + case SNDRV_PCM_TRIGGER_SUSPEND:
> + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
> + regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
> + regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +struct snd_soc_dai_ops fsl_spdif_dai_ops = {
> + .startup = fsl_spdif_startup,
> + .hw_params = fsl_spdif_hw_params,
> + .trigger = fsl_spdif_trigger,
> + .shutdown = fsl_spdif_shutdown,
> +};
> +
> +
> +/*
> + * ============================================
> + * FSL SPDIF IEC958 controller(mixer) functions
> + *
> + * Channel status get/put control
> + * User bit value get/put control
> + * Valid bit value get control
> + * DPLL lock status get control
> + * User bit sync mode selection control
> + * ============================================
> + */
> +
> +static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
> + uinfo->count = 1;
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + uvalue->value.iec958.status[0] = ctrl->ch_status[0];
> + uvalue->value.iec958.status[1] = ctrl->ch_status[1];
> + uvalue->value.iec958.status[2] = ctrl->ch_status[2];
> + uvalue->value.iec958.status[3] = ctrl->ch_status[3];
> +
> + return 0;
> +}
> +
> +static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *uvalue)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> +
> + ctrl->ch_status[0] = uvalue->value.iec958.status[0];
> + ctrl->ch_status[1] = uvalue->value.iec958.status[1];
> + ctrl->ch_status[2] = uvalue->value.iec958.status[2];
> + ctrl->ch_status[3] = uvalue->value.iec958.status[3];
> +
> + spdif_write_channel_status(spdif_priv);
> +
> + return 0;
> +}
> +
> +/* Get channel status from SPDIF_RX_CCHAN register */
> +static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 cstatus, val;
> +
> + regmap_read(regmap, REG_SPDIF_SIS, &val);
> + if (!(val & INT_CNEW)) {
> + return -EAGAIN;
> + }
> +
> + regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
> + ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[2] = cstatus & 0xFF;
> +
> + regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
> + ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
> + ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
> + ucontrol->value.iec958.status[5] = cstatus & 0xFF;
> +
> + /* clear intr */
> + regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
> +
> + return 0;
> +}
> +
> +/*
> + * Get User bits (subcode) from chip value which readed out
> + * in UChannel register.
> + */
> +static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
> + memcpy(&ucontrol->value.iec958.subcode[0],
> + &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
> +static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
> + uinfo->count = SPDIF_QSUB_SIZE;
> +
> + return 0;
> +}
> +
> +/* Get Q subcode from chip value which readed out in QChannel register
> */ +static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&ctrl->ctl_lock, flags);
> + if (ctrl->ready_buf) {
> + int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
> + memcpy(&ucontrol->value.bytes.data[0],
> + &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
> + } else {
> + ret = -EAGAIN;
> + }
> + spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
> +
> + return ret;
> +}
> +
> +/* Valid bit infomation */
> +static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/* Get valid good bit from interrupt status register */
> +static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + val = regmap_read(regmap, REG_SPDIF_SIS, &val);
> + ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
> + regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
> +
> + return 0;
> +}
> +
> +/* DPLL lock infomation */
> +static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 16000;
> + uinfo->value.integer.max = 96000;
> +
> + return 0;
> +}
> +
> +static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
> + 24, 16, 12, 8, 6, 4, 3,
> +};
> +
> +/* Get RX data clock rate given the SPDIF bus_clk */
> +static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
> + enum spdif_gainsel gainsel)
> +{
> + struct regmap *regmap = spdif_priv->regmap;
> + struct platform_device *pdev = spdif_priv->pdev;
> + u64 tmpval64, busclk_freq = 0;
> + u32 freqmeas, phaseconf;
> + enum spdif_rxclk_src clksrc;
> +
> + regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
> + regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
> +
> + clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
> + if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
> + /* get bus clock from system */
> + busclk_freq = clk_get_rate(spdif_priv->rxclk);
> + }
> +
> + /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
> + tmpval64 = (u64) busclk_freq * freqmeas;
> + do_div(tmpval64, gainsel_multi[gainsel] * 1024);
> + do_div(tmpval64, 128 * 1024);
> +
> + dev_dbg(&pdev->dev, "FreqMeas: %d\n", (int)freqmeas);
> + dev_dbg(&pdev->dev, "BusclkFreq: %d\n", (int)busclk_freq);
> + dev_dbg(&pdev->dev, "RxRate: %d\n", (int)tmpval64);
> +
> + return (int)tmpval64;
> +}
> +
> +/*
> + * Get DPLL lock or not info from stable interrupt status register.
> + * User application must use this control to get locked,
> + * then can do next PCM operation
> + */
> +static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
> +
> + if (atomic_read(&spdif_priv->dpll_locked))
> + ucontrol->value.integer.value[0] = rate;
> + else
> + ucontrol->value.integer.value[0] = 0;
> +
> + return 0;
> +}
> +
> +/* User bit sync mode info */
> +static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + uinfo->value.integer.max = 1;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val;
> +
> + regmap_read(regmap, REG_SPDIF_SRCD, &val);
> + ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
> +
> + return 0;
> +}
> +
> +/*
> + * User bit sync mode:
> + * 1 CD User channel subcode
> + * 0 Non-CD data
> + */
> +static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
> + struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
> + struct regmap *regmap = spdif_priv->regmap;
> + u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
> +
> + regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
> +
> + return 0;
> +}
> +
> +/* FSL SPDIF IEC958 controller defines */
> +static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
> + /* status cchanel controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
> + .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_pb_get,
> + .put = fsl_spdif_pb_put,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_capture_get,
> + },
> + /* user bits controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_info,
> + .get = fsl_spdif_subcode_get,
> + },
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 Q-subcode Capture Default",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_qinfo,
> + .get = fsl_spdif_qget,
> + },
> + /* valid bit error controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 V-Bit Errors",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_vbit_info,
> + .get = fsl_spdif_vbit_get,
> + },
> + /* DPLL lock info get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "RX Sample Rate",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_rxrate_info,
> + .get = fsl_spdif_rxrate_get,
> + },
> + /* User bit sync mode set/get controller */
> + {
> + .iface = SNDRV_CTL_ELEM_IFACE_PCM,
> + .name = "IEC958 USyncMode CDText",
> + .access = SNDRV_CTL_ELEM_ACCESS_READ |
> + SNDRV_CTL_ELEM_ACCESS_WRITE |
> + SNDRV_CTL_ELEM_ACCESS_VOLATILE,
> + .info = fsl_spdif_usync_info,
> + .get = fsl_spdif_usync_get,
> + .put = fsl_spdif_usync_put,
> + },
> +};
> +
> +static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
> +{
> + struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
> +
> + dai->playback_dma_data = &spdif_private->dma_params_tx;
> + dai->capture_dma_data = &spdif_private->dma_params_rx;
> +
> + snd_soc_add_dai_controls(dai, fsl_spdif_ctrls,
> ARRAY_SIZE(fsl_spdif_ctrls)); +
> + return 0;
> +}
> +
> +struct snd_soc_dai_driver fsl_spdif_dai = {
> + .probe = &fsl_spdif_dai_probe,
> + .playback = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_PLAYBACK,
> + .formats = FSL_SPDIF_FORMATS_PLAYBACK,
> + },
> + .capture = {
> + .channels_min = 2,
> + .channels_max = 2,
> + .rates = FSL_SPDIF_RATES_CAPTURE,
> + .formats = FSL_SPDIF_FORMATS_CAPTURE,
> + },
> + .ops = &fsl_spdif_dai_ops,
> +};
> +
> +static const struct snd_soc_component_driver fsl_spdif_component = {
> + .name = "fsl-spdif",
> +};
> +
> +/*
> + * ================
> + * FSL SPDIF REGMAP
> + * ================
> + */
> +
> +static bool fsl_spdif_readable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIS:
> + case REG_SPDIF_SRL:
> + case REG_SPDIF_SRR:
> + case REG_SPDIF_SRCSH:
> + case REG_SPDIF_SRCSL:
> + case REG_SPDIF_SRU:
> + case REG_SPDIF_SRQ:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_SRFM:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int
> reg) +{
> + switch (reg) {
> + case REG_SPDIF_SCR:
> + case REG_SPDIF_SRCD:
> + case REG_SPDIF_SRPC:
> + case REG_SPDIF_SIE:
> + case REG_SPDIF_SIC:
> + case REG_SPDIF_STL:
> + case REG_SPDIF_STR:
> + case REG_SPDIF_STCSCH:
> + case REG_SPDIF_STCSCL:
> + case REG_SPDIF_STC:
> + return true;
> + default:
> + return false;
> + };
> +}
> +
> +static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int
> reg) +{
> + /* Sync all registers after reset */
> + return true;
> +}
> +
> +static const struct regmap_config fsl_spdif_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> +
> + .max_register = REG_SPDIF_STC,
> + .readable_reg = fsl_spdif_readable_reg,
> + .writeable_reg = fsl_spdif_writeable_reg,
> + .volatile_reg = fsl_spdif_volatile_reg,
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
> +static void spdif_clksrc_index_lookup(struct fsl_spdif_priv
> *spdif_priv) +{
> + const char *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct device_node *np = pdev->dev.of_node;
> + struct clk *tmpclk;
> + char tmp[16];
> + int i, j;
> +
> + /* Start to decide tx/rxclk_src index */
> + spdif_priv->rxclk_src = -1;
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + spdif_priv->txclk_src[i] = -1;
> +
> + /* Look up the clock source list to find the clock source index */
> + for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> + sprintf(tmp, "src%d", i);
> + tmpclk = devm_clk_get(&pdev->dev, tmp);
> + if (IS_ERR(tmpclk))
> + continue;
> +
> + /* Catch the clksrc identical to configured rxclk */
> + if (tmpclk == spdif_priv->rxclk)
> + spdif_priv->rxclk_src = i;
> +
> + for (j = 0; j < SPDIF_TXRATE_MAX; j++) {
> + /* Catch the clksrc identical to configured txclk */
> + if (tmpclk == spdif_priv->txclk[j])
> + spdif_priv->txclk_src[j] = i;
> + }
> + }
> +
> + /* Plan B when failed to find the index for rx clock source */
> + if (spdif_priv->rxclk_src == -1) {
> + dev_warn(&pdev->dev, "force to use core clock as rx clock.\n");
> + spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + /* Plan B when failed to find the index for tx clock source */
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + if (spdif_priv->txclk_src[i] != -1)
> + continue;
> + dev_warn(&pdev->dev, "force to use core clock as %s clock.\n",
> rate[i]); + spdif_priv->txclk_src[i] = DEFAULT_TXCLK_SRC;
> + spdif_priv->txclk[i] = spdif_priv->coreclk;
> + }
> +
> + if (i > SRPC_NODPLL_START1) {
> + /* Drop src5 for rxclk src */
> + spdif_priv->rxclk_src -= 1;
> +
> + /* Restore the offset to higher rxclk src */
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + }
> +
> + /* Use the un-conditioned conf for rx clock if no rx-clksrc-lock */
> + if (!of_property_read_bool(np, "rx-clksrc-lock")) {
> + if (i < SRPC_NODPLL_START1)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET1;
> + else if (i < SRPC_NODPLL_START2)
> + spdif_priv->rxclk_src += SRPC_CLKSRC_SEL_LOCKED_OFFSET2;
> + }
> +}
> +
> +static void spdif_clk_cal_txdiv(struct fsl_spdif_priv *spdif_priv)
> +{
> + struct platform_device *pdev = spdif_priv->pdev;
> + struct clk **clk = spdif_priv->txclk;
> + u64 rate_ideal, rate_actual, sub, savesub;
> + u32 i, div, arate, rate[] = { 32000, 44100, 48000, };
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++, savesub = 100000) {
> + for (div = 1; div <= 128; div++) {
> + rate_ideal = rate[i] * (div + 1) * 64;
> + rate_actual = clk_round_rate(clk[i], rate_ideal);
> +
> + arate = rate_actual / 64;
> + arate /= div;
> + if (arate == rate[i]) {
> + savesub = 0;
> + spdif_priv->txclk_div[i] = div;
> + break;
> + } else if (arate / rate[i] == 1) {
> + sub = (arate - rate[i]) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + } else if (rate[i] / arate == 1) {
> + sub = (rate[i] - arate) * 100000;
> + do_div(sub, rate[i]);
> + if (sub < savesub) {
> + savesub = sub;
> + spdif_priv->txclk_div[i] = div;
> + }
> + }
> + }
> + dev_dbg(&pdev->dev, "calculated %dHz div: %d\n",
> + rate[i], spdif_priv->txclk_div[i]);
> + }
> +}
> +
> +static int fsl_spdif_probe(struct platform_device *pdev)
> +{
> + const char *p, *rate[] = { "tx-32000", "tx-44100", "tx-48000", };
> + struct fsl_spdif_priv *spdif_priv;
> + struct spdif_mixer_control *ctrl;
> + struct device_node *np = pdev->dev.of_node;
> + struct resource res;
> + void __iomem *regs;
> + int ret = 0, i;
> +
> + if (!of_device_is_available(np))
> + return -ENODEV;
I'm not sure your probe function will be ever called if the device is
unavailable. A simple check for !np would be enough.
> + /* The DAI name is the last part of the full name of the node. */
This has not been mentioned in binding documentation and I'm not sure this
is correct.
> + p = strrchr(np->full_name, '/') + 1;
You should be able to use np->name directly.
> + spdif_priv = devm_kzalloc(&pdev->dev,
> + sizeof(struct fsl_spdif_priv) + strlen(p) + 1, GFP_KERNEL);
> + if (!spdif_priv) {
> + dev_err(&pdev->dev, "could not allocate DAI object\n");
> + return -ENOMEM;
> + }
> +
> + strcpy(spdif_priv->name, p);
> +
> + spdif_priv->pdev = pdev;
> +
> + /* Initialize this copy of the CPU DAI driver structure */
> + memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai,
> sizeof(fsl_spdif_dai)); + spdif_priv->cpu_dai_drv.name =
> spdif_priv->name;
> +
> + /* Get the addresses and IRQ */
> + ret = of_address_to_resource(np, 0, &res);
This has been already done for you by platform driver core. You can just
use platform_get_resource() to retrieve the already parsed resource.
> + if (ret) {
> + dev_err(&pdev->dev, "could not determine device resources\n");
> + return ret;
> + }
> +
> + regs = of_iomap(np, 0);
devm_ioremap_resource() would be better here.
> + if (IS_ERR(regs)) {
> + dev_err(&pdev->dev, "could not map device resources\n");
> + return PTR_ERR(regs);
> + }
> +
> + spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> + "core", regs, &fsl_spdif_regmap_config);
> + if (IS_ERR(spdif_priv->regmap)) {
> + dev_err(&pdev->dev, "regmap init failed\n");
> + ret = PTR_ERR(spdif_priv->regmap);
> + return ret;
> + }
> +
> + spdif_priv->irq = irq_of_parse_and_map(np, 0);
platform_get_resource()
> + if (spdif_priv->irq == NO_IRQ) {
> + dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
> + ret = -ENXIO;
> + goto error_iomap;
> + }
> +
> + /* The 'name' should not have any slashes in it. */
> + ret = request_irq(spdif_priv->irq, spdif_isr, 0,
> + spdif_priv->name, spdif_priv);
> + if (ret) {
> + dev_err(&pdev->dev, "could not claim irq %u\n", spdif_priv->irq);
> + goto error_irqmap;
> + }
> +
> + spdif_priv->coreclk = devm_clk_get(&pdev->dev, NULL);
I'm not sure this is correct. You have not specified the order of clocks
in your DT bindings, so it is not guaranteed that "core" clock will be
always first.
IMHO it won't hurt to simply call devm_clk_get() with "core" as clock
name and will be much safer.
Best regards,
Tomasz
> + if (IS_ERR(spdif_priv->coreclk)) {
> + dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
> + ret = PTR_ERR(spdif_priv->coreclk);
> + goto error_irqreq;
> + }
> +
> + spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rx");
> + if (IS_ERR(spdif_priv->rxclk)) {
> + dev_warn(&pdev->dev, "using core clock as rx clk\n");
> + spdif_priv->rxclk = spdif_priv->coreclk;
> + }
> +
> + spdif_priv->txclk_main = devm_clk_get(&pdev->dev, "tx");
> + if (IS_ERR(spdif_priv->txclk_main)) {
> + dev_warn(&pdev->dev, "using core clock as tx clk\n");
> + spdif_priv->txclk_main = spdif_priv->coreclk;
> + }
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
> + spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, rate[i]);
> + if (IS_ERR(spdif_priv->txclk[i])) {
> + dev_warn(&pdev->dev, "using tx clock as %s clk\n", rate[i]);
> + spdif_priv->txclk[i] = spdif_priv->txclk_main;
> + }
> + }
> +
> + spdif_clksrc_index_lookup(spdif_priv);
> +
> + /* We use regmap to control core clk, so no need to prepare it */
> + clk_prepare(spdif_priv->rxclk);
> + clk_prepare(spdif_priv->txclk_main);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_prepare(spdif_priv->txclk[i]);
> +
> + spdif_clk_cal_txdiv(spdif_priv);
> +
> + /* initial spinlock for control data */
> + ctrl = &spdif_priv->fsl_spdif_control;
> + spin_lock_init(&ctrl->ctl_lock);
> +
> + /* init tx channel status default value */
> + ctrl->ch_status[0] =
> + IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
> + ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
> + ctrl->ch_status[2] = 0x00;
> + ctrl->ch_status[3] =
> + IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
> +
> + atomic_set(&spdif_priv->dpll_locked, 0);
> +
> + spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
> + spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
> + spdif_priv->dma_params_tx.addr = res.start + REG_SPDIF_STL;
> + spdif_priv->dma_params_rx.addr = res.start + REG_SPDIF_SRL;
> +
> + /* Register with ASoC */
> + dev_set_drvdata(&pdev->dev, spdif_priv);
> +
> + ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
> + &spdif_priv->cpu_dai_drv, 1);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
> + goto error_dev;
> + }
> +
> + ret = imx_pcm_dma_init(pdev);
> + if (ret) {
> + dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
> + goto error_component;
> + }
> +
> + return ret;
> +
> +error_component:
> + snd_soc_unregister_component(&pdev->dev);
> +error_dev:
> + dev_set_drvdata(&pdev->dev, NULL);
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +error_irqreq:
> + free_irq(spdif_priv->irq, spdif_priv);
> +error_irqmap:
> + irq_dispose_mapping(spdif_priv->irq);
> +error_iomap:
> + iounmap(regs);
> +
> + return ret;
> +}
> +
> +static int fsl_spdif_remove(struct platform_device *pdev)
> +{
> + struct fsl_spdif_priv *spdif_priv = platform_get_drvdata(pdev);
> + int i;
> +
> + imx_pcm_dma_exit(pdev);
> + snd_soc_unregister_component(&pdev->dev);
> +
> + for (i = 0; i < SPDIF_TXRATE_MAX; i++)
> + clk_unprepare(spdif_priv->txclk[i]);
> + clk_unprepare(spdif_priv->txclk_main);
> + clk_unprepare(spdif_priv->rxclk);
> +
> + free_irq(spdif_priv->irq, spdif_priv);
> + irq_dispose_mapping(spdif_priv->irq);
> +
> + dev_set_drvdata(&pdev->dev, NULL);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id fsl_spdif_dt_ids[] = {
> + { .compatible = "fsl,imx35-spdif", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
> +
> +static struct platform_driver fsl_spdif_driver = {
> + .driver = {
> + .name = "fsl-spdif-dai",
> + .owner = THIS_MODULE,
> + .of_match_table = fsl_spdif_dt_ids,
> + },
> + .probe = fsl_spdif_probe,
> + .remove = fsl_spdif_remove,
> +};
> +
> +module_platform_driver(fsl_spdif_driver);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:fsl-spdif-dai");
> diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h
> new file mode 100644
> index 0000000..df183fb
> --- /dev/null
> +++ b/sound/soc/fsl/fsl_spdif.h
> @@ -0,0 +1,224 @@
> +/*
> + * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + * Author: Nicolin Chen <b42378@freescale.com>
> + *
> + * Based on fsl_ssi.h
> + * Author: Timur Tabi <timur@freescale.com>
> + * Copyright 2007-2008 Freescale Semiconductor, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> License + * version 2. This program is licensed "as is" without any
> warranty of any + * kind, whether express or implied.
> + */
> +
> +#ifndef _FSL_SPDIF_DAI_H
> +#define _FSL_SPDIF_DAI_H
> +
> +/* S/PDIF Register Map */
> +#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
> +#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
> +#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
> +#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
> +#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
> +#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
> +#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
> +#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
> +#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
> +#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
> +#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
> +#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
> +#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
> +#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
> +#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
> +#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
> +#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
> +#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
> +
> +
> +/* SPDIF Configuration register */
> +#define SCR_RXFIFO_CTL_OFFSET 23
> +#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
> +#define SCR_RXFIFO_OFF_OFFSET 22
> +#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
> +#define SCR_RXFIFO_RST_OFFSET 21
> +#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
> +#define SCR_RXFIFO_FSEL_OFFSET 19
> +#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
> +#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
> +#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
> +#define SCR_TXFIFO_FSEL_OFFSET 15
> +#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
> +#define SCR_LOW_POWER (1 << 13)
> +#define SCR_SOFT_RESET (1 << 12)
> +#define SCR_TXFIFO_CTRL_OFFSET 10
> +#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
> +#define SCR_DMA_RX_EN_OFFSET 9
> +#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
> +#define SCR_DMA_TX_EN_OFFSET 8
> +#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
> +#define SCR_VAL_OFFSET 5
> +#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
> +#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
> +#define SCR_TXSEL_OFFSET 2
> +#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
> +#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
> +#define SCR_USRC_SEL_OFFSET 0x0
> +#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
> +#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
> +
> +/* SPDIF CDText control */
> +#define SRCD_CD_USER_OFFSET 1
> +#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
> +
> +/* SPDIF Phase Configuration register */
> +#define SRPC_DPLL_LOCKED (1 << 6)
> +#define SRPC_CLKSRC_SEL_OFFSET 7
> +#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
> +#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) &
> SRPC_CLKSRC_SEL_MASK) +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
> +#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
> +#define SRPC_GAINSEL_OFFSET 3
> +#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
> +#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) &
> SRPC_GAINSEL_MASK) +
> +/* SPDIF rx clock source */
> +enum spdif_rxclk_src {
> + SRPC_CLKSRC_0 = 0,
> + SRPC_CLKSRC_1,
> + SRPC_CLKSRC_2,
> + SRPC_CLKSRC_3,
> + SRPC_CLKSRC_4,
> + SRPC_CLKSRC_5,
> + SRPC_CLKSRC_6,
> + SRPC_CLKSRC_7,
> + SRPC_CLKSRC_8,
> + SRPC_CLKSRC_9,
> + SRPC_CLKSRC_10,
> + SRPC_CLKSRC_11,
> + SRPC_CLKSRC_12,
> + SRPC_CLKSRC_13,
> + SRPC_CLKSRC_14,
> + SRPC_CLKSRC_15,
> +};
> +#define SRPC_CLKSRC_MAX (SRPC_CLKSRC_15 + 1)
> +#define DEFAULT_RXCLK_SRC SRPC_CLKSRC_0
> +
> +enum spdif_gainsel {
> + GAINSEL_MULTI_24 = 0,
> + GAINSEL_MULTI_16,
> + GAINSEL_MULTI_12,
> + GAINSEL_MULTI_8,
> + GAINSEL_MULTI_6,
> + GAINSEL_MULTI_4,
> + GAINSEL_MULTI_3,
> +};
> +#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
> +#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
> +
> +/* SPDIF interrupt mask define */
> +#define INT_DPLL_LOCKED (1 << 20)
> +#define INT_TXFIFO_UNOV (1 << 19)
> +#define INT_TXFIFO_RESYNC (1 << 18)
> +#define INT_CNEW (1 << 17)
> +#define INT_VAL_NOGOOD (1 << 16)
> +#define INT_SYM_ERR (1 << 15)
> +#define INT_BIT_ERR (1 << 14)
> +#define INT_URX_FUL (1 << 10)
> +#define INT_URX_OV (1 << 9)
> +#define INT_QRX_FUL (1 << 8)
> +#define INT_QRX_OV (1 << 7)
> +#define INT_UQ_SYNC (1 << 6)
> +#define INT_UQ_ERR (1 << 5)
> +#define INT_RXFIFO_UNOV (1 << 4)
> +#define INT_RXFIFO_RESYNC (1 << 3)
> +#define INT_LOSS_LOCK (1 << 2)
> +#define INT_TX_EM (1 << 1)
> +#define INT_RXFIFO_FUL (1 << 0)
> +
> +/* SPDIF Clock register */
> +#define STC_SYSCLK_DIV_OFFSET 11
> +#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
> +#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_SYSCLK_DIV_MASK) +#define STC_TXCLK_SRC_OFFSET 8
> +#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
> +#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) &
> STC_TXCLK_SRC_MASK) +#define STC_TXCLK_ALL_EN_OFFSET 7
> +#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
> +#define STC_TXCLK_DIV_OFFSET 0
> +#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
> +#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) &
> STC_TXCLK_DIV_MASK) +
> +/* SPDIF tx clksrc */
> +enum spdif_txclk_src {
> + STC_TXCLK_SRC_0 = 0,
> + STC_TXCLK_SRC_1,
> + STC_TXCLK_SRC_2,
> + STC_TXCLK_SRC_3,
> + STC_TXCLK_SRC_4,
> + STC_TXCLK_SRC_5,
> + STC_TXCLK_SRC_6,
> + STC_TXCLK_SRC_7,
> +};
> +#define STC_TXCLK_SRC_MAX (STC_TXCLK_SRC_7 + 1)
> +#define DEFAULT_TXCLK_SRC STC_TXCLK_SRC_1
> +
> +/* SPDIF tx rate */
> +enum spdif_txrate {
> + SPDIF_TXRATE_32000 = 0,
> + SPDIF_TXRATE_44100,
> + SPDIF_TXRATE_48000,
> +};
> +#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
> +
> +
> +#define SPDIF_CSTATUS_BYTE 6
> +#define SPDIF_UBITS_SIZE 96
> +#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
> +
> +
> +#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000)
> +
> +#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
> + SNDRV_PCM_RATE_32000 | \
> + SNDRV_PCM_RATE_44100 | \
> + SNDRV_PCM_RATE_48000 | \
> + SNDRV_PCM_RATE_64000 | \
> + SNDRV_PCM_RATE_96000)
> +
> +#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
> + SNDRV_PCM_FMTBIT_S20_3LE | \
> + SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
> +
> +#endif /* _FSL_SPDIF_DAI_H */
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-15 12:18 ` Tomasz Figa
(?)
(?)
@ 2013-08-16 4:43 ` Nicolin Chen
2013-08-16 7:08 ` Sascha Hauer
2013-08-17 12:56 ` Tomasz Figa
-1 siblings, 2 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-16 4:43 UTC (permalink / raw)
To: Tomasz Figa
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, s.hauer, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Hi Tomasz,
Thank you for the comments. I'll revise them in v6.
And below is my reply for you comments.
On Thu, Aug 15, 2013 at 02:18:22PM +0200, Tomasz Figa wrote:
> > + - clock-names : Includes the following entries:
> > + name type comments
> > + "core" Required The core clock of spdif controller
> > +
> > + "rx" Optional Rx clock source for spdif record.
> > + If absent, will use core clock.
> > +
> > + "tx" Optional Tx clock source for spdif playback.
> > + If absent, will use core clock.
> > +
> > + "tx-32000" Optional Tx clock source for 32000Hz sample rate
> > + playback. If absent, will use tx clock.
> > +
> > + "tx-44100" Optional Tx clock source for 44100Hz sample rate
> > + playback. If absent, will use tx clock.
> > +
> > + "tx-48000" Optional Tx clock source for 48000Hz sample rate
> > + playback. If absent, will use tx clock.
> > +
> > + "src<0-7>" Optional Clock source list for tx and rx clock
> > + to look up their clock source indexes.
> > + This clock list should be identical to
> > + the list of TxClk_Source bit value of
> > + register SPDIF_STC. If absent or failed
> > + to look up, tx and rx clock would then
> > + ignore the "rx", "tx" "tx-32000",
> > + "tx-44100", "tx-48000" clock phandles
> > + and select the core clock as default
> > + tx and rx clock.
>
> I suspect a little abuse of clocks property here. From the description of
> "core" and "src<0-7>" clocks I assume that the IP can have up to 9 clock
> inputs - core clock and up to 8 extra source clocks. Is it correct?
>
> If yes, this makes the "tx", "rx" and "tx-*" clocks describe
> configuration, not hardware. IMHO it should be up to the driver which
> source clocks to use for tx and rx channels and for each sampling rate.
First, you are right that all the properties you just commented are
software configurations. And I got the point that device tree now
can't allow any software configuration even if the actual hardware
connection will depend on it.
If so, I would like to remove those abused clocks and also drop the
unused clocks in src<0-7>, then just remain those needed clocks src.
I think that can be plausible because there'll be no more clock abuse
and the driver will be able to get the source index from the name
'src<num>'.
And you are right about the 9 clock inputs, just there're not only 9
inputs but also an extra external clock from S/PDIF transmitter via
coaxial cable or optical fiber -- RxCLK. Please check the following
list:
0000 if (DPLL Locked) SPDIF_RxClk else extal
0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
0101 extal_clk
0110 spdif_clk
0111 asrc_clk
1000 spdif_extclk
1001 esai_hckt
1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
1100 mkb_clk
1101 mlb_phy_clk
When (DPLL Locked) condition matches, the rx clock can ignore the 8 input
clocks from clock mux then use the external one from a S/PDIF transmitter.
So for the below part:
> > +Optional properties:
> > +
> > + - rx-clksrc-lock: This is a boolean property. If present, ClkSrc_Sel
> > bit + of SPDIF_SRPC would be set a clock source that cares DPLL locked
> > condition. +
>
> This again looks like software configuration, not hardware description.
> Could you elaborate a bit more on meaning of this property?
I think the rx-clksrc-lock property should be included in DT as well, since
it's exactly a available clock source for rx. But I guess I just need to
figure out a better way or a more elaborated description.
Thank you,
Nicolin Chen
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 4:43 ` Nicolin Chen
@ 2013-08-16 7:08 ` Sascha Hauer
2013-08-16 8:01 ` Nicolin Chen
2013-08-17 12:56 ` Tomasz Figa
1 sibling, 1 reply; 77+ messages in thread
From: Sascha Hauer @ 2013-08-16 7:08 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Fri, Aug 16, 2013 at 12:43:31PM +0800, Nicolin Chen wrote:
> Hi Tomasz,
>
> Thank you for the comments. I'll revise them in v6.
> And below is my reply for you comments.
>
> On Thu, Aug 15, 2013 at 02:18:22PM +0200, Tomasz Figa wrote:
> > > + - clock-names : Includes the following entries:
> > > + name type comments
> > > + "core" Required The core clock of spdif controller
> > > +
> > > + "rx" Optional Rx clock source for spdif record.
> > > + If absent, will use core clock.
> > > +
> > > + "tx" Optional Tx clock source for spdif playback.
> > > + If absent, will use core clock.
> > > +
> > > + "tx-32000" Optional Tx clock source for 32000Hz sample rate
> > > + playback. If absent, will use tx clock.
> > > +
> > > + "tx-44100" Optional Tx clock source for 44100Hz sample rate
> > > + playback. If absent, will use tx clock.
> > > +
> > > + "tx-48000" Optional Tx clock source for 48000Hz sample rate
> > > + playback. If absent, will use tx clock.
> > > +
> > > + "src<0-7>" Optional Clock source list for tx and rx clock
> > > + to look up their clock source indexes.
> > > + This clock list should be identical to
> > > + the list of TxClk_Source bit value of
> > > + register SPDIF_STC. If absent or failed
> > > + to look up, tx and rx clock would then
> > > + ignore the "rx", "tx" "tx-32000",
> > > + "tx-44100", "tx-48000" clock phandles
> > > + and select the core clock as default
> > > + tx and rx clock.
> >
> > I suspect a little abuse of clocks property here. From the description of
> > "core" and "src<0-7>" clocks I assume that the IP can have up to 9 clock
> > inputs - core clock and up to 8 extra source clocks. Is it correct?
> >
> > If yes, this makes the "tx", "rx" and "tx-*" clocks describe
> > configuration, not hardware. IMHO it should be up to the driver which
> > source clocks to use for tx and rx channels and for each sampling rate.
>
> First, you are right that all the properties you just commented are
> software configurations. And I got the point that device tree now
> can't allow any software configuration even if the actual hardware
> connection will depend on it.
>
> If so, I would like to remove those abused clocks and also drop the
> unused clocks in src<0-7>, then just remain those needed clocks src.
> I think that can be plausible because there'll be no more clock abuse
> and the driver will be able to get the source index from the name
> 'src<num>'.
>
> And you are right about the 9 clock inputs, just there're not only 9
> inputs but also an extra external clock from S/PDIF transmitter via
> coaxial cable or optical fiber -- RxCLK. Please check the following
> list:
>
> 0000 if (DPLL Locked) SPDIF_RxClk else extal
> 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> 0101 extal_clk
> 0110 spdif_clk
> 0111 asrc_clk
> 1000 spdif_extclk
> 1001 esai_hckt
> 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> 1100 mkb_clk
> 1101 mlb_phy_clk
>
> When (DPLL Locked) condition matches, the rx clock can ignore the 8 input
> clocks from clock mux then use the external one from a S/PDIF transmitter.
So extal, spdif_clk, asrc_clk, spdif_extclk, esai_hckt, mlb_clk and
mlb_phy_clk are clocks provided to the S/PDIF core and thus should be
described in the devicetree.
Which of them the driver should use is configuration and thus normally
should *not* be described in the devicetree. However, there may be no
good way for the driver to know which clock to use in which case. There
may be additional board requirements which are unknown to the driver. So
in this case it might be valid to put the information which clock to use
into the devicetree. But be aware that from the moment you put this
information into the devicetree the driver is no longer free to chose
the best clock, even if in future we find a good way to automatically
guess the best clock. Do you have some insights in which case I would
use which input clock? Is this only about which clock has the best
suitable input frequency or is this also about synchronization of the
audio signal with some other unit?
Likewise with the rx-clksrc-lock property. what are the reasons to
enable/disable this property? Is this an option you want to change
during runtime? Is it an option you always want to use when it's
available?
If you don't know the answer then it might be a good option to just let
the driver pick a sane default. If someone feels the need to change the
default he probably comes up with a good reason why this is necessary.
And then we can discuss again whether we want to have the option in the
devicetree or some sysfs entry or whatever else.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 7:08 ` Sascha Hauer
@ 2013-08-16 8:01 ` Nicolin Chen
2013-08-16 8:56 ` Sascha Hauer
0 siblings, 1 reply; 77+ messages in thread
From: Nicolin Chen @ 2013-08-16 8:01 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Hi Sascha,
Thank you for the detailed comments.
On Fri, Aug 16, 2013 at 09:08:18AM +0200, Sascha Hauer wrote:
> Which of them the driver should use is configuration and thus normally
> should *not* be described in the devicetree. However, there may be no
> good way for the driver to know which clock to use in which case. There
> may be additional board requirements which are unknown to the driver. So
> in this case it might be valid to put the information which clock to use
> into the devicetree. But be aware that from the moment you put this
> information into the devicetree the driver is no longer free to chose
> the best clock, even if in future we find a good way to automatically
> guess the best clock. Do you have some insights in which case I would
> use which input clock? Is this only about which clock has the best
> suitable input frequency or is this also about synchronization of the
> audio signal with some other unit?
I understand. What I'm thinking now is to let the driver find the best
clock source for tx clock and a correspond divisor like this:
"tx<0-8>" Optional Tx clock source for spdif playback.
If absent, will use core clock.
The index from 0 to 8 is identical
to the clock source list described
in TxClk_Source bit of register STC.
Multiple clock source are allowed
for this tx clock source. The driver
will select one source from them for
each supported sample rate according
to the clock rates of these provided
clock sources.
Please review this idea.
And likewise for rx:
"rx<0-16>" Optional Rx clock source for spdif record.
If absent, will use core clock.
The index from 0 to 16 is identical
to the clock source list described
in ClkSrc_Sel bit of register SRPC.
If the index provided contains an
"if (DPLL Locked)" condition in its
source, the correspond clock phandle
should be the one in "else" path.
Only one rx clock source should be
defined here.
> Likewise with the rx-clksrc-lock property. what are the reasons to
> enable/disable this property? Is this an option you want to change
> during runtime? Is it an option you always want to use when it's
> available?
>
> If you don't know the answer then it might be a good option to just let
> the driver pick a sane default. If someone feels the need to change the
> default he probably comes up with a good reason why this is necessary.
> And then we can discuss again whether we want to have the option in the
> devicetree or some sysfs entry or whatever else.
The answer is, SPDIF controller actually doesn't care about which rx
clock source being chosen or even whether it has the "if (DPLL Locked)"
condition or not. It can measure its input clock sample rate by measuring
the signal source, from a spdif transmitter via coaxial cable or optical
line. However, the rxclk will be sent to other IP, ASRC on i.MX6Q for
example. Quoting from the i.MX6Q reference manual that "Both the Rx clock
and Tx clock are sent to the ASRC".
Therefore, if 'rx-clksrc-lock' is present, that means ASRC will get a
clock source indirectly from coaxial cable that contains the sample rate
information. So it can know what input sample rate is and do his own
procedure accordingly.
Thank you,
Nicolin Chen
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 8:01 ` Nicolin Chen
@ 2013-08-16 8:56 ` Sascha Hauer
2013-08-16 9:53 ` Nicolin Chen
2013-08-17 12:26 ` Tomasz Figa
0 siblings, 2 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-16 8:56 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Fri, Aug 16, 2013 at 04:01:25PM +0800, Nicolin Chen wrote:
> Hi Sascha,
>
> Thank you for the detailed comments.
>
> On Fri, Aug 16, 2013 at 09:08:18AM +0200, Sascha Hauer wrote:
> > Which of them the driver should use is configuration and thus normally
> > should *not* be described in the devicetree. However, there may be no
> > good way for the driver to know which clock to use in which case. There
> > may be additional board requirements which are unknown to the driver. So
> > in this case it might be valid to put the information which clock to use
> > into the devicetree. But be aware that from the moment you put this
> > information into the devicetree the driver is no longer free to chose
> > the best clock, even if in future we find a good way to automatically
> > guess the best clock. Do you have some insights in which case I would
> > use which input clock? Is this only about which clock has the best
> > suitable input frequency or is this also about synchronization of the
> > audio signal with some other unit?
>
> I understand. What I'm thinking now is to let the driver find the best
> clock source for tx clock and a correspond divisor like this:
>
> "tx<0-8>" Optional Tx clock source for spdif playback.
> If absent, will use core clock.
> The index from 0 to 8 is identical
> to the clock source list described
> in TxClk_Source bit of register STC.
> Multiple clock source are allowed
> for this tx clock source. The driver
> will select one source from them for
> each supported sample rate according
> to the clock rates of these provided
> clock sources.
You mean tx<0-7>.
Also I would make this option required. Use a dummy clock for mux inputs
that are grounded for a specific SoC.
>
> Please review this idea.
>
>
> And likewise for rx:
>
> "rx<0-16>" Optional Rx clock source for spdif record.
> If absent, will use core clock.
> The index from 0 to 16 is identical
> to the clock source list described
> in ClkSrc_Sel bit of register SRPC.
> If the index provided contains an
> "if (DPLL Locked)" condition in its
> source, the correspond clock phandle
> should be the one in "else" path.
> Only one rx clock source should be
> defined here.
Again, describe the input clocks *to* *the* *S/PDIF* *core* in the
devicetree. Nothing more, nothing less. We've already been at the point
where we realized that half of the above clocks only describe the
'PDLL locked' condition. Also the tx clocks are from what I see identical
to the rx clocks. The following are the clocks:
clock-names: "core", "rxtx<0-7>" Required. The S/PDIF core has a core
clock and 8 clocks which are muxed internally to provide input/output
sample clocks.
This is all binding that is needed for now.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 8:56 ` Sascha Hauer
@ 2013-08-16 9:53 ` Nicolin Chen
2013-08-16 10:11 ` Sascha Hauer
2013-08-17 12:26 ` Tomasz Figa
1 sibling, 1 reply; 77+ messages in thread
From: Nicolin Chen @ 2013-08-16 9:53 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Fri, Aug 16, 2013 at 10:56:32AM +0200, Sascha Hauer wrote:
> > "tx<0-8>" Optional Tx clock source for spdif playback.
> > If absent, will use core clock.
> > The index from 0 to 8 is identical
> > to the clock source list described
> > in TxClk_Source bit of register STC.
> > Multiple clock source are allowed
> > for this tx clock source. The driver
> > will select one source from them for
> > each supported sample rate according
> > to the clock rates of these provided
> > clock sources.
>
> You mean tx<0-7>
Yes. Thank you.
> Also I would make this option required. Use a dummy clock for mux inputs
> that are grounded for a specific SoC.
Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
so in most cases we can't provide a phandle for them, eg: spdif_ext.
I think it's a bit hard to force it to be 'required'. An 'optional'
looks more flexible to me and a default one is ensured even if it's
missing.
> > "rx<0-16>" Optional Rx clock source for spdif record.
> > If absent, will use core clock.
> > The index from 0 to 16 is identical
> > to the clock source list described
> > in ClkSrc_Sel bit of register SRPC.
> > If the index provided contains an
> > "if (DPLL Locked)" condition in its
> > source, the correspond clock phandle
> > should be the one in "else" path.
> > Only one rx clock source should be
> > defined here.
>
> Again, describe the input clocks *to* *the* *S/PDIF* *core* in the
> devicetree. Nothing more, nothing less. We've already been at the point
> where we realized that half of the above clocks only describe the
> 'PDLL locked' condition. Also the tx clocks are from what I see identical
> to the rx clocks. The following are the clocks:
>
> clock-names: "core", "rxtx<0-7>" Required. The S/PDIF core has a core
> clock and 8 clocks which are muxed internally to provide input/output
> sample clocks.
I know the reason why you suggest to combine two into 'rxtx<0-7>'
is because the clock mux is defined so. And the previous suggestion
'the option required' is also because of it. But actually the rxclk
itself, can be not only routed from the clock mux but also derived
from DPLL of SPDIF Rx BLOCK as well. So, IMHO, it's more likely to
be a fact that rxclk actually has 9 clock source, 8 from mux and
1 from DPLL. But why we here have to exclude it?
WELL anyway, I know my opinion might not be concerned so much. So
I would like to follow the suggestion as an expediency because I
still wish this patch could be finally applied and merged into
mainline :(
But I still don't get why we need to be so obsessed to make this
impenetrable rule of devicetree that we here have to sacrifice
something we could have reasonably done.
And thank you for the comments again, Sascha.
Nicolin Chen
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 9:53 ` Nicolin Chen
@ 2013-08-16 10:11 ` Sascha Hauer
2013-08-16 10:16 ` Nicolin Chen
2013-08-17 12:28 ` Tomasz Figa
0 siblings, 2 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-16 10:11 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Fri, Aug 16, 2013 at 05:53:58PM +0800, Nicolin Chen wrote:
> On Fri, Aug 16, 2013 at 10:56:32AM +0200, Sascha Hauer wrote:
> > > "tx<0-8>" Optional Tx clock source for spdif playback.
> > > If absent, will use core clock.
> > > The index from 0 to 8 is identical
> > > to the clock source list described
> > > in TxClk_Source bit of register STC.
> > > Multiple clock source are allowed
> > > for this tx clock source. The driver
> > > will select one source from them for
> > > each supported sample rate according
> > > to the clock rates of these provided
> > > clock sources.
> >
> > You mean tx<0-7>
>
> Yes. Thank you.
>
> > Also I would make this option required. Use a dummy clock for mux inputs
> > that are grounded for a specific SoC.
>
> Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
> so in most cases we can't provide a phandle for them, eg: spdif_ext.
> I think it's a bit hard to force it to be 'required'. An 'optional'
> looks more flexible to me and a default one is ensured even if it's
> missing.
<&clks 0> is the dummy clock. This can be used for all input clocks not
defined by the SoC.
spdif_ext would be a fixed clock on boards which provide it, but wiring
this up would be the job of the board maintainer.
> > Again, describe the input clocks *to* *the* *S/PDIF* *core* in the
> > devicetree. Nothing more, nothing less. We've already been at the point
> > where we realized that half of the above clocks only describe the
> > 'PDLL locked' condition. Also the tx clocks are from what I see identical
> > to the rx clocks. The following are the clocks:
> >
> > clock-names: "core", "rxtx<0-7>" Required. The S/PDIF core has a core
> > clock and 8 clocks which are muxed internally to provide input/output
> > sample clocks.
>
> I know the reason why you suggest to combine two into 'rxtx<0-7>'
> is because the clock mux is defined so. And the previous suggestion
> 'the option required' is also because of it. But actually the rxclk
> itself, can be not only routed from the clock mux but also derived
> from DPLL of SPDIF Rx BLOCK as well. So, IMHO, it's more likely to
> be a fact that rxclk actually has 9 clock source, 8 from mux and
> 1 from DPLL. But why we here have to exclude it?
Because this is configuration, not hardware description.
>
> WELL anyway, I know my opinion might not be concerned so much. So
> I would like to follow the suggestion as an expediency because I
> still wish this patch could be finally applied and merged into
> mainline :(
>
> But I still don't get why we need to be so obsessed to make this
> impenetrable rule of devicetree that we here have to sacrifice
> something we could have reasonably done.
Look, it's really simple. Define the binding in a way that describes the
hardware. Then use some sensible default in the driver for which clock
to use. This doesn't have to cover all possible usecases, it only has
to work. This is all that is necessary to get this driver mainline and
will make most users happy. Then, later, someone might come along who
needs more fine grained control over the clocks, but this guy is then
able to justify *why* more control is needed.
This is not about getting a full featured driver into mainline. Get
a basic driver into mainline and improve it later. You'll make it
easier for us all.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 10:11 ` Sascha Hauer
@ 2013-08-16 10:16 ` Nicolin Chen
2013-08-17 12:28 ` Tomasz Figa
1 sibling, 0 replies; 77+ messages in thread
From: Nicolin Chen @ 2013-08-16 10:16 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Fri, Aug 16, 2013 at 12:11:51PM +0200, Sascha Hauer wrote:
> > Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
> > so in most cases we can't provide a phandle for them, eg: spdif_ext.
> > I think it's a bit hard to force it to be 'required'. An 'optional'
> > looks more flexible to me and a default one is ensured even if it's
> > missing.
>
> <&clks 0> is the dummy clock. This can be used for all input clocks not
> defined by the SoC.
That's feasible, thank you.
> spdif_ext would be a fixed clock on boards which provide it, but wiring
> this up would be the job of the board maintainer.
Understood.
> Look, it's really simple. Define the binding in a way that describes the
> hardware. Then use some sensible default in the driver for which clock
> to use. This doesn't have to cover all possible usecases, it only has
> to work. This is all that is necessary to get this driver mainline and
> will make most users happy. Then, later, someone might come along who
> needs more fine grained control over the clocks, but this guy is then
> able to justify *why* more control is needed.
>
> This is not about getting a full featured driver into mainline. Get
> a basic driver into mainline and improve it later. You'll make it
> easier for us all.
Thank you for explain all these to the despicable me.
I'll try to make myself more comfortable with rules here.
Best regards,
Nicolin Chen
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 8:56 ` Sascha Hauer
@ 2013-08-17 12:26 ` Tomasz Figa
2013-08-17 12:26 ` Tomasz Figa
1 sibling, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 12:26 UTC (permalink / raw)
To: Sascha Hauer
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Friday 16 of August 2013 10:56:32 Sascha Hauer wrote:
> On Fri, Aug 16, 2013 at 04:01:25PM +0800, Nicolin Chen wrote:
> > Hi Sascha,
> >
> > Thank you for the detailed comments.
> >
> > On Fri, Aug 16, 2013 at 09:08:18AM +0200, Sascha Hauer wrote:
> > > Which of them the driver should use is configuration and thus
> > > normally
> > > should *not* be described in the devicetree. However, there may be
> > > no
> > > good way for the driver to know which clock to use in which case.
> > > There
> > > may be additional board requirements which are unknown to the
> > > driver. So in this case it might be valid to put the information
> > > which clock to use into the devicetree. But be aware that from the
> > > moment you put this information into the devicetree the driver is
> > > no longer free to chose the best clock, even if in future we find a
> > > good way to automatically guess the best clock. Do you have some
> > > insights in which case I would use which input clock? Is this only
> > > about which clock has the best suitable input frequency or is this
> > > also about synchronization of the audio signal with some other
> > > unit?
> >
> > I understand. What I'm thinking now is to let the driver find the best
> > clock source for tx clock and a correspond divisor like this:
> >
> > "tx<0-8>" Optional Tx clock source for spdif playback.
> >
> > If absent, will use core clock.
> > The index from 0 to 8 is identical
> > to the clock source list described
> > in TxClk_Source bit of register STC.
> > Multiple clock source are allowed
> > for this tx clock source. The driver
> > will select one source from them for
> > each supported sample rate according
> > to the clock rates of these provided
> > clock sources.
>
> You mean tx<0-7>.
>
> Also I would make this option required. Use a dummy clock for mux inputs
> that are grounded for a specific SoC.
Why do you need a dummy clock?
The driver can simply try to grab all the possible clocks and discard
those that failed, so you can just keep those grounded clocks unspecified.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 12:26 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 12:26 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Friday 16 of August 2013 10:56:32 Sascha Hauer wrote:
> On Fri, Aug 16, 2013 at 04:01:25PM +0800, Nicolin Chen wrote:
> > Hi Sascha,
> >
> > Thank you for the detailed comments.
> >
> > On Fri, Aug 16, 2013 at 09:08:18AM +0200, Sascha Hauer wrote:
> > > Which of them the driver should use is configuration and thus
> > > normally
> > > should *not* be described in the devicetree. However, there may be
> > > no
> > > good way for the driver to know which clock to use in which case.
> > > There
> > > may be additional board requirements which are unknown to the
> > > driver. So in this case it might be valid to put the information
> > > which clock to use into the devicetree. But be aware that from the
> > > moment you put this information into the devicetree the driver is
> > > no longer free to chose the best clock, even if in future we find a
> > > good way to automatically guess the best clock. Do you have some
> > > insights in which case I would use which input clock? Is this only
> > > about which clock has the best suitable input frequency or is this
> > > also about synchronization of the audio signal with some other
> > > unit?
> >
> > I understand. What I'm thinking now is to let the driver find the best
> > clock source for tx clock and a correspond divisor like this:
> >
> > "tx<0-8>" Optional Tx clock source for spdif playback.
> >
> > If absent, will use core clock.
> > The index from 0 to 8 is identical
> > to the clock source list described
> > in TxClk_Source bit of register STC.
> > Multiple clock source are allowed
> > for this tx clock source. The driver
> > will select one source from them for
> > each supported sample rate according
> > to the clock rates of these provided
> > clock sources.
>
> You mean tx<0-7>.
>
> Also I would make this option required. Use a dummy clock for mux inputs
> that are grounded for a specific SoC.
Why do you need a dummy clock?
The driver can simply try to grab all the possible clocks and discard
those that failed, so you can just keep those grounded clocks unspecified.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 10:11 ` Sascha Hauer
@ 2013-08-17 12:28 ` Tomasz Figa
2013-08-17 12:28 ` Tomasz Figa
1 sibling, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 12:28 UTC (permalink / raw)
To: Sascha Hauer
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Friday 16 of August 2013 12:11:51 Sascha Hauer wrote:
> On Fri, Aug 16, 2013 at 05:53:58PM +0800, Nicolin Chen wrote:
> > On Fri, Aug 16, 2013 at 10:56:32AM +0200, Sascha Hauer wrote:
> > > > "tx<0-8>" Optional Tx clock source for spdif
playback.
> > > >
> > > > If absent, will use core clock.
> > > > The index from 0 to 8 is identical
> > > > to the clock source list described
> > > > in TxClk_Source bit of register
STC.
> > > > Multiple clock source are allowed
> > > > for this tx clock source. The
driver
> > > > will select one source from them
for
> > > > each supported sample rate
according
> > > > to the clock rates of these
provided
> > > > clock sources.
> > >
> > > You mean tx<0-7>
> >
> > Yes. Thank you.
> >
> > > Also I would make this option required. Use a dummy clock for mux
> > > inputs that are grounded for a specific SoC.
> >
> > Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
> > so in most cases we can't provide a phandle for them, eg: spdif_ext.
> > I think it's a bit hard to force it to be 'required'. An 'optional'
> > looks more flexible to me and a default one is ensured even if it's
> > missing.
>
> <&clks 0> is the dummy clock. This can be used for all input clocks not
> defined by the SoC.
Where does this assumption come from? Is it documented anywhere? What
about cases when you have full description of clocks in device tree, with
one node per clock and #clock-cells = <0>?
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 12:28 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 12:28 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Friday 16 of August 2013 12:11:51 Sascha Hauer wrote:
> On Fri, Aug 16, 2013 at 05:53:58PM +0800, Nicolin Chen wrote:
> > On Fri, Aug 16, 2013 at 10:56:32AM +0200, Sascha Hauer wrote:
> > > > "tx<0-8>" Optional Tx clock source for spdif
playback.
> > > >
> > > > If absent, will use core clock.
> > > > The index from 0 to 8 is identical
> > > > to the clock source list described
> > > > in TxClk_Source bit of register
STC.
> > > > Multiple clock source are allowed
> > > > for this tx clock source. The
driver
> > > > will select one source from them
for
> > > > each supported sample rate
according
> > > > to the clock rates of these
provided
> > > > clock sources.
> > >
> > > You mean tx<0-7>
> >
> > Yes. Thank you.
> >
> > > Also I would make this option required. Use a dummy clock for mux
> > > inputs that are grounded for a specific SoC.
> >
> > Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
> > so in most cases we can't provide a phandle for them, eg: spdif_ext.
> > I think it's a bit hard to force it to be 'required'. An 'optional'
> > looks more flexible to me and a default one is ensured even if it's
> > missing.
>
> <&clks 0> is the dummy clock. This can be used for all input clocks not
> defined by the SoC.
Where does this assumption come from? Is it documented anywhere? What
about cases when you have full description of clocks in device tree, with
one node per clock and #clock-cells = <0>?
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-16 4:43 ` Nicolin Chen
@ 2013-08-17 12:56 ` Tomasz Figa
2013-08-17 12:56 ` Tomasz Figa
1 sibling, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 12:56 UTC (permalink / raw)
To: Nicolin Chen
Cc: ian.campbell, pawel.moll, galak, broonie, lars, p.zabel, s.hauer,
linuxppc-dev, alsa-devel, devicetree, timur, rob.herring,
shawn.guo, festevam, swarren, mark.rutland
Hi Nicolin,
On Friday 16 of August 2013 12:43:31 Nicolin Chen wrote:
> Hi Tomasz,
>
> Thank you for the comments.
You're welcome.
> I'll revise them in v6.
> And below is my reply for you comments.
Thanks for your reply.
> On Thu, Aug 15, 2013 at 02:18:22PM +0200, Tomasz Figa wrote:
> > > + - clock-names : Includes the following entries:
> > > + name type comments
> > > + "core" Required The core clock of spdif controller
> > > +
> > > + "rx" Optional Rx clock source for spdif record.
> > > + If absent, will use core clock.
> > > +
> > > + "tx" Optional Tx clock source for spdif
playback.
> > > + If absent, will use core clock.
> > > +
> > > + "tx-32000" Optional Tx clock source for 32000Hz sample
rate
> > > + playback. If absent, will use tx
clock.
> > > +
> > > + "tx-44100" Optional Tx clock source for 44100Hz sample
rate
> > > + playback. If absent, will use tx
clock.
> > > +
> > > + "tx-48000" Optional Tx clock source for 48000Hz sample
rate
> > > + playback. If absent, will use tx
clock.
> > > +
> > > + "src<0-7>" Optional Clock source list for tx and rx
clock
> > > + to look up their clock source
indexes.
> > > + This clock list should be
identical to
> > > + the list of TxClk_Source bit value
of
> > > + register SPDIF_STC. If absent or
failed
> > > + to look up, tx and rx clock would
then
> > > + ignore the "rx", "tx" "tx-32000",
> > > + "tx-44100", "tx-48000" clock
phandles
> > > + and select the core clock as
default
> > > + tx and rx clock.
> >
> > I suspect a little abuse of clocks property here. From the description
> > of "core" and "src<0-7>" clocks I assume that the IP can have up to 9
> > clock inputs - core clock and up to 8 extra source clocks. Is it
> > correct?
> >
> > If yes, this makes the "tx", "rx" and "tx-*" clocks describe
> > configuration, not hardware. IMHO it should be up to the driver which
> > source clocks to use for tx and rx channels and for each sampling
> > rate.
>
> First, you are right that all the properties you just commented are
> software configurations. And I got the point that device tree now
> can't allow any software configuration even if the actual hardware
> connection will depend on it.
>
> If so, I would like to remove those abused clocks and also drop the
> unused clocks in src<0-7>, then just remain those needed clocks src.
> I think that can be plausible because there'll be no more clock abuse
> and the driver will be able to get the source index from the name
> 'src<num>'.
OK.
> And you are right about the 9 clock inputs, just there're not only 9
> inputs but also an extra external clock from S/PDIF transmitter via
> coaxial cable or optical fiber -- RxCLK. Please check the following
> list:
>
> 0000 if (DPLL Locked) SPDIF_RxClk else extal
> 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> 0101 extal_clk
> 0110 spdif_clk
> 0111 asrc_clk
> 1000 spdif_extclk
> 1001 esai_hckt
> 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> 1100 mkb_clk
> 1101 mlb_phy_clk
Could you explain what the above values are? If they are values written to
a 4-bit mux that selects RX clock source, then all the 16 clocks should be
specified from device tree, even if they are duplicated.
Are the clock names you used above names of clock inputs of the S/PDIF
block or names of SoC-wide clocks?
Can the assignment of clock inputs change? For example on one SoC
0000 if (DPLL Locked) SPDIF_RxClk else extal_clk
0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
...
0101 extal_clk
0110 spdif_clk
...
and on another
0000 if (DPLL Locked) SPDIF_RxClk else spdif_clk
0001 if (DPLL Locked) SPDIF_RxClk else extal_clk
...
0101 extal_clk
0110 spdif_clk
...
(notice the swapped 0000 and 0001 inputs)
Same goes for the TX mux. If it is a 3-bit, 8-input mux, then it should be
described in device tree separately, as it is different than the 4-bit,
16-input RX mux.
> When (DPLL Locked) condition matches, the rx clock can ignore the 8
> input clocks from clock mux then use the external one from a S/PDIF
> transmitter.
What happens if the "DPLL locked" condition doesn't match? When this can
happen?
> So for the below part:
> > > +Optional properties:
> > > +
> > > + - rx-clksrc-lock: This is a boolean property. If present,
> > > ClkSrc_Sel
> > > bit + of SPDIF_SRPC would be set a clock source that cares DPLL
> > > locked
> > > condition. +
> >
> > This again looks like software configuration, not hardware
> > description.
> > Could you elaborate a bit more on meaning of this property?
>
> I think the rx-clksrc-lock property should be included in DT as well,
> since it's exactly a available clock source for rx. But I guess I just
> need to figure out a better way or a more elaborated description.
I still don't understand the meaning of this property. Could you explain
it please?
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 12:56 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 12:56 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, s.hauer, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Hi Nicolin,
On Friday 16 of August 2013 12:43:31 Nicolin Chen wrote:
> Hi Tomasz,
>
> Thank you for the comments.
You're welcome.
> I'll revise them in v6.
> And below is my reply for you comments.
Thanks for your reply.
> On Thu, Aug 15, 2013 at 02:18:22PM +0200, Tomasz Figa wrote:
> > > + - clock-names : Includes the following entries:
> > > + name type comments
> > > + "core" Required The core clock of spdif controller
> > > +
> > > + "rx" Optional Rx clock source for spdif record.
> > > + If absent, will use core clock.
> > > +
> > > + "tx" Optional Tx clock source for spdif
playback.
> > > + If absent, will use core clock.
> > > +
> > > + "tx-32000" Optional Tx clock source for 32000Hz sample
rate
> > > + playback. If absent, will use tx
clock.
> > > +
> > > + "tx-44100" Optional Tx clock source for 44100Hz sample
rate
> > > + playback. If absent, will use tx
clock.
> > > +
> > > + "tx-48000" Optional Tx clock source for 48000Hz sample
rate
> > > + playback. If absent, will use tx
clock.
> > > +
> > > + "src<0-7>" Optional Clock source list for tx and rx
clock
> > > + to look up their clock source
indexes.
> > > + This clock list should be
identical to
> > > + the list of TxClk_Source bit value
of
> > > + register SPDIF_STC. If absent or
failed
> > > + to look up, tx and rx clock would
then
> > > + ignore the "rx", "tx" "tx-32000",
> > > + "tx-44100", "tx-48000" clock
phandles
> > > + and select the core clock as
default
> > > + tx and rx clock.
> >
> > I suspect a little abuse of clocks property here. From the description
> > of "core" and "src<0-7>" clocks I assume that the IP can have up to 9
> > clock inputs - core clock and up to 8 extra source clocks. Is it
> > correct?
> >
> > If yes, this makes the "tx", "rx" and "tx-*" clocks describe
> > configuration, not hardware. IMHO it should be up to the driver which
> > source clocks to use for tx and rx channels and for each sampling
> > rate.
>
> First, you are right that all the properties you just commented are
> software configurations. And I got the point that device tree now
> can't allow any software configuration even if the actual hardware
> connection will depend on it.
>
> If so, I would like to remove those abused clocks and also drop the
> unused clocks in src<0-7>, then just remain those needed clocks src.
> I think that can be plausible because there'll be no more clock abuse
> and the driver will be able to get the source index from the name
> 'src<num>'.
OK.
> And you are right about the 9 clock inputs, just there're not only 9
> inputs but also an extra external clock from S/PDIF transmitter via
> coaxial cable or optical fiber -- RxCLK. Please check the following
> list:
>
> 0000 if (DPLL Locked) SPDIF_RxClk else extal
> 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> 0101 extal_clk
> 0110 spdif_clk
> 0111 asrc_clk
> 1000 spdif_extclk
> 1001 esai_hckt
> 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> 1100 mkb_clk
> 1101 mlb_phy_clk
Could you explain what the above values are? If they are values written to
a 4-bit mux that selects RX clock source, then all the 16 clocks should be
specified from device tree, even if they are duplicated.
Are the clock names you used above names of clock inputs of the S/PDIF
block or names of SoC-wide clocks?
Can the assignment of clock inputs change? For example on one SoC
0000 if (DPLL Locked) SPDIF_RxClk else extal_clk
0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
...
0101 extal_clk
0110 spdif_clk
...
and on another
0000 if (DPLL Locked) SPDIF_RxClk else spdif_clk
0001 if (DPLL Locked) SPDIF_RxClk else extal_clk
...
0101 extal_clk
0110 spdif_clk
...
(notice the swapped 0000 and 0001 inputs)
Same goes for the TX mux. If it is a 3-bit, 8-input mux, then it should be
described in device tree separately, as it is different than the 4-bit,
16-input RX mux.
> When (DPLL Locked) condition matches, the rx clock can ignore the 8
> input clocks from clock mux then use the external one from a S/PDIF
> transmitter.
What happens if the "DPLL locked" condition doesn't match? When this can
happen?
> So for the below part:
> > > +Optional properties:
> > > +
> > > + - rx-clksrc-lock: This is a boolean property. If present,
> > > ClkSrc_Sel
> > > bit + of SPDIF_SRPC would be set a clock source that cares DPLL
> > > locked
> > > condition. +
> >
> > This again looks like software configuration, not hardware
> > description.
> > Could you elaborate a bit more on meaning of this property?
>
> I think the rx-clksrc-lock property should be included in DT as well,
> since it's exactly a available clock source for rx. But I guess I just
> need to figure out a better way or a more elaborated description.
I still don't understand the meaning of this property. Could you explain
it please?
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 12:28 ` Tomasz Figa
@ 2013-08-17 14:53 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 14:53 UTC (permalink / raw)
To: Tomasz Figa
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > Also I would make this option required. Use a dummy clock for mux
> > > > inputs that are grounded for a specific SoC.
> > >
> > > Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
> > > so in most cases we can't provide a phandle for them, eg: spdif_ext.
> > > I think it's a bit hard to force it to be 'required'. An 'optional'
> > > looks more flexible to me and a default one is ensured even if it's
> > > missing.
> >
> > <&clks 0> is the dummy clock. This can be used for all input clocks not
> > defined by the SoC.
>
> Where does this assumption come from? Is it documented anywhere?
This is how all i.MX clock bindings currently are. See
Documentation/devicetree/bindings/clock/imx*-clock.txt
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 14:53 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 14:53 UTC (permalink / raw)
To: Tomasz Figa
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > Also I would make this option required. Use a dummy clock for mux
> > > > inputs that are grounded for a specific SoC.
> > >
> > > Some clocks are not from CCM and we haven't defined in imx6q-clk.txt,
> > > so in most cases we can't provide a phandle for them, eg: spdif_ext.
> > > I think it's a bit hard to force it to be 'required'. An 'optional'
> > > looks more flexible to me and a default one is ensured even if it's
> > > missing.
> >
> > <&clks 0> is the dummy clock. This can be used for all input clocks not
> > defined by the SoC.
>
> Where does this assumption come from? Is it documented anywhere?
This is how all i.MX clock bindings currently are. See
Documentation/devicetree/bindings/clock/imx*-clock.txt
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 12:26 ` Tomasz Figa
@ 2013-08-17 15:00 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 15:00 UTC (permalink / raw)
To: Tomasz Figa
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Sat, Aug 17, 2013 at 02:26:40PM +0200, Tomasz Figa wrote:
> > You mean tx<0-7>.
> >
> > Also I would make this option required. Use a dummy clock for mux inputs
> > that are grounded for a specific SoC.
>
> Why do you need a dummy clock?
>
> The driver can simply try to grab all the possible clocks and discard
> those that failed, so you can just keep those grounded clocks unspecified.
We don't need dummy clocks. My motivation saying this that I was afraid
people try to configure the driver by skipping the clocks they don't
want from the devicetree.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 15:00 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 15:00 UTC (permalink / raw)
To: Tomasz Figa
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Sat, Aug 17, 2013 at 02:26:40PM +0200, Tomasz Figa wrote:
> > You mean tx<0-7>.
> >
> > Also I would make this option required. Use a dummy clock for mux inputs
> > that are grounded for a specific SoC.
>
> Why do you need a dummy clock?
>
> The driver can simply try to grab all the possible clocks and discard
> those that failed, so you can just keep those grounded clocks unspecified.
We don't need dummy clocks. My motivation saying this that I was afraid
people try to configure the driver by skipping the clocks they don't
want from the devicetree.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 15:00 ` Sascha Hauer
@ 2013-08-17 15:13 ` Tomasz Figa
-1 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 15:13 UTC (permalink / raw)
To: Sascha Hauer
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Saturday 17 of August 2013 17:00:02 Sascha Hauer wrote:
> On Sat, Aug 17, 2013 at 02:26:40PM +0200, Tomasz Figa wrote:
> > > You mean tx<0-7>.
> > >
> > > Also I would make this option required. Use a dummy clock for mux
> > > inputs that are grounded for a specific SoC.
> >
> > Why do you need a dummy clock?
> >
> > The driver can simply try to grab all the possible clocks and discard
> > those that failed, so you can just keep those grounded clocks
> > unspecified.
> We don't need dummy clocks. My motivation saying this that I was afraid
> people try to configure the driver by skipping the clocks they don't
> want from the devicetree.
I'm not really sure if the same abuse couldn't be easily achieved by
putting dummy clocks in place of those skipped clocks.
Adding a note in binding documentation that says that all clocks that are
fed to the IP shall be specified should be fine IMHO.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 15:13 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 15:13 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Saturday 17 of August 2013 17:00:02 Sascha Hauer wrote:
> On Sat, Aug 17, 2013 at 02:26:40PM +0200, Tomasz Figa wrote:
> > > You mean tx<0-7>.
> > >
> > > Also I would make this option required. Use a dummy clock for mux
> > > inputs that are grounded for a specific SoC.
> >
> > Why do you need a dummy clock?
> >
> > The driver can simply try to grab all the possible clocks and discard
> > those that failed, so you can just keep those grounded clocks
> > unspecified.
> We don't need dummy clocks. My motivation saying this that I was afraid
> people try to configure the driver by skipping the clocks they don't
> want from the devicetree.
I'm not really sure if the same abuse couldn't be easily achieved by
putting dummy clocks in place of those skipped clocks.
Adding a note in binding documentation that says that all clocks that are
fed to the IP shall be specified should be fine IMHO.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 12:56 ` Tomasz Figa
@ 2013-08-17 15:14 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 15:14 UTC (permalink / raw)
To: Tomasz Figa
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Sat, Aug 17, 2013 at 02:56:11PM +0200, Tomasz Figa wrote:
> Hi Nicolin,
> > First, you are right that all the properties you just commented are
> > software configurations. And I got the point that device tree now
> > can't allow any software configuration even if the actual hardware
> > connection will depend on it.
> >
> > If so, I would like to remove those abused clocks and also drop the
> > unused clocks in src<0-7>, then just remain those needed clocks src.
> > I think that can be plausible because there'll be no more clock abuse
> > and the driver will be able to get the source index from the name
> > 'src<num>'.
>
> OK.
>
> > And you are right about the 9 clock inputs, just there're not only 9
> > inputs but also an extra external clock from S/PDIF transmitter via
> > coaxial cable or optical fiber -- RxCLK. Please check the following
> > list:
> >
> > 0000 if (DPLL Locked) SPDIF_RxClk else extal
> > 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> > 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> > 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> > 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> > 0101 extal_clk
> > 0110 spdif_clk
> > 0111 asrc_clk
> > 1000 spdif_extclk
> > 1001 esai_hckt
> > 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> > 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> > 1100 mkb_clk
> > 1101 mlb_phy_clk
>
> Could you explain what the above values are? If they are values written to
> a 4-bit mux that selects RX clock source, then all the 16 clocks should be
> specified from device tree, even if they are duplicated.
The S/PDIF core can recover the clock for the tx signal from the rx
signal. So if you have an S/PDIF input signal, then the DPLL will be
locked and the SPDIF_RxClk can be used for tx. So the above are really 8
clocks and one "If DPLL locked, use it" bit.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 15:14 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 15:14 UTC (permalink / raw)
To: Tomasz Figa
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Sat, Aug 17, 2013 at 02:56:11PM +0200, Tomasz Figa wrote:
> Hi Nicolin,
> > First, you are right that all the properties you just commented are
> > software configurations. And I got the point that device tree now
> > can't allow any software configuration even if the actual hardware
> > connection will depend on it.
> >
> > If so, I would like to remove those abused clocks and also drop the
> > unused clocks in src<0-7>, then just remain those needed clocks src.
> > I think that can be plausible because there'll be no more clock abuse
> > and the driver will be able to get the source index from the name
> > 'src<num>'.
>
> OK.
>
> > And you are right about the 9 clock inputs, just there're not only 9
> > inputs but also an extra external clock from S/PDIF transmitter via
> > coaxial cable or optical fiber -- RxCLK. Please check the following
> > list:
> >
> > 0000 if (DPLL Locked) SPDIF_RxClk else extal
> > 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> > 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> > 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> > 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> > 0101 extal_clk
> > 0110 spdif_clk
> > 0111 asrc_clk
> > 1000 spdif_extclk
> > 1001 esai_hckt
> > 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> > 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> > 1100 mkb_clk
> > 1101 mlb_phy_clk
>
> Could you explain what the above values are? If they are values written to
> a 4-bit mux that selects RX clock source, then all the 16 clocks should be
> specified from device tree, even if they are duplicated.
The S/PDIF core can recover the clock for the tx signal from the rx
signal. So if you have an S/PDIF input signal, then the DPLL will be
locked and the SPDIF_RxClk can be used for tx. So the above are really 8
clocks and one "If DPLL locked, use it" bit.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 15:13 ` Tomasz Figa
@ 2013-08-17 15:14 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 15:14 UTC (permalink / raw)
To: Tomasz Figa
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Sat, Aug 17, 2013 at 05:13:20PM +0200, Tomasz Figa wrote:
> On Saturday 17 of August 2013 17:00:02 Sascha Hauer wrote:
> > On Sat, Aug 17, 2013 at 02:26:40PM +0200, Tomasz Figa wrote:
> > > > You mean tx<0-7>.
> > > >
> > > > Also I would make this option required. Use a dummy clock for mux
> > > > inputs that are grounded for a specific SoC.
> > >
> > > Why do you need a dummy clock?
> > >
> > > The driver can simply try to grab all the possible clocks and discard
> > > those that failed, so you can just keep those grounded clocks
> > > unspecified.
> > We don't need dummy clocks. My motivation saying this that I was afraid
> > people try to configure the driver by skipping the clocks they don't
> > want from the devicetree.
>
> I'm not really sure if the same abuse couldn't be easily achieved by
> putting dummy clocks in place of those skipped clocks.
That's right, yes.
>
> Adding a note in binding documentation that says that all clocks that are
> fed to the IP shall be specified should be fine IMHO.
ok.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 15:14 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-17 15:14 UTC (permalink / raw)
To: Tomasz Figa
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Sat, Aug 17, 2013 at 05:13:20PM +0200, Tomasz Figa wrote:
> On Saturday 17 of August 2013 17:00:02 Sascha Hauer wrote:
> > On Sat, Aug 17, 2013 at 02:26:40PM +0200, Tomasz Figa wrote:
> > > > You mean tx<0-7>.
> > > >
> > > > Also I would make this option required. Use a dummy clock for mux
> > > > inputs that are grounded for a specific SoC.
> > >
> > > Why do you need a dummy clock?
> > >
> > > The driver can simply try to grab all the possible clocks and discard
> > > those that failed, so you can just keep those grounded clocks
> > > unspecified.
> > We don't need dummy clocks. My motivation saying this that I was afraid
> > people try to configure the driver by skipping the clocks they don't
> > want from the devicetree.
>
> I'm not really sure if the same abuse couldn't be easily achieved by
> putting dummy clocks in place of those skipped clocks.
That's right, yes.
>
> Adding a note in binding documentation that says that all clocks that are
> fed to the IP shall be specified should be fine IMHO.
ok.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 14:53 ` Sascha Hauer
@ 2013-08-17 15:17 ` Tomasz Figa
-1 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 15:17 UTC (permalink / raw)
To: Sascha Hauer
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland,
mturquette
On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > Also I would make this option required. Use a dummy clock for
> > > > > mux
> > > > > inputs that are grounded for a specific SoC.
> > > >
> > > > Some clocks are not from CCM and we haven't defined in
> > > > imx6q-clk.txt,
> > > > so in most cases we can't provide a phandle for them, eg:
> > > > spdif_ext.
> > > > I think it's a bit hard to force it to be 'required'. An
> > > > 'optional'
> > > > looks more flexible to me and a default one is ensured even if
> > > > it's
> > > > missing.
> > >
> > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > not
> > > defined by the SoC.
> >
> > Where does this assumption come from? Is it documented anywhere?
>
> This is how all i.MX clock bindings currently are. See
> Documentation/devicetree/bindings/clock/imx*-clock.txt
OK, thanks.
I guess we need some discussion on dummy clocks vs skipped clocks. I think
we want some consistency on this, don't we?
If we really need a dummy clock, then we might also want a generic way to
specify it.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 15:17 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 15:17 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, mturquette,
ian.campbell, pawel.moll, swarren, festevam, Nicolin Chen, timur,
rob.herring, broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > Also I would make this option required. Use a dummy clock for
> > > > > mux
> > > > > inputs that are grounded for a specific SoC.
> > > >
> > > > Some clocks are not from CCM and we haven't defined in
> > > > imx6q-clk.txt,
> > > > so in most cases we can't provide a phandle for them, eg:
> > > > spdif_ext.
> > > > I think it's a bit hard to force it to be 'required'. An
> > > > 'optional'
> > > > looks more flexible to me and a default one is ensured even if
> > > > it's
> > > > missing.
> > >
> > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > not
> > > defined by the SoC.
> >
> > Where does this assumption come from? Is it documented anywhere?
>
> This is how all i.MX clock bindings currently are. See
> Documentation/devicetree/bindings/clock/imx*-clock.txt
OK, thanks.
I guess we need some discussion on dummy clocks vs skipped clocks. I think
we want some consistency on this, don't we?
If we really need a dummy clock, then we might also want a generic way to
specify it.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 15:14 ` Sascha Hauer
@ 2013-08-17 15:38 ` Tomasz Figa
-1 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 15:38 UTC (permalink / raw)
To: Sascha Hauer
Cc: Nicolin Chen, ian.campbell, pawel.moll, galak, broonie, lars,
p.zabel, linuxppc-dev, alsa-devel, devicetree, timur,
rob.herring, shawn.guo, festevam, swarren, mark.rutland
On Saturday 17 of August 2013 17:14:09 Sascha Hauer wrote:
> On Sat, Aug 17, 2013 at 02:56:11PM +0200, Tomasz Figa wrote:
> > Hi Nicolin,
> >
> > > First, you are right that all the properties you just commented are
> > > software configurations. And I got the point that device tree now
> > > can't allow any software configuration even if the actual hardware
> > > connection will depend on it.
> > >
> > > If so, I would like to remove those abused clocks and also drop the
> > > unused clocks in src<0-7>, then just remain those needed clocks src.
> > > I think that can be plausible because there'll be no more clock
> > > abuse
> > > and the driver will be able to get the source index from the name
> > > 'src<num>'.
> >
> > OK.
> >
> > > And you are right about the 9 clock inputs, just there're not only 9
> > > inputs but also an extra external clock from S/PDIF transmitter via
> > > coaxial cable or optical fiber -- RxCLK. Please check the following
> > > list:
> > >
> > > 0000 if (DPLL Locked) SPDIF_RxClk else extal
> > > 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> > > 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> > > 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> > > 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> > > 0101 extal_clk
> > > 0110 spdif_clk
> > > 0111 asrc_clk
> > > 1000 spdif_extclk
> > > 1001 esai_hckt
> > > 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> > > 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> > > 1100 mkb_clk
> > > 1101 mlb_phy_clk
> >
> > Could you explain what the above values are? If they are values
> > written to a 4-bit mux that selects RX clock source, then all the 16
> > clocks should be specified from device tree, even if they are
> > duplicated.
>
> The S/PDIF core can recover the clock for the tx signal from the rx
> signal. So if you have an S/PDIF input signal, then the DPLL will be
> locked and the SPDIF_RxClk can be used for tx. So the above are really 8
> clocks and one "If DPLL locked, use it" bit.
Yes, I'm aware of this and the solution you proposed is fully acceptable,
but it complicates the driver a bit.
If you look at the mux inputs above, you can see that there is no single
bit that specifies "if DPLL locked, use it" mode. Instead the conditional
clock sources are mixed with fixed clock sources, without a linear
translation to 0-7 range, which would have to be hardcoded in the driver.
I guess it's a matter of preference, but if the IP has a RX clock
selection mux that has 16 inputs, the natural representation in device
tree that comes to my mind is 16 clocks - one for each input of the mux.
One might choose to abstract this as 8 clocks, though, since each clock is
duplicated.
In this particular case, the driver would have to know which mux inputs
can use DPLL anyway, so some hardcoding in the driver is still going to
take place, so I guess both solutions are equally right.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-17 15:38 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-17 15:38 UTC (permalink / raw)
To: Sascha Hauer
Cc: mark.rutland, devicetree, alsa-devel, lars, ian.campbell,
pawel.moll, swarren, festevam, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Saturday 17 of August 2013 17:14:09 Sascha Hauer wrote:
> On Sat, Aug 17, 2013 at 02:56:11PM +0200, Tomasz Figa wrote:
> > Hi Nicolin,
> >
> > > First, you are right that all the properties you just commented are
> > > software configurations. And I got the point that device tree now
> > > can't allow any software configuration even if the actual hardware
> > > connection will depend on it.
> > >
> > > If so, I would like to remove those abused clocks and also drop the
> > > unused clocks in src<0-7>, then just remain those needed clocks src.
> > > I think that can be plausible because there'll be no more clock
> > > abuse
> > > and the driver will be able to get the source index from the name
> > > 'src<num>'.
> >
> > OK.
> >
> > > And you are right about the 9 clock inputs, just there're not only 9
> > > inputs but also an extra external clock from S/PDIF transmitter via
> > > coaxial cable or optical fiber -- RxCLK. Please check the following
> > > list:
> > >
> > > 0000 if (DPLL Locked) SPDIF_RxClk else extal
> > > 0001 if (DPLL Locked) SPDIF_RxClk else spdif_clk
> > > 0010 if (DPLL Locked) SPDIF_RxClk else asrc_clk
> > > 0011 if (DPLL Locked) SPDIF_RxClk else spdif_extclk
> > > 0100 if (DPLL Locked) SPDIF_Rxclk else esai_hckt
> > > 0101 extal_clk
> > > 0110 spdif_clk
> > > 0111 asrc_clk
> > > 1000 spdif_extclk
> > > 1001 esai_hckt
> > > 1010 if (DPLL Locked) SPDIF_RxClk else mlb_clk
> > > 1011 if (DPLL Locked) SPDIF_RxClk else mlb_phy_clk
> > > 1100 mkb_clk
> > > 1101 mlb_phy_clk
> >
> > Could you explain what the above values are? If they are values
> > written to a 4-bit mux that selects RX clock source, then all the 16
> > clocks should be specified from device tree, even if they are
> > duplicated.
>
> The S/PDIF core can recover the clock for the tx signal from the rx
> signal. So if you have an S/PDIF input signal, then the DPLL will be
> locked and the SPDIF_RxClk can be used for tx. So the above are really 8
> clocks and one "If DPLL locked, use it" bit.
Yes, I'm aware of this and the solution you proposed is fully acceptable,
but it complicates the driver a bit.
If you look at the mux inputs above, you can see that there is no single
bit that specifies "if DPLL locked, use it" mode. Instead the conditional
clock sources are mixed with fixed clock sources, without a linear
translation to 0-7 range, which would have to be hardcoded in the driver.
I guess it's a matter of preference, but if the IP has a RX clock
selection mux that has 16 inputs, the natural representation in device
tree that comes to my mind is 16 clocks - one for each input of the mux.
One might choose to abstract this as 8 clocks, though, since each clock is
duplicated.
In this particular case, the driver would have to know which mux inputs
can use DPLL anyway, so some hardcoding in the driver is still going to
take place, so I guess both solutions are equally right.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-17 15:17 ` Tomasz Figa
@ 2013-08-19 9:35 ` Mark Rutland
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-19 9:35 UTC (permalink / raw)
To: Tomasz Figa
Cc: Sascha Hauer, Nicolin Chen, ian.campbell, Pawel Moll, galak,
broonie, lars, p.zabel, linuxppc-dev, alsa-devel, devicetree,
timur, rob.herring, shawn.guo, festevam, swarren, mturquette
On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > mux
> > > > > > inputs that are grounded for a specific SoC.
> > > > >
> > > > > Some clocks are not from CCM and we haven't defined in
> > > > > imx6q-clk.txt,
> > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > spdif_ext.
> > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > 'optional'
> > > > > looks more flexible to me and a default one is ensured even if
> > > > > it's
> > > > > missing.
> > > >
> > > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > > not
> > > > defined by the SoC.
> > >
> > > Where does this assumption come from? Is it documented anywhere?
> >
> > This is how all i.MX clock bindings currently are. See
> > Documentation/devicetree/bindings/clock/imx*-clock.txt
>
> OK, thanks.
>
> I guess we need some discussion on dummy clocks vs skipped clocks. I think
> we want some consistency on this, don't we?
>
> If we really need a dummy clock, then we might also want a generic way to
> specify it.
What do we actually mean by a "dummy clock"? We already have bindings
for "fixed-clock" and co friends describe relatively simple
preconfigured clocks.
If a clock isn't actually wired, we shouldn't describe it at all, or
we're describing what Linux wants to think rather than what the hardware
actually is. That can easily be handled with clock-names.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-19 9:35 ` Mark Rutland
0 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-19 9:35 UTC (permalink / raw)
To: Tomasz Figa
Cc: devicetree, alsa-devel, lars, mturquette, ian.campbell,
Pawel Moll, swarren, festevam, Sascha Hauer, Nicolin Chen, timur,
rob.herring, broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > mux
> > > > > > inputs that are grounded for a specific SoC.
> > > > >
> > > > > Some clocks are not from CCM and we haven't defined in
> > > > > imx6q-clk.txt,
> > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > spdif_ext.
> > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > 'optional'
> > > > > looks more flexible to me and a default one is ensured even if
> > > > > it's
> > > > > missing.
> > > >
> > > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > > not
> > > > defined by the SoC.
> > >
> > > Where does this assumption come from? Is it documented anywhere?
> >
> > This is how all i.MX clock bindings currently are. See
> > Documentation/devicetree/bindings/clock/imx*-clock.txt
>
> OK, thanks.
>
> I guess we need some discussion on dummy clocks vs skipped clocks. I think
> we want some consistency on this, don't we?
>
> If we really need a dummy clock, then we might also want a generic way to
> specify it.
What do we actually mean by a "dummy clock"? We already have bindings
for "fixed-clock" and co friends describe relatively simple
preconfigured clocks.
If a clock isn't actually wired, we shouldn't describe it at all, or
we're describing what Linux wants to think rather than what the hardware
actually is. That can easily be handled with clock-names.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-19 9:35 ` Mark Rutland
(?)
@ 2013-08-20 0:06 ` Mike Turquette
-1 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-20 0:06 UTC (permalink / raw)
To: Mark Rutland, Tomasz Figa
Cc: Sascha Hauer, Nicolin Chen, ian.campbell, Pawel Moll, galak,
broonie, lars, p.zabel, linuxppc-dev, alsa-devel, devicetree,
timur, rob.herring, shawn.guo, festevam, swarren
Quoting Mark Rutland (2013-08-19 02:35:43)
> On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > > mux
> > > > > > > inputs that are grounded for a specific SoC.
> > > > > >
> > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > imx6q-clk.txt,
> > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > spdif_ext.
> > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > 'optional'
> > > > > > looks more flexible to me and a default one is ensured even if
> > > > > > it's
> > > > > > missing.
> > > > >
> > > > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > > > not
> > > > > defined by the SoC.
> > > >
> > > > Where does this assumption come from? Is it documented anywhere?
> > >
> > > This is how all i.MX clock bindings currently are. See
> > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> >
> > OK, thanks.
> >
> > I guess we need some discussion on dummy clocks vs skipped clocks. I think
> > we want some consistency on this, don't we?
> >
> > If we really need a dummy clock, then we might also want a generic way to
> > specify it.
>
> What do we actually mean by a "dummy clock"? We already have bindings
> for "fixed-clock" and co friends describe relatively simple
> preconfigured clocks.
Some platforms have a fake clock which defines noops callbacks and
basically doesn't do anything. This is analogous to the dummy regulator
implementation. A central one could be registered by the clock core, as
is done by the regulator core.
I'll add this to the todo list.
Regards,
Mike
>
> If a clock isn't actually wired, we shouldn't describe it at all, or
> we're describing what Linux wants to think rather than what the hardware
> actually is. That can easily be handled with clock-names.
>
> Thanks,
> Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-20 0:06 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-20 0:06 UTC (permalink / raw)
To: Mark Rutland, Tomasz Figa
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Sascha Hauer, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Mark Rutland (2013-08-19 02:35:43)
> On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > > mux
> > > > > > > inputs that are grounded for a specific SoC.
> > > > > >
> > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > imx6q-clk.txt,
> > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > spdif_ext.
> > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > 'optional'
> > > > > > looks more flexible to me and a default one is ensured even if
> > > > > > it's
> > > > > > missing.
> > > > >
> > > > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > > > not
> > > > > defined by the SoC.
> > > >
> > > > Where does this assumption come from? Is it documented anywhere?
> > >
> > > This is how all i.MX clock bindings currently are. See
> > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> >
> > OK, thanks.
> >
> > I guess we need some discussion on dummy clocks vs skipped clocks. I think
> > we want some consistency on this, don't we?
> >
> > If we really need a dummy clock, then we might also want a generic way to
> > specify it.
>
> What do we actually mean by a "dummy clock"? We already have bindings
> for "fixed-clock" and co friends describe relatively simple
> preconfigured clocks.
Some platforms have a fake clock which defines noops callbacks and
basically doesn't do anything. This is analogous to the dummy regulator
implementation. A central one could be registered by the clock core, as
is done by the regulator core.
I'll add this to the todo list.
Regards,
Mike
>
> If a clock isn't actually wired, we shouldn't describe it at all, or
> we're describing what Linux wants to think rather than what the hardware
> actually is. That can easily be handled with clock-names.
>
> Thanks,
> Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-20 0:06 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-20 0:06 UTC (permalink / raw)
To: Mark Rutland, Tomasz Figa
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Sascha Hauer, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Mark Rutland (2013-08-19 02:35:43)
> On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > > mux
> > > > > > > inputs that are grounded for a specific SoC.
> > > > > > =
> > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > imx6q-clk.txt,
> > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > spdif_ext.
> > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > 'optional'
> > > > > > looks more flexible to me and a default one is ensured even if
> > > > > > it's
> > > > > > missing.
> > > > > =
> > > > > <&clks 0> is the dummy clock. This can be used for all input cloc=
ks
> > > > > not
> > > > > defined by the SoC.
> > > > =
> > > > Where does this assumption come from? Is it documented anywhere?
> > > =
> > > This is how all i.MX clock bindings currently are. See
> > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > =
> > OK, thanks.
> > =
> > I guess we need some discussion on dummy clocks vs skipped clocks. I th=
ink =
> > we want some consistency on this, don't we?
> > =
> > If we really need a dummy clock, then we might also want a generic way =
to =
> > specify it.
> =
> What do we actually mean by a "dummy clock"? We already have bindings
> for "fixed-clock" and co friends describe relatively simple
> preconfigured clocks.
Some platforms have a fake clock which defines noops callbacks and
basically doesn't do anything. This is analogous to the dummy regulator
implementation. A central one could be registered by the clock core, as
is done by the regulator core.
I'll add this to the todo list.
Regards,
Mike
> =
> If a clock isn't actually wired, we shouldn't describe it at all, or
> we're describing what Linux wants to think rather than what the hardware
> actually is. That can easily be handled with clock-names.
> =
> Thanks,
> Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-20 0:06 ` Mike Turquette
@ 2013-08-21 8:50 ` Mark Rutland
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-21 8:50 UTC (permalink / raw)
To: Mike Turquette
Cc: Tomasz Figa, Sascha Hauer, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> Quoting Mark Rutland (2013-08-19 02:35:43)
> > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > > > mux
> > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > >
> > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > imx6q-clk.txt,
> > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > spdif_ext.
> > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > 'optional'
> > > > > > > looks more flexible to me and a default one is ensured even if
> > > > > > > it's
> > > > > > > missing.
> > > > > >
> > > > > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > > > > not
> > > > > > defined by the SoC.
> > > > >
> > > > > Where does this assumption come from? Is it documented anywhere?
> > > >
> > > > This is how all i.MX clock bindings currently are. See
> > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > >
> > > OK, thanks.
> > >
> > > I guess we need some discussion on dummy clocks vs skipped clocks. I think
> > > we want some consistency on this, don't we?
> > >
> > > If we really need a dummy clock, then we might also want a generic way to
> > > specify it.
> >
> > What do we actually mean by a "dummy clock"? We already have bindings
> > for "fixed-clock" and co friends describe relatively simple
> > preconfigured clocks.
>
> Some platforms have a fake clock which defines noops callbacks and
> basically doesn't do anything. This is analogous to the dummy regulator
> implementation. A central one could be registered by the clock core, as
> is done by the regulator core.
When you say some platforms, you presumably mean the platform code in
Linux? A dummy clock sounds like a completely Linux-specific abstraction
rather than a description of the hardware, and I don't see why we need
that in the DT:
* If a clock is wired up and running (as presumably the dummy clock is),
then surely it's a fixed-clock (it's running, we and we have no
control over it, but we presumably know its rate) and can be described
as such?
* If no clock is wired up, then we should be able to describe that. If a
driver believes that a clock is required when it isn't (for some level
of functionality), then that driver should be fixed up to support the
clock as being optional.
Am I missing something?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-21 8:50 ` Mark Rutland
0 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-21 8:50 UTC (permalink / raw)
To: Mike Turquette
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Sascha Hauer, Nicolin Chen, Tomasz Figa, rob.herring,
timur, broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> Quoting Mark Rutland (2013-08-19 02:35:43)
> > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > Also I would make this option required. Use a dummy clock for
> > > > > > > > mux
> > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > >
> > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > imx6q-clk.txt,
> > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > spdif_ext.
> > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > 'optional'
> > > > > > > looks more flexible to me and a default one is ensured even if
> > > > > > > it's
> > > > > > > missing.
> > > > > >
> > > > > > <&clks 0> is the dummy clock. This can be used for all input clocks
> > > > > > not
> > > > > > defined by the SoC.
> > > > >
> > > > > Where does this assumption come from? Is it documented anywhere?
> > > >
> > > > This is how all i.MX clock bindings currently are. See
> > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > >
> > > OK, thanks.
> > >
> > > I guess we need some discussion on dummy clocks vs skipped clocks. I think
> > > we want some consistency on this, don't we?
> > >
> > > If we really need a dummy clock, then we might also want a generic way to
> > > specify it.
> >
> > What do we actually mean by a "dummy clock"? We already have bindings
> > for "fixed-clock" and co friends describe relatively simple
> > preconfigured clocks.
>
> Some platforms have a fake clock which defines noops callbacks and
> basically doesn't do anything. This is analogous to the dummy regulator
> implementation. A central one could be registered by the clock core, as
> is done by the regulator core.
When you say some platforms, you presumably mean the platform code in
Linux? A dummy clock sounds like a completely Linux-specific abstraction
rather than a description of the hardware, and I don't see why we need
that in the DT:
* If a clock is wired up and running (as presumably the dummy clock is),
then surely it's a fixed-clock (it's running, we and we have no
control over it, but we presumably know its rate) and can be described
as such?
* If no clock is wired up, then we should be able to describe that. If a
driver believes that a clock is required when it isn't (for some level
of functionality), then that driver should be fixed up to support the
clock as being optional.
Am I missing something?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-21 8:50 ` Mark Rutland
@ 2013-08-21 21:34 ` Tomasz Figa
-1 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-21 21:34 UTC (permalink / raw)
To: Mark Rutland
Cc: Mike Turquette, Sascha Hauer, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > Quoting Mark Rutland (2013-08-19 02:35:43)
> >
> > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > clock for
> > > > > > > > > mux
> > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > >
> > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > imx6q-clk.txt,
> > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > spdif_ext.
> > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > 'optional'
> > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > even if
> > > > > > > > it's
> > > > > > > > missing.
> > > > > > >
> > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > clocks
> > > > > > > not
> > > > > > > defined by the SoC.
> > > > > >
> > > > > > Where does this assumption come from? Is it documented
> > > > > > anywhere?
> > > > >
> > > > > This is how all i.MX clock bindings currently are. See
> > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > >
> > > > OK, thanks.
> > > >
> > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > I think we want some consistency on this, don't we?
> > > >
> > > > If we really need a dummy clock, then we might also want a generic
> > > > way to specify it.
> > >
> > > What do we actually mean by a "dummy clock"? We already have
> > > bindings
> > > for "fixed-clock" and co friends describe relatively simple
> > > preconfigured clocks.
> >
> > Some platforms have a fake clock which defines noops callbacks and
> > basically doesn't do anything. This is analogous to the dummy
> > regulator
> > implementation. A central one could be registered by the clock core,
> > as
> > is done by the regulator core.
>
> When you say some platforms, you presumably mean the platform code in
> Linux? A dummy clock sounds like a completely Linux-specific abstraction
> rather than a description of the hardware, and I don't see why we need
> that in the DT:
>
> * If a clock is wired up and running (as presumably the dummy clock is),
> then surely it's a fixed-clock (it's running, we and we have no control
> over it, but we presumably know its rate) and can be described as such?
>
> * If no clock is wired up, then we should be able to describe that. If a
> driver believes that a clock is required when it isn't (for some level
> of functionality), then that driver should be fixed up to support the
> clock as being optional.
>
> Am I missing something?
I second that.
Moreover, I don't think that device tree should deal with dummy anything.
It should be able to describe hardware that is available on given system,
not list what hardware is not available.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-21 21:34 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-21 21:34 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, festevam, Sascha Hauer, Nicolin Chen, timur,
rob.herring, broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > Quoting Mark Rutland (2013-08-19 02:35:43)
> >
> > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > clock for
> > > > > > > > > mux
> > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > >
> > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > imx6q-clk.txt,
> > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > spdif_ext.
> > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > 'optional'
> > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > even if
> > > > > > > > it's
> > > > > > > > missing.
> > > > > > >
> > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > clocks
> > > > > > > not
> > > > > > > defined by the SoC.
> > > > > >
> > > > > > Where does this assumption come from? Is it documented
> > > > > > anywhere?
> > > > >
> > > > > This is how all i.MX clock bindings currently are. See
> > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > >
> > > > OK, thanks.
> > > >
> > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > I think we want some consistency on this, don't we?
> > > >
> > > > If we really need a dummy clock, then we might also want a generic
> > > > way to specify it.
> > >
> > > What do we actually mean by a "dummy clock"? We already have
> > > bindings
> > > for "fixed-clock" and co friends describe relatively simple
> > > preconfigured clocks.
> >
> > Some platforms have a fake clock which defines noops callbacks and
> > basically doesn't do anything. This is analogous to the dummy
> > regulator
> > implementation. A central one could be registered by the clock core,
> > as
> > is done by the regulator core.
>
> When you say some platforms, you presumably mean the platform code in
> Linux? A dummy clock sounds like a completely Linux-specific abstraction
> rather than a description of the hardware, and I don't see why we need
> that in the DT:
>
> * If a clock is wired up and running (as presumably the dummy clock is),
> then surely it's a fixed-clock (it's running, we and we have no control
> over it, but we presumably know its rate) and can be described as such?
>
> * If no clock is wired up, then we should be able to describe that. If a
> driver believes that a clock is required when it isn't (for some level
> of functionality), then that driver should be fixed up to support the
> clock as being optional.
>
> Am I missing something?
I second that.
Moreover, I don't think that device tree should deal with dummy anything.
It should be able to describe hardware that is available on given system,
not list what hardware is not available.
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-21 21:34 ` Tomasz Figa
(?)
@ 2013-08-22 7:19 ` Mike Turquette
-1 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-22 7:19 UTC (permalink / raw)
To: Tomasz Figa, Mark Rutland
Cc: Sascha Hauer, Nicolin Chen, ian.campbell, Pawel Moll, galak,
broonie, lars, p.zabel, linuxppc-dev, alsa-devel, devicetree,
timur, rob.herring, shawn.guo, festevam, swarren
Quoting Tomasz Figa (2013-08-21 14:34:55)
> On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > >
> > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > clock for
> > > > > > > > > > mux
> > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > >
> > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > imx6q-clk.txt,
> > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > spdif_ext.
> > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > 'optional'
> > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > even if
> > > > > > > > > it's
> > > > > > > > > missing.
> > > > > > > >
> > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > clocks
> > > > > > > > not
> > > > > > > > defined by the SoC.
> > > > > > >
> > > > > > > Where does this assumption come from? Is it documented
> > > > > > > anywhere?
> > > > > >
> > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > >
> > > > > OK, thanks.
> > > > >
> > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > I think we want some consistency on this, don't we?
> > > > >
> > > > > If we really need a dummy clock, then we might also want a generic
> > > > > way to specify it.
> > > >
> > > > What do we actually mean by a "dummy clock"? We already have
> > > > bindings
> > > > for "fixed-clock" and co friends describe relatively simple
> > > > preconfigured clocks.
> > >
> > > Some platforms have a fake clock which defines noops callbacks and
> > > basically doesn't do anything. This is analogous to the dummy
> > > regulator
> > > implementation. A central one could be registered by the clock core,
> > > as
> > > is done by the regulator core.
> >
> > When you say some platforms, you presumably mean the platform code in
> > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > rather than a description of the hardware, and I don't see why we need
> > that in the DT:
> >
> > * If a clock is wired up and running (as presumably the dummy clock is),
> > then surely it's a fixed-clock (it's running, we and we have no control
> > over it, but we presumably know its rate) and can be described as such?
> >
> > * If no clock is wired up, then we should be able to describe that. If a
> > driver believes that a clock is required when it isn't (for some level
> > of functionality), then that driver should be fixed up to support the
> > clock as being optional.
> >
> > Am I missing something?
>
> I second that.
>
> Moreover, I don't think that device tree should deal with dummy anything.
> It should be able to describe hardware that is available on given system,
> not list what hardware is not available.
I wasn't clear. The dummy clock IS a completely Linux-specific
abstraction.
I'm not advocating a dummy clock in DT. I am advocating consolidation of
the implementation of a clock that does nothing into the clock core.
This code could easily live in drivers/clk/clk.c instead of having
everyone open-code it.
As far as specifying a dummy clock in DT? I dunno. DT should describe
real hardware so there isn't much use for a dummy clock.
I'm guessing one of the reasons for such a clock are drivers do not
honor the clk.h api and they freak out when clk_get gives them a NULL
pointer?
Regards,
Mike
>
> Best regards,
> Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 7:19 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-22 7:19 UTC (permalink / raw)
To: Tomasz Figa, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Sascha Hauer, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Tomasz Figa (2013-08-21 14:34:55)
> On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > >
> > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > clock for
> > > > > > > > > > mux
> > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > >
> > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > imx6q-clk.txt,
> > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > spdif_ext.
> > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > 'optional'
> > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > even if
> > > > > > > > > it's
> > > > > > > > > missing.
> > > > > > > >
> > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > clocks
> > > > > > > > not
> > > > > > > > defined by the SoC.
> > > > > > >
> > > > > > > Where does this assumption come from? Is it documented
> > > > > > > anywhere?
> > > > > >
> > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > >
> > > > > OK, thanks.
> > > > >
> > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > I think we want some consistency on this, don't we?
> > > > >
> > > > > If we really need a dummy clock, then we might also want a generic
> > > > > way to specify it.
> > > >
> > > > What do we actually mean by a "dummy clock"? We already have
> > > > bindings
> > > > for "fixed-clock" and co friends describe relatively simple
> > > > preconfigured clocks.
> > >
> > > Some platforms have a fake clock which defines noops callbacks and
> > > basically doesn't do anything. This is analogous to the dummy
> > > regulator
> > > implementation. A central one could be registered by the clock core,
> > > as
> > > is done by the regulator core.
> >
> > When you say some platforms, you presumably mean the platform code in
> > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > rather than a description of the hardware, and I don't see why we need
> > that in the DT:
> >
> > * If a clock is wired up and running (as presumably the dummy clock is),
> > then surely it's a fixed-clock (it's running, we and we have no control
> > over it, but we presumably know its rate) and can be described as such?
> >
> > * If no clock is wired up, then we should be able to describe that. If a
> > driver believes that a clock is required when it isn't (for some level
> > of functionality), then that driver should be fixed up to support the
> > clock as being optional.
> >
> > Am I missing something?
>
> I second that.
>
> Moreover, I don't think that device tree should deal with dummy anything.
> It should be able to describe hardware that is available on given system,
> not list what hardware is not available.
I wasn't clear. The dummy clock IS a completely Linux-specific
abstraction.
I'm not advocating a dummy clock in DT. I am advocating consolidation of
the implementation of a clock that does nothing into the clock core.
This code could easily live in drivers/clk/clk.c instead of having
everyone open-code it.
As far as specifying a dummy clock in DT? I dunno. DT should describe
real hardware so there isn't much use for a dummy clock.
I'm guessing one of the reasons for such a clock are drivers do not
honor the clk.h api and they freak out when clk_get gives them a NULL
pointer?
Regards,
Mike
>
> Best regards,
> Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 7:19 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-22 7:19 UTC (permalink / raw)
To: Tomasz Figa, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Sascha Hauer, Nicolin Chen, timur, rob.herring,
broonie, p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Tomasz Figa (2013-08-21 14:34:55)
> On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > =
> > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > clock for
> > > > > > > > > > mux
> > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > =
> > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > imx6q-clk.txt,
> > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > spdif_ext.
> > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > 'optional'
> > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > even if
> > > > > > > > > it's
> > > > > > > > > missing.
> > > > > > > > =
> > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > clocks
> > > > > > > > not
> > > > > > > > defined by the SoC.
> > > > > > > =
> > > > > > > Where does this assumption come from? Is it documented
> > > > > > > anywhere?
> > > > > > =
> > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > =
> > > > > OK, thanks.
> > > > > =
> > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > I think we want some consistency on this, don't we?
> > > > > =
> > > > > If we really need a dummy clock, then we might also want a generic
> > > > > way to specify it.
> > > > =
> > > > What do we actually mean by a "dummy clock"? We already have
> > > > bindings
> > > > for "fixed-clock" and co friends describe relatively simple
> > > > preconfigured clocks.
> > > =
> > > Some platforms have a fake clock which defines noops callbacks and
> > > basically doesn't do anything. This is analogous to the dummy
> > > regulator
> > > implementation. A central one could be registered by the clock core,
> > > as
> > > is done by the regulator core.
> > =
> > When you say some platforms, you presumably mean the platform code in
> > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > rather than a description of the hardware, and I don't see why we need
> > that in the DT:
> > =
> > * If a clock is wired up and running (as presumably the dummy clock is),
> > then surely it's a fixed-clock (it's running, we and we have no control
> > over it, but we presumably know its rate) and can be described as such?
> > =
> > * If no clock is wired up, then we should be able to describe that. If a
> > driver believes that a clock is required when it isn't (for some level
> > of functionality), then that driver should be fixed up to support the
> > clock as being optional.
> > =
> > Am I missing something?
> =
> I second that.
> =
> Moreover, I don't think that device tree should deal with dummy anything. =
> It should be able to describe hardware that is available on given system, =
> not list what hardware is not available.
I wasn't clear. The dummy clock IS a completely Linux-specific
abstraction.
I'm not advocating a dummy clock in DT. I am advocating consolidation of
the implementation of a clock that does nothing into the clock core.
This code could easily live in drivers/clk/clk.c instead of having
everyone open-code it.
As far as specifying a dummy clock in DT? I dunno. DT should describe
real hardware so there isn't much use for a dummy clock.
I'm guessing one of the reasons for such a clock are drivers do not
honor the clk.h api and they freak out when clk_get gives them a NULL
pointer?
Regards,
Mike
> =
> Best regards,
> Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-22 7:19 ` Mike Turquette
@ 2013-08-22 12:09 ` Mark Rutland
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-22 12:09 UTC (permalink / raw)
To: Mike Turquette, Sascha Hauer
Cc: Tomasz Figa, Nicolin Chen, ian.campbell, Pawel Moll, galak,
broonie, lars, p.zabel, linuxppc-dev, alsa-devel, devicetree,
timur, rob.herring, shawn.guo, festevam, swarren
On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> Quoting Tomasz Figa (2013-08-21 14:34:55)
> > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > >
> > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > clock for
> > > > > > > > > > > mux
> > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > >
> > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > spdif_ext.
> > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > 'optional'
> > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > even if
> > > > > > > > > > it's
> > > > > > > > > > missing.
> > > > > > > > >
> > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > clocks
> > > > > > > > > not
> > > > > > > > > defined by the SoC.
> > > > > > > >
> > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > anywhere?
> > > > > > >
> > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > >
> > > > > > OK, thanks.
> > > > > >
> > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > I think we want some consistency on this, don't we?
> > > > > >
> > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > way to specify it.
> > > > >
> > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > bindings
> > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > preconfigured clocks.
> > > >
> > > > Some platforms have a fake clock which defines noops callbacks and
> > > > basically doesn't do anything. This is analogous to the dummy
> > > > regulator
> > > > implementation. A central one could be registered by the clock core,
> > > > as
> > > > is done by the regulator core.
> > >
> > > When you say some platforms, you presumably mean the platform code in
> > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > rather than a description of the hardware, and I don't see why we need
> > > that in the DT:
> > >
> > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > then surely it's a fixed-clock (it's running, we and we have no control
> > > over it, but we presumably know its rate) and can be described as such?
> > >
> > > * If no clock is wired up, then we should be able to describe that. If a
> > > driver believes that a clock is required when it isn't (for some level
> > > of functionality), then that driver should be fixed up to support the
> > > clock as being optional.
> > >
> > > Am I missing something?
> >
> > I second that.
> >
> > Moreover, I don't think that device tree should deal with dummy anything.
> > It should be able to describe hardware that is available on given system,
> > not list what hardware is not available.
>
> I wasn't clear. The dummy clock IS a completely Linux-specific
> abstraction.
>
> I'm not advocating a dummy clock in DT. I am advocating consolidation of
> the implementation of a clock that does nothing into the clock core.
> This code could easily live in drivers/clk/clk.c instead of having
> everyone open-code it.
>
> As far as specifying a dummy clock in DT? I dunno. DT should describe
> real hardware so there isn't much use for a dummy clock.
Sorry, I misunderstood. Good to hear we're on the same page :)
>
> I'm guessing one of the reasons for such a clock are drivers do not
> honor the clk.h api and they freak out when clk_get gives them a NULL
> pointer?
I'm not sure. Sascha, could you shed some light on the matter?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 12:09 ` Mark Rutland
0 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-22 12:09 UTC (permalink / raw)
To: Mike Turquette, Sascha Hauer
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Nicolin Chen, Tomasz Figa, rob.herring, timur, broonie,
p.zabel, galak, shawn.guo, linuxppc-dev
On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> Quoting Tomasz Figa (2013-08-21 14:34:55)
> > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > >
> > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > clock for
> > > > > > > > > > > mux
> > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > >
> > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > spdif_ext.
> > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > 'optional'
> > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > even if
> > > > > > > > > > it's
> > > > > > > > > > missing.
> > > > > > > > >
> > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > clocks
> > > > > > > > > not
> > > > > > > > > defined by the SoC.
> > > > > > > >
> > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > anywhere?
> > > > > > >
> > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > >
> > > > > > OK, thanks.
> > > > > >
> > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > I think we want some consistency on this, don't we?
> > > > > >
> > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > way to specify it.
> > > > >
> > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > bindings
> > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > preconfigured clocks.
> > > >
> > > > Some platforms have a fake clock which defines noops callbacks and
> > > > basically doesn't do anything. This is analogous to the dummy
> > > > regulator
> > > > implementation. A central one could be registered by the clock core,
> > > > as
> > > > is done by the regulator core.
> > >
> > > When you say some platforms, you presumably mean the platform code in
> > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > rather than a description of the hardware, and I don't see why we need
> > > that in the DT:
> > >
> > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > then surely it's a fixed-clock (it's running, we and we have no control
> > > over it, but we presumably know its rate) and can be described as such?
> > >
> > > * If no clock is wired up, then we should be able to describe that. If a
> > > driver believes that a clock is required when it isn't (for some level
> > > of functionality), then that driver should be fixed up to support the
> > > clock as being optional.
> > >
> > > Am I missing something?
> >
> > I second that.
> >
> > Moreover, I don't think that device tree should deal with dummy anything.
> > It should be able to describe hardware that is available on given system,
> > not list what hardware is not available.
>
> I wasn't clear. The dummy clock IS a completely Linux-specific
> abstraction.
>
> I'm not advocating a dummy clock in DT. I am advocating consolidation of
> the implementation of a clock that does nothing into the clock core.
> This code could easily live in drivers/clk/clk.c instead of having
> everyone open-code it.
>
> As far as specifying a dummy clock in DT? I dunno. DT should describe
> real hardware so there isn't much use for a dummy clock.
Sorry, I misunderstood. Good to hear we're on the same page :)
>
> I'm guessing one of the reasons for such a clock are drivers do not
> honor the clk.h api and they freak out when clk_get gives them a NULL
> pointer?
I'm not sure. Sascha, could you shed some light on the matter?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-22 12:09 ` Mark Rutland
@ 2013-08-22 21:00 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-22 21:00 UTC (permalink / raw)
To: Mark Rutland
Cc: Mike Turquette, Tomasz Figa, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > >
> > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > > clock for
> > > > > > > > > > > > mux
> > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > >
> > > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > > spdif_ext.
> > > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > > 'optional'
> > > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > > even if
> > > > > > > > > > > it's
> > > > > > > > > > > missing.
> > > > > > > > > >
> > > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > > clocks
> > > > > > > > > > not
> > > > > > > > > > defined by the SoC.
> > > > > > > > >
> > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > anywhere?
> > > > > > > >
> > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > >
> > > > > > > OK, thanks.
> > > > > > >
> > > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > > I think we want some consistency on this, don't we?
> > > > > > >
> > > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > > way to specify it.
> > > > > >
> > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > bindings
> > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > preconfigured clocks.
> > > > >
> > > > > Some platforms have a fake clock which defines noops callbacks and
> > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > regulator
> > > > > implementation. A central one could be registered by the clock core,
> > > > > as
> > > > > is done by the regulator core.
> > > >
> > > > When you say some platforms, you presumably mean the platform code in
> > > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > > rather than a description of the hardware, and I don't see why we need
> > > > that in the DT:
> > > >
> > > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > > then surely it's a fixed-clock (it's running, we and we have no control
> > > > over it, but we presumably know its rate) and can be described as such?
> > > >
> > > > * If no clock is wired up, then we should be able to describe that. If a
> > > > driver believes that a clock is required when it isn't (for some level
> > > > of functionality), then that driver should be fixed up to support the
> > > > clock as being optional.
> > > >
> > > > Am I missing something?
> > >
> > > I second that.
> > >
> > > Moreover, I don't think that device tree should deal with dummy anything.
> > > It should be able to describe hardware that is available on given system,
> > > not list what hardware is not available.
> >
> > I wasn't clear. The dummy clock IS a completely Linux-specific
> > abstraction.
> >
> > I'm not advocating a dummy clock in DT. I am advocating consolidation of
> > the implementation of a clock that does nothing into the clock core.
> > This code could easily live in drivers/clk/clk.c instead of having
> > everyone open-code it.
> >
> > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > real hardware so there isn't much use for a dummy clock.
>
>
> Sorry, I misunderstood. Good to hear we're on the same page :)
>
> >
> > I'm guessing one of the reasons for such a clock are drivers do not
> > honor the clk.h api and they freak out when clk_get gives them a NULL
> > pointer?
>
> I'm not sure. Sascha, could you shed some light on the matter?
The original reason introducing the dummy clocks in the i.MX dtbs
was to provide devices a clock which the driver requests but is
not software controllable. We often have the case where the same
devices are on several SoCs, but not on all of them all clocks have
a bit to en/disable them.
Anyway, to accomplish this we don't need dummy clocks. We can just
describe the real clocks.
BTW with the S/PDIF core on which not all mux inputs are connected
to actual clocks we could also describe the unconnected inputs as
ground clocks with rate 0. This way we describe something which
is really there instead of dummy clocks ;)
Background to why it might be a good idea to connect a ground clock
to the unconnected input pins is that a driver has a chance to
successfully grab all clocks. Otherwise how does the driver distinguish
between an unconnected and an erroneous clock?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 21:00 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-22 21:00 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, festevam, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo,
linuxppc-dev
On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > >
> > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > > clock for
> > > > > > > > > > > > mux
> > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > >
> > > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > > spdif_ext.
> > > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > > 'optional'
> > > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > > even if
> > > > > > > > > > > it's
> > > > > > > > > > > missing.
> > > > > > > > > >
> > > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > > clocks
> > > > > > > > > > not
> > > > > > > > > > defined by the SoC.
> > > > > > > > >
> > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > anywhere?
> > > > > > > >
> > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > >
> > > > > > > OK, thanks.
> > > > > > >
> > > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > > I think we want some consistency on this, don't we?
> > > > > > >
> > > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > > way to specify it.
> > > > > >
> > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > bindings
> > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > preconfigured clocks.
> > > > >
> > > > > Some platforms have a fake clock which defines noops callbacks and
> > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > regulator
> > > > > implementation. A central one could be registered by the clock core,
> > > > > as
> > > > > is done by the regulator core.
> > > >
> > > > When you say some platforms, you presumably mean the platform code in
> > > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > > rather than a description of the hardware, and I don't see why we need
> > > > that in the DT:
> > > >
> > > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > > then surely it's a fixed-clock (it's running, we and we have no control
> > > > over it, but we presumably know its rate) and can be described as such?
> > > >
> > > > * If no clock is wired up, then we should be able to describe that. If a
> > > > driver believes that a clock is required when it isn't (for some level
> > > > of functionality), then that driver should be fixed up to support the
> > > > clock as being optional.
> > > >
> > > > Am I missing something?
> > >
> > > I second that.
> > >
> > > Moreover, I don't think that device tree should deal with dummy anything.
> > > It should be able to describe hardware that is available on given system,
> > > not list what hardware is not available.
> >
> > I wasn't clear. The dummy clock IS a completely Linux-specific
> > abstraction.
> >
> > I'm not advocating a dummy clock in DT. I am advocating consolidation of
> > the implementation of a clock that does nothing into the clock core.
> > This code could easily live in drivers/clk/clk.c instead of having
> > everyone open-code it.
> >
> > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > real hardware so there isn't much use for a dummy clock.
>
>
> Sorry, I misunderstood. Good to hear we're on the same page :)
>
> >
> > I'm guessing one of the reasons for such a clock are drivers do not
> > honor the clk.h api and they freak out when clk_get gives them a NULL
> > pointer?
>
> I'm not sure. Sascha, could you shed some light on the matter?
The original reason introducing the dummy clocks in the i.MX dtbs
was to provide devices a clock which the driver requests but is
not software controllable. We often have the case where the same
devices are on several SoCs, but not on all of them all clocks have
a bit to en/disable them.
Anyway, to accomplish this we don't need dummy clocks. We can just
describe the real clocks.
BTW with the S/PDIF core on which not all mux inputs are connected
to actual clocks we could also describe the unconnected inputs as
ground clocks with rate 0. This way we describe something which
is really there instead of dummy clocks ;)
Background to why it might be a good idea to connect a ground clock
to the unconnected input pins is that a driver has a chance to
successfully grab all clocks. Otherwise how does the driver distinguish
between an unconnected and an erroneous clock?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-22 21:00 ` Sascha Hauer
(?)
@ 2013-08-22 22:43 ` Mike Turquette
-1 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-22 22:43 UTC (permalink / raw)
To: Sascha Hauer, Mark Rutland
Cc: Tomasz Figa, Nicolin Chen, ian.campbell, Pawel Moll, galak,
broonie, lars, p.zabel, linuxppc-dev, alsa-devel, devicetree,
timur, rob.herring, shawn.guo, festevam, swarren
Quoting Sascha Hauer (2013-08-22 14:00:35)
> On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > >
> > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > > > clock for
> > > > > > > > > > > > > mux
> > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > >
> > > > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > > > 'optional'
> > > > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > > > even if
> > > > > > > > > > > > it's
> > > > > > > > > > > > missing.
> > > > > > > > > > >
> > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > > > clocks
> > > > > > > > > > > not
> > > > > > > > > > > defined by the SoC.
> > > > > > > > > >
> > > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > > anywhere?
> > > > > > > > >
> > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > >
> > > > > > > > OK, thanks.
> > > > > > > >
> > > > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > >
> > > > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > > > way to specify it.
> > > > > > >
> > > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > > bindings
> > > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > > preconfigured clocks.
> > > > > >
> > > > > > Some platforms have a fake clock which defines noops callbacks and
> > > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > > regulator
> > > > > > implementation. A central one could be registered by the clock core,
> > > > > > as
> > > > > > is done by the regulator core.
> > > > >
> > > > > When you say some platforms, you presumably mean the platform code in
> > > > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > > > rather than a description of the hardware, and I don't see why we need
> > > > > that in the DT:
> > > > >
> > > > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > > > then surely it's a fixed-clock (it's running, we and we have no control
> > > > > over it, but we presumably know its rate) and can be described as such?
> > > > >
> > > > > * If no clock is wired up, then we should be able to describe that. If a
> > > > > driver believes that a clock is required when it isn't (for some level
> > > > > of functionality), then that driver should be fixed up to support the
> > > > > clock as being optional.
> > > > >
> > > > > Am I missing something?
> > > >
> > > > I second that.
> > > >
> > > > Moreover, I don't think that device tree should deal with dummy anything.
> > > > It should be able to describe hardware that is available on given system,
> > > > not list what hardware is not available.
> > >
> > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > abstraction.
> > >
> > > I'm not advocating a dummy clock in DT. I am advocating consolidation of
> > > the implementation of a clock that does nothing into the clock core.
> > > This code could easily live in drivers/clk/clk.c instead of having
> > > everyone open-code it.
> > >
> > > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > > real hardware so there isn't much use for a dummy clock.
> >
> >
> > Sorry, I misunderstood. Good to hear we're on the same page :)
> >
> > >
> > > I'm guessing one of the reasons for such a clock are drivers do not
> > > honor the clk.h api and they freak out when clk_get gives them a NULL
> > > pointer?
> >
> > I'm not sure. Sascha, could you shed some light on the matter?
>
> The original reason introducing the dummy clocks in the i.MX dtbs
> was to provide devices a clock which the driver requests but is
> not software controllable. We often have the case where the same
> devices are on several SoCs, but not on all of them all clocks have
> a bit to en/disable them.
>
> Anyway, to accomplish this we don't need dummy clocks. We can just
> describe the real clocks.
You could use a dummy clk for the Linux implementation, but the downside
is that a dummy clock has a rate of 0 always and a your clocks likely
have non-zero rates.
It is probably better for you define a clock which only implements the
.recalc_rate callback. If the rate of this clock changes without Linux
having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
>
> BTW with the S/PDIF core on which not all mux inputs are connected
> to actual clocks we could also describe the unconnected inputs as
> ground clocks with rate 0. This way we describe something which
> is really there instead of dummy clocks ;)
Again you could use a dummy clock for this OR a fixed-rate clock with a
rate of zero from the perspective of the Linux implementation.
Do you think it worthwhile to have a DT binding for a grounded clock?
That is not an entirely uncommon case.
>
> Background to why it might be a good idea to connect a ground clock
> to the unconnected input pins is that a driver has a chance to
> successfully grab all clocks. Otherwise how does the driver distinguish
> between an unconnected and an erroneous clock?
Sorry, I don't follow this last question. Do you mean how to distinguish
based on the value returned from clk_get?
Regards,
Mike
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 22:43 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-22 22:43 UTC (permalink / raw)
To: Sascha Hauer, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Nicolin Chen, Tomasz Figa, rob.herring, timur, broonie,
p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Sascha Hauer (2013-08-22 14:00:35)
> On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > >
> > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > > > clock for
> > > > > > > > > > > > > mux
> > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > >
> > > > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > > > 'optional'
> > > > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > > > even if
> > > > > > > > > > > > it's
> > > > > > > > > > > > missing.
> > > > > > > > > > >
> > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > > > clocks
> > > > > > > > > > > not
> > > > > > > > > > > defined by the SoC.
> > > > > > > > > >
> > > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > > anywhere?
> > > > > > > > >
> > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > >
> > > > > > > > OK, thanks.
> > > > > > > >
> > > > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > >
> > > > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > > > way to specify it.
> > > > > > >
> > > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > > bindings
> > > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > > preconfigured clocks.
> > > > > >
> > > > > > Some platforms have a fake clock which defines noops callbacks and
> > > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > > regulator
> > > > > > implementation. A central one could be registered by the clock core,
> > > > > > as
> > > > > > is done by the regulator core.
> > > > >
> > > > > When you say some platforms, you presumably mean the platform code in
> > > > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > > > rather than a description of the hardware, and I don't see why we need
> > > > > that in the DT:
> > > > >
> > > > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > > > then surely it's a fixed-clock (it's running, we and we have no control
> > > > > over it, but we presumably know its rate) and can be described as such?
> > > > >
> > > > > * If no clock is wired up, then we should be able to describe that. If a
> > > > > driver believes that a clock is required when it isn't (for some level
> > > > > of functionality), then that driver should be fixed up to support the
> > > > > clock as being optional.
> > > > >
> > > > > Am I missing something?
> > > >
> > > > I second that.
> > > >
> > > > Moreover, I don't think that device tree should deal with dummy anything.
> > > > It should be able to describe hardware that is available on given system,
> > > > not list what hardware is not available.
> > >
> > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > abstraction.
> > >
> > > I'm not advocating a dummy clock in DT. I am advocating consolidation of
> > > the implementation of a clock that does nothing into the clock core.
> > > This code could easily live in drivers/clk/clk.c instead of having
> > > everyone open-code it.
> > >
> > > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > > real hardware so there isn't much use for a dummy clock.
> >
> >
> > Sorry, I misunderstood. Good to hear we're on the same page :)
> >
> > >
> > > I'm guessing one of the reasons for such a clock are drivers do not
> > > honor the clk.h api and they freak out when clk_get gives them a NULL
> > > pointer?
> >
> > I'm not sure. Sascha, could you shed some light on the matter?
>
> The original reason introducing the dummy clocks in the i.MX dtbs
> was to provide devices a clock which the driver requests but is
> not software controllable. We often have the case where the same
> devices are on several SoCs, but not on all of them all clocks have
> a bit to en/disable them.
>
> Anyway, to accomplish this we don't need dummy clocks. We can just
> describe the real clocks.
You could use a dummy clk for the Linux implementation, but the downside
is that a dummy clock has a rate of 0 always and a your clocks likely
have non-zero rates.
It is probably better for you define a clock which only implements the
.recalc_rate callback. If the rate of this clock changes without Linux
having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
>
> BTW with the S/PDIF core on which not all mux inputs are connected
> to actual clocks we could also describe the unconnected inputs as
> ground clocks with rate 0. This way we describe something which
> is really there instead of dummy clocks ;)
Again you could use a dummy clock for this OR a fixed-rate clock with a
rate of zero from the perspective of the Linux implementation.
Do you think it worthwhile to have a DT binding for a grounded clock?
That is not an entirely uncommon case.
>
> Background to why it might be a good idea to connect a ground clock
> to the unconnected input pins is that a driver has a chance to
> successfully grab all clocks. Otherwise how does the driver distinguish
> between an unconnected and an erroneous clock?
Sorry, I don't follow this last question. Do you mean how to distinguish
based on the value returned from clk_get?
Regards,
Mike
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 22:43 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-22 22:43 UTC (permalink / raw)
To: Sascha Hauer, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Nicolin Chen, Tomasz Figa, rob.herring, timur, broonie,
p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Sascha Hauer (2013-08-22 14:00:35)
> On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > =
> > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wro=
te:
> > > > > > > > > > > > > Also I would make this option required. Use a dum=
my
> > > > > > > > > > > > > clock for
> > > > > > > > > > > > > mux
> > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > =
> > > > > > > > > > > > Some clocks are not from CCM and we haven't defined=
in
> > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > so in most cases we can't provide a phandle for the=
m, eg:
> > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > I think it's a bit hard to force it to be 'required=
'. An
> > > > > > > > > > > > 'optional'
> > > > > > > > > > > > looks more flexible to me and a default one is ensu=
red
> > > > > > > > > > > > even if
> > > > > > > > > > > > it's
> > > > > > > > > > > > missing.
> > > > > > > > > > > =
> > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for al=
l input
> > > > > > > > > > > clocks
> > > > > > > > > > > not
> > > > > > > > > > > defined by the SoC.
> > > > > > > > > > =
> > > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > > anywhere?
> > > > > > > > > =
> > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > =
> > > > > > > > OK, thanks.
> > > > > > > > =
> > > > > > > > I guess we need some discussion on dummy clocks vs skipped =
clocks.
> > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > =
> > > > > > > > If we really need a dummy clock, then we might also want a =
generic
> > > > > > > > way to specify it.
> > > > > > > =
> > > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > > bindings
> > > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > > preconfigured clocks.
> > > > > > =
> > > > > > Some platforms have a fake clock which defines noops callbacks =
and
> > > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > > regulator
> > > > > > implementation. A central one could be registered by the clock =
core,
> > > > > > as
> > > > > > is done by the regulator core.
> > > > > =
> > > > > When you say some platforms, you presumably mean the platform cod=
e in
> > > > > Linux? A dummy clock sounds like a completely Linux-specific abst=
raction
> > > > > rather than a description of the hardware, and I don't see why we=
need
> > > > > that in the DT:
> > > > > =
> > > > > * If a clock is wired up and running (as presumably the dummy clo=
ck is),
> > > > > then surely it's a fixed-clock (it's running, we and we have no c=
ontrol
> > > > > over it, but we presumably know its rate) and can be described as=
such?
> > > > > =
> > > > > * If no clock is wired up, then we should be able to describe tha=
t. If a
> > > > > driver believes that a clock is required when it isn't (for some =
level
> > > > > of functionality), then that driver should be fixed up to support=
the
> > > > > clock as being optional.
> > > > > =
> > > > > Am I missing something?
> > > > =
> > > > I second that.
> > > > =
> > > > Moreover, I don't think that device tree should deal with dummy any=
thing. =
> > > > It should be able to describe hardware that is available on given s=
ystem, =
> > > > not list what hardware is not available.
> > > =
> > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > abstraction.
> > > =
> > > I'm not advocating a dummy clock in DT. I am advocating consolidation=
of
> > > the implementation of a clock that does nothing into the clock core.
> > > This code could easily live in drivers/clk/clk.c instead of having
> > > everyone open-code it.
> > > =
> > > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > > real hardware so there isn't much use for a dummy clock.
> > =
> > =
> > Sorry, I misunderstood. Good to hear we're on the same page :)
> > =
> > > =
> > > I'm guessing one of the reasons for such a clock are drivers do not
> > > honor the clk.h api and they freak out when clk_get gives them a NULL
> > > pointer?
> > =
> > I'm not sure. Sascha, could you shed some light on the matter?
> =
> The original reason introducing the dummy clocks in the i.MX dtbs
> was to provide devices a clock which the driver requests but is
> not software controllable. We often have the case where the same
> devices are on several SoCs, but not on all of them all clocks have
> a bit to en/disable them.
> =
> Anyway, to accomplish this we don't need dummy clocks. We can just
> describe the real clocks.
You could use a dummy clk for the Linux implementation, but the downside
is that a dummy clock has a rate of 0 always and a your clocks likely
have non-zero rates.
It is probably better for you define a clock which only implements the
.recalc_rate callback. If the rate of this clock changes without Linux
having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> =
> BTW with the S/PDIF core on which not all mux inputs are connected
> to actual clocks we could also describe the unconnected inputs as
> ground clocks with rate 0. This way we describe something which
> is really there instead of dummy clocks ;)
Again you could use a dummy clock for this OR a fixed-rate clock with a
rate of zero from the perspective of the Linux implementation.
Do you think it worthwhile to have a DT binding for a grounded clock?
That is not an entirely uncommon case.
> =
> Background to why it might be a good idea to connect a ground clock
> to the unconnected input pins is that a driver has a chance to
> successfully grab all clocks. Otherwise how does the driver distinguish
> between an unconnected and an erroneous clock?
Sorry, I don't follow this last question. Do you mean how to distinguish
based on the value returned from clk_get?
Regards,
Mike
> =
> Sascha
> =
> -- =
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-22 22:43 ` Mike Turquette
@ 2013-08-22 22:49 ` Tomasz Figa
-1 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-22 22:49 UTC (permalink / raw)
To: Mike Turquette
Cc: Sascha Hauer, Mark Rutland, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> Quoting Sascha Hauer (2013-08-22 14:00:35)
>
> > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > >
> > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
wrote:
> > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > >
> > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
wrote:
> > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
wrote:
> > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
wrote:
> > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > defined in
> > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > ensured
> > > > > > > > > > > > > even if
> > > > > > > > > > > > > it's
> > > > > > > > > > > > > missing.
> > > > > > > > > > > >
> > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > all input
> > > > > > > > > > > > clocks
> > > > > > > > > > > > not
> > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > >
> > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > documented
> > > > > > > > > > > anywhere?
> > > > > > > > > >
> > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > >
> > > > > > > > > OK, thanks.
> > > > > > > > >
> > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > skipped clocks.
> > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > >
> > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > a generic
> > > > > > > > > way to specify it.
> > > > > > > >
> > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > have
> > > > > > > > bindings
> > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > simple
> > > > > > > > preconfigured clocks.
> > > > > > >
> > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > callbacks and
> > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > dummy
> > > > > > > regulator
> > > > > > > implementation. A central one could be registered by the
> > > > > > > clock core,
> > > > > > > as
> > > > > > > is done by the regulator core.
> > > > > >
> > > > > > When you say some platforms, you presumably mean the platform
> > > > > > code in
> > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > abstraction rather than a description of the hardware, and I
> > > > > > don't see why we need that in the DT:
> > > > > >
> > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > and we have no control over it, but we presumably know its
> > > > > > rate) and can be described as such?
> > > > > >
> > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > that. If a driver believes that a clock is required when it
> > > > > > isn't (for some level of functionality), then that driver
> > > > > > should be fixed up to support the clock as being optional.
> > > > > >
> > > > > > Am I missing something?
> > > > >
> > > > > I second that.
> > > > >
> > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > anything. It should be able to describe hardware that is
> > > > > available on given system, not list what hardware is not
> > > > > available.
> > > >
> > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > abstraction.
> > > >
> > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > consolidation of the implementation of a clock that does nothing
> > > > into the clock core. This code could easily live in
> > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > >
> > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > describe
> > > > real hardware so there isn't much use for a dummy clock.
> > >
> > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > >
> > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > not
> > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > NULL
> > > > pointer?
> > >
> > > I'm not sure. Sascha, could you shed some light on the matter?
> >
> > The original reason introducing the dummy clocks in the i.MX dtbs
> > was to provide devices a clock which the driver requests but is
> > not software controllable. We often have the case where the same
> > devices are on several SoCs, but not on all of them all clocks have
> > a bit to en/disable them.
> >
> > Anyway, to accomplish this we don't need dummy clocks. We can just
> > describe the real clocks.
>
> You could use a dummy clk for the Linux implementation, but the downside
> is that a dummy clock has a rate of 0 always and a your clocks likely
> have non-zero rates.
>
> It is probably better for you define a clock which only implements the
> .recalc_rate callback. If the rate of this clock changes without Linux
> having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
I doubt that rate of a dummy clock could ever change... unless it is a
rather smart dummy.
> > BTW with the S/PDIF core on which not all mux inputs are connected
> > to actual clocks we could also describe the unconnected inputs as
> > ground clocks with rate 0. This way we describe something which
> > is really there instead of dummy clocks ;)
>
> Again you could use a dummy clock for this OR a fixed-rate clock with a
> rate of zero from the perspective of the Linux implementation.
>
> Do you think it worthwhile to have a DT binding for a grounded clock?
> That is not an entirely uncommon case.
Well, how would that differ from skipping a clock from clocks list, i.e.
not specifying it in clock-names and clocks properties?
> > Background to why it might be a good idea to connect a ground clock
> > to the unconnected input pins is that a driver has a chance to
> > successfully grab all clocks. Otherwise how does the driver
> > distinguish
> > between an unconnected and an erroneous clock?
>
> Sorry, I don't follow this last question. Do you mean how to distinguish
> based on the value returned from clk_get?
Hmm, in theory, a driver could want to distinguish an error case (e.g.
clock specified, but there is a problem with it) from no clock (e.g. clock
not specified in DT, because it is not available on particular board).
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-22 22:49 ` Tomasz Figa
0 siblings, 0 replies; 77+ messages in thread
From: Tomasz Figa @ 2013-08-22 22:49 UTC (permalink / raw)
To: Mike Turquette
Cc: Mark Rutland, devicetree, alsa-devel, lars, ian.campbell,
Pawel Moll, swarren, festevam, Sascha Hauer, Nicolin Chen, timur,
rob.herring, broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> Quoting Sascha Hauer (2013-08-22 14:00:35)
>
> > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > >
> > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
wrote:
> > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > >
> > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
wrote:
> > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
wrote:
> > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
wrote:
> > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > defined in
> > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > ensured
> > > > > > > > > > > > > even if
> > > > > > > > > > > > > it's
> > > > > > > > > > > > > missing.
> > > > > > > > > > > >
> > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > all input
> > > > > > > > > > > > clocks
> > > > > > > > > > > > not
> > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > >
> > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > documented
> > > > > > > > > > > anywhere?
> > > > > > > > > >
> > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > >
> > > > > > > > > OK, thanks.
> > > > > > > > >
> > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > skipped clocks.
> > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > >
> > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > a generic
> > > > > > > > > way to specify it.
> > > > > > > >
> > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > have
> > > > > > > > bindings
> > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > simple
> > > > > > > > preconfigured clocks.
> > > > > > >
> > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > callbacks and
> > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > dummy
> > > > > > > regulator
> > > > > > > implementation. A central one could be registered by the
> > > > > > > clock core,
> > > > > > > as
> > > > > > > is done by the regulator core.
> > > > > >
> > > > > > When you say some platforms, you presumably mean the platform
> > > > > > code in
> > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > abstraction rather than a description of the hardware, and I
> > > > > > don't see why we need that in the DT:
> > > > > >
> > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > and we have no control over it, but we presumably know its
> > > > > > rate) and can be described as such?
> > > > > >
> > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > that. If a driver believes that a clock is required when it
> > > > > > isn't (for some level of functionality), then that driver
> > > > > > should be fixed up to support the clock as being optional.
> > > > > >
> > > > > > Am I missing something?
> > > > >
> > > > > I second that.
> > > > >
> > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > anything. It should be able to describe hardware that is
> > > > > available on given system, not list what hardware is not
> > > > > available.
> > > >
> > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > abstraction.
> > > >
> > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > consolidation of the implementation of a clock that does nothing
> > > > into the clock core. This code could easily live in
> > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > >
> > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > describe
> > > > real hardware so there isn't much use for a dummy clock.
> > >
> > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > >
> > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > not
> > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > NULL
> > > > pointer?
> > >
> > > I'm not sure. Sascha, could you shed some light on the matter?
> >
> > The original reason introducing the dummy clocks in the i.MX dtbs
> > was to provide devices a clock which the driver requests but is
> > not software controllable. We often have the case where the same
> > devices are on several SoCs, but not on all of them all clocks have
> > a bit to en/disable them.
> >
> > Anyway, to accomplish this we don't need dummy clocks. We can just
> > describe the real clocks.
>
> You could use a dummy clk for the Linux implementation, but the downside
> is that a dummy clock has a rate of 0 always and a your clocks likely
> have non-zero rates.
>
> It is probably better for you define a clock which only implements the
> .recalc_rate callback. If the rate of this clock changes without Linux
> having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
I doubt that rate of a dummy clock could ever change... unless it is a
rather smart dummy.
> > BTW with the S/PDIF core on which not all mux inputs are connected
> > to actual clocks we could also describe the unconnected inputs as
> > ground clocks with rate 0. This way we describe something which
> > is really there instead of dummy clocks ;)
>
> Again you could use a dummy clock for this OR a fixed-rate clock with a
> rate of zero from the perspective of the Linux implementation.
>
> Do you think it worthwhile to have a DT binding for a grounded clock?
> That is not an entirely uncommon case.
Well, how would that differ from skipping a clock from clocks list, i.e.
not specifying it in clock-names and clocks properties?
> > Background to why it might be a good idea to connect a ground clock
> > to the unconnected input pins is that a driver has a chance to
> > successfully grab all clocks. Otherwise how does the driver
> > distinguish
> > between an unconnected and an erroneous clock?
>
> Sorry, I don't follow this last question. Do you mean how to distinguish
> based on the value returned from clk_get?
Hmm, in theory, a driver could want to distinguish an error case (e.g.
clock specified, but there is a problem with it) from no clock (e.g. clock
not specified in DT, because it is not available on particular board).
Best regards,
Tomasz
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-22 22:49 ` Tomasz Figa
@ 2013-08-23 6:34 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-23 6:34 UTC (permalink / raw)
To: Tomasz Figa
Cc: Mike Turquette, Mark Rutland, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > Quoting Sascha Hauer (2013-08-22 14:00:35)
> >
> > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > >
> > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> wrote:
> > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > >
> > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> wrote:
> > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> wrote:
> > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> wrote:
> > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > missing.
> > > > > > > > > > > > >
> > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > all input
> > > > > > > > > > > > > clocks
> > > > > > > > > > > > > not
> > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > >
> > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > documented
> > > > > > > > > > > > anywhere?
> > > > > > > > > > >
> > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > >
> > > > > > > > > > OK, thanks.
> > > > > > > > > >
> > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > skipped clocks.
> > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > >
> > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > a generic
> > > > > > > > > > way to specify it.
> > > > > > > > >
> > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > have
> > > > > > > > > bindings
> > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > simple
> > > > > > > > > preconfigured clocks.
> > > > > > > >
> > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > callbacks and
> > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > dummy
> > > > > > > > regulator
> > > > > > > > implementation. A central one could be registered by the
> > > > > > > > clock core,
> > > > > > > > as
> > > > > > > > is done by the regulator core.
> > > > > > >
> > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > code in
> > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > don't see why we need that in the DT:
> > > > > > >
> > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > and we have no control over it, but we presumably know its
> > > > > > > rate) and can be described as such?
> > > > > > >
> > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > should be fixed up to support the clock as being optional.
> > > > > > >
> > > > > > > Am I missing something?
> > > > > >
> > > > > > I second that.
> > > > > >
> > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > anything. It should be able to describe hardware that is
> > > > > > available on given system, not list what hardware is not
> > > > > > available.
> > > > >
> > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > abstraction.
> > > > >
> > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > consolidation of the implementation of a clock that does nothing
> > > > > into the clock core. This code could easily live in
> > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > >
> > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > describe
> > > > > real hardware so there isn't much use for a dummy clock.
> > > >
> > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > >
> > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > not
> > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > NULL
> > > > > pointer?
> > > >
> > > > I'm not sure. Sascha, could you shed some light on the matter?
> > >
> > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > was to provide devices a clock which the driver requests but is
> > > not software controllable. We often have the case where the same
> > > devices are on several SoCs, but not on all of them all clocks have
> > > a bit to en/disable them.
> > >
> > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > describe the real clocks.
> >
> > You could use a dummy clk for the Linux implementation, but the downside
> > is that a dummy clock has a rate of 0 always and a your clocks likely
> > have non-zero rates.
> >
> > It is probably better for you define a clock which only implements the
> > .recalc_rate callback. If the rate of this clock changes without Linux
> > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
>
> I doubt that rate of a dummy clock could ever change... unless it is a
> rather smart dummy.
>
> > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > to actual clocks we could also describe the unconnected inputs as
> > > ground clocks with rate 0. This way we describe something which
> > > is really there instead of dummy clocks ;)
> >
> > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > rate of zero from the perspective of the Linux implementation.
> >
> > Do you think it worthwhile to have a DT binding for a grounded clock?
> > That is not an entirely uncommon case.
>
> Well, how would that differ from skipping a clock from clocks list, i.e.
> not specifying it in clock-names and clocks properties?
The difference is that you can successfully grab it in your driver.
>
> > > Background to why it might be a good idea to connect a ground clock
> > > to the unconnected input pins is that a driver has a chance to
> > > successfully grab all clocks. Otherwise how does the driver
> > > distinguish
> > > between an unconnected and an erroneous clock?
> >
> > Sorry, I don't follow this last question. Do you mean how to distinguish
> > based on the value returned from clk_get?
>
> Hmm, in theory, a driver could want to distinguish an error case (e.g.
> clock specified, but there is a problem with it) from no clock (e.g. clock
> not specified in DT, because it is not available on particular board).
Yes, that's what I meant. To illustrate the problem for this driver:
for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
sprintf(tmp, "rxtx%d", i);
clk = devm_clk_get(&pdev->dev, tmp);
if (IS_ERR(clk)) {
/*
* This can either mean this clock is not wired
* up (skipped in the devicetree, *or* it is wired
* up, but there went something wrong requesting it.
* We can only ignore this error.
*/
}
}
This could be solved by always specifying all input clocks in the
devicetree.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 6:34 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-23 6:34 UTC (permalink / raw)
To: Tomasz Figa
Cc: Mark Rutland, devicetree, alsa-devel, lars, Mike Turquette,
ian.campbell, Pawel Moll, swarren, festevam, Nicolin Chen, timur,
rob.herring, broonie, p.zabel, galak, shawn.guo, linuxppc-dev
On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > Quoting Sascha Hauer (2013-08-22 14:00:35)
> >
> > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > >
> > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> wrote:
> > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > >
> > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> wrote:
> > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> wrote:
> > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> wrote:
> > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > missing.
> > > > > > > > > > > > >
> > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > all input
> > > > > > > > > > > > > clocks
> > > > > > > > > > > > > not
> > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > >
> > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > documented
> > > > > > > > > > > > anywhere?
> > > > > > > > > > >
> > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > >
> > > > > > > > > > OK, thanks.
> > > > > > > > > >
> > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > skipped clocks.
> > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > >
> > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > a generic
> > > > > > > > > > way to specify it.
> > > > > > > > >
> > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > have
> > > > > > > > > bindings
> > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > simple
> > > > > > > > > preconfigured clocks.
> > > > > > > >
> > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > callbacks and
> > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > dummy
> > > > > > > > regulator
> > > > > > > > implementation. A central one could be registered by the
> > > > > > > > clock core,
> > > > > > > > as
> > > > > > > > is done by the regulator core.
> > > > > > >
> > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > code in
> > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > don't see why we need that in the DT:
> > > > > > >
> > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > and we have no control over it, but we presumably know its
> > > > > > > rate) and can be described as such?
> > > > > > >
> > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > should be fixed up to support the clock as being optional.
> > > > > > >
> > > > > > > Am I missing something?
> > > > > >
> > > > > > I second that.
> > > > > >
> > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > anything. It should be able to describe hardware that is
> > > > > > available on given system, not list what hardware is not
> > > > > > available.
> > > > >
> > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > abstraction.
> > > > >
> > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > consolidation of the implementation of a clock that does nothing
> > > > > into the clock core. This code could easily live in
> > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > >
> > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > describe
> > > > > real hardware so there isn't much use for a dummy clock.
> > > >
> > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > >
> > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > not
> > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > NULL
> > > > > pointer?
> > > >
> > > > I'm not sure. Sascha, could you shed some light on the matter?
> > >
> > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > was to provide devices a clock which the driver requests but is
> > > not software controllable. We often have the case where the same
> > > devices are on several SoCs, but not on all of them all clocks have
> > > a bit to en/disable them.
> > >
> > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > describe the real clocks.
> >
> > You could use a dummy clk for the Linux implementation, but the downside
> > is that a dummy clock has a rate of 0 always and a your clocks likely
> > have non-zero rates.
> >
> > It is probably better for you define a clock which only implements the
> > .recalc_rate callback. If the rate of this clock changes without Linux
> > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
>
> I doubt that rate of a dummy clock could ever change... unless it is a
> rather smart dummy.
>
> > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > to actual clocks we could also describe the unconnected inputs as
> > > ground clocks with rate 0. This way we describe something which
> > > is really there instead of dummy clocks ;)
> >
> > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > rate of zero from the perspective of the Linux implementation.
> >
> > Do you think it worthwhile to have a DT binding for a grounded clock?
> > That is not an entirely uncommon case.
>
> Well, how would that differ from skipping a clock from clocks list, i.e.
> not specifying it in clock-names and clocks properties?
The difference is that you can successfully grab it in your driver.
>
> > > Background to why it might be a good idea to connect a ground clock
> > > to the unconnected input pins is that a driver has a chance to
> > > successfully grab all clocks. Otherwise how does the driver
> > > distinguish
> > > between an unconnected and an erroneous clock?
> >
> > Sorry, I don't follow this last question. Do you mean how to distinguish
> > based on the value returned from clk_get?
>
> Hmm, in theory, a driver could want to distinguish an error case (e.g.
> clock specified, but there is a problem with it) from no clock (e.g. clock
> not specified in DT, because it is not available on particular board).
Yes, that's what I meant. To illustrate the problem for this driver:
for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
sprintf(tmp, "rxtx%d", i);
clk = devm_clk_get(&pdev->dev, tmp);
if (IS_ERR(clk)) {
/*
* This can either mean this clock is not wired
* up (skipped in the devicetree, *or* it is wired
* up, but there went something wrong requesting it.
* We can only ignore this error.
*/
}
}
This could be solved by always specifying all input clocks in the
devicetree.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-22 21:00 ` Sascha Hauer
@ 2013-08-23 12:44 ` Mark Rutland
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-23 12:44 UTC (permalink / raw)
To: Sascha Hauer
Cc: Mike Turquette, Tomasz Figa, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Thu, Aug 22, 2013 at 10:00:35PM +0100, Sascha Hauer wrote:
> On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > >
> > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > > > clock for
> > > > > > > > > > > > > mux
> > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > >
> > > > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > > > 'optional'
> > > > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > > > even if
> > > > > > > > > > > > it's
> > > > > > > > > > > > missing.
> > > > > > > > > > >
> > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > > > clocks
> > > > > > > > > > > not
> > > > > > > > > > > defined by the SoC.
> > > > > > > > > >
> > > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > > anywhere?
> > > > > > > > >
> > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > >
> > > > > > > > OK, thanks.
> > > > > > > >
> > > > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > >
> > > > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > > > way to specify it.
> > > > > > >
> > > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > > bindings
> > > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > > preconfigured clocks.
> > > > > >
> > > > > > Some platforms have a fake clock which defines noops callbacks and
> > > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > > regulator
> > > > > > implementation. A central one could be registered by the clock core,
> > > > > > as
> > > > > > is done by the regulator core.
> > > > >
> > > > > When you say some platforms, you presumably mean the platform code in
> > > > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > > > rather than a description of the hardware, and I don't see why we need
> > > > > that in the DT:
> > > > >
> > > > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > > > then surely it's a fixed-clock (it's running, we and we have no control
> > > > > over it, but we presumably know its rate) and can be described as such?
> > > > >
> > > > > * If no clock is wired up, then we should be able to describe that. If a
> > > > > driver believes that a clock is required when it isn't (for some level
> > > > > of functionality), then that driver should be fixed up to support the
> > > > > clock as being optional.
> > > > >
> > > > > Am I missing something?
> > > >
> > > > I second that.
> > > >
> > > > Moreover, I don't think that device tree should deal with dummy anything.
> > > > It should be able to describe hardware that is available on given system,
> > > > not list what hardware is not available.
> > >
> > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > abstraction.
> > >
> > > I'm not advocating a dummy clock in DT. I am advocating consolidation of
> > > the implementation of a clock that does nothing into the clock core.
> > > This code could easily live in drivers/clk/clk.c instead of having
> > > everyone open-code it.
> > >
> > > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > > real hardware so there isn't much use for a dummy clock.
> >
> >
> > Sorry, I misunderstood. Good to hear we're on the same page :)
> >
> > >
> > > I'm guessing one of the reasons for such a clock are drivers do not
> > > honor the clk.h api and they freak out when clk_get gives them a NULL
> > > pointer?
> >
> > I'm not sure. Sascha, could you shed some light on the matter?
>
> The original reason introducing the dummy clocks in the i.MX dtbs
> was to provide devices a clock which the driver requests but is
> not software controllable. We often have the case where the same
> devices are on several SoCs, but not on all of them all clocks have
> a bit to en/disable them.
So those clocks are always on at some fixed rate?
>
> Anyway, to accomplish this we don't need dummy clocks. We can just
> describe the real clocks.
Ok.
>
> BTW with the S/PDIF core on which not all mux inputs are connected
> to actual clocks we could also describe the unconnected inputs as
> ground clocks with rate 0. This way we describe something which
> is really there instead of dummy clocks ;)
>
> Background to why it might be a good idea to connect a ground clock
> to the unconnected input pins is that a driver has a chance to
> successfully grab all clocks. Otherwise how does the driver distinguish
> between an unconnected and an erroneous clock?
Surely the presence of a name in "clock-names" tells you that a clock is
connected, and if not listed it's not connected? If we don't have the
infrastructure for telling apart unconnected clocks from inability to
enable/configure clocks, that's a Linux issue rather than something that
should be hacked up in the dt.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 12:44 ` Mark Rutland
0 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-23 12:44 UTC (permalink / raw)
To: Sascha Hauer
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, festevam, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo,
linuxppc-dev
On Thu, Aug 22, 2013 at 10:00:35PM +0100, Sascha Hauer wrote:
> On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette wrote:
> > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > >
> > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa wrote:
> > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer wrote:
> > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa wrote:
> > > > > > > > > > > > > Also I would make this option required. Use a dummy
> > > > > > > > > > > > > clock for
> > > > > > > > > > > > > mux
> > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > >
> > > > > > > > > > > > Some clocks are not from CCM and we haven't defined in
> > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > so in most cases we can't provide a phandle for them, eg:
> > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > I think it's a bit hard to force it to be 'required'. An
> > > > > > > > > > > > 'optional'
> > > > > > > > > > > > looks more flexible to me and a default one is ensured
> > > > > > > > > > > > even if
> > > > > > > > > > > > it's
> > > > > > > > > > > > missing.
> > > > > > > > > > >
> > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for all input
> > > > > > > > > > > clocks
> > > > > > > > > > > not
> > > > > > > > > > > defined by the SoC.
> > > > > > > > > >
> > > > > > > > > > Where does this assumption come from? Is it documented
> > > > > > > > > > anywhere?
> > > > > > > > >
> > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > >
> > > > > > > > OK, thanks.
> > > > > > > >
> > > > > > > > I guess we need some discussion on dummy clocks vs skipped clocks.
> > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > >
> > > > > > > > If we really need a dummy clock, then we might also want a generic
> > > > > > > > way to specify it.
> > > > > > >
> > > > > > > What do we actually mean by a "dummy clock"? We already have
> > > > > > > bindings
> > > > > > > for "fixed-clock" and co friends describe relatively simple
> > > > > > > preconfigured clocks.
> > > > > >
> > > > > > Some platforms have a fake clock which defines noops callbacks and
> > > > > > basically doesn't do anything. This is analogous to the dummy
> > > > > > regulator
> > > > > > implementation. A central one could be registered by the clock core,
> > > > > > as
> > > > > > is done by the regulator core.
> > > > >
> > > > > When you say some platforms, you presumably mean the platform code in
> > > > > Linux? A dummy clock sounds like a completely Linux-specific abstraction
> > > > > rather than a description of the hardware, and I don't see why we need
> > > > > that in the DT:
> > > > >
> > > > > * If a clock is wired up and running (as presumably the dummy clock is),
> > > > > then surely it's a fixed-clock (it's running, we and we have no control
> > > > > over it, but we presumably know its rate) and can be described as such?
> > > > >
> > > > > * If no clock is wired up, then we should be able to describe that. If a
> > > > > driver believes that a clock is required when it isn't (for some level
> > > > > of functionality), then that driver should be fixed up to support the
> > > > > clock as being optional.
> > > > >
> > > > > Am I missing something?
> > > >
> > > > I second that.
> > > >
> > > > Moreover, I don't think that device tree should deal with dummy anything.
> > > > It should be able to describe hardware that is available on given system,
> > > > not list what hardware is not available.
> > >
> > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > abstraction.
> > >
> > > I'm not advocating a dummy clock in DT. I am advocating consolidation of
> > > the implementation of a clock that does nothing into the clock core.
> > > This code could easily live in drivers/clk/clk.c instead of having
> > > everyone open-code it.
> > >
> > > As far as specifying a dummy clock in DT? I dunno. DT should describe
> > > real hardware so there isn't much use for a dummy clock.
> >
> >
> > Sorry, I misunderstood. Good to hear we're on the same page :)
> >
> > >
> > > I'm guessing one of the reasons for such a clock are drivers do not
> > > honor the clk.h api and they freak out when clk_get gives them a NULL
> > > pointer?
> >
> > I'm not sure. Sascha, could you shed some light on the matter?
>
> The original reason introducing the dummy clocks in the i.MX dtbs
> was to provide devices a clock which the driver requests but is
> not software controllable. We often have the case where the same
> devices are on several SoCs, but not on all of them all clocks have
> a bit to en/disable them.
So those clocks are always on at some fixed rate?
>
> Anyway, to accomplish this we don't need dummy clocks. We can just
> describe the real clocks.
Ok.
>
> BTW with the S/PDIF core on which not all mux inputs are connected
> to actual clocks we could also describe the unconnected inputs as
> ground clocks with rate 0. This way we describe something which
> is really there instead of dummy clocks ;)
>
> Background to why it might be a good idea to connect a ground clock
> to the unconnected input pins is that a driver has a chance to
> successfully grab all clocks. Otherwise how does the driver distinguish
> between an unconnected and an erroneous clock?
Surely the presence of a name in "clock-names" tells you that a clock is
connected, and if not listed it's not connected? If we don't have the
infrastructure for telling apart unconnected clocks from inability to
enable/configure clocks, that's a Linux issue rather than something that
should be hacked up in the dt.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-23 6:34 ` Sascha Hauer
@ 2013-08-23 12:58 ` Mark Rutland
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-23 12:58 UTC (permalink / raw)
To: Sascha Hauer
Cc: Tomasz Figa, Mike Turquette, Nicolin Chen, ian.campbell,
Pawel Moll, galak, broonie, lars, p.zabel, linuxppc-dev,
alsa-devel, devicetree, timur, rob.herring, shawn.guo, festevam,
swarren
On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > >
> > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > >
> > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > wrote:
> > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > >
> > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > wrote:
> > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > wrote:
> > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > wrote:
> > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > not
> > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > documented
> > > > > > > > > > > > > anywhere?
> > > > > > > > > > > >
> > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > >
> > > > > > > > > > > OK, thanks.
> > > > > > > > > > >
> > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > skipped clocks.
> > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > >
> > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > a generic
> > > > > > > > > > > way to specify it.
> > > > > > > > > >
> > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > have
> > > > > > > > > > bindings
> > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > simple
> > > > > > > > > > preconfigured clocks.
> > > > > > > > >
> > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > callbacks and
> > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > dummy
> > > > > > > > > regulator
> > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > clock core,
> > > > > > > > > as
> > > > > > > > > is done by the regulator core.
> > > > > > > >
> > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > code in
> > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > don't see why we need that in the DT:
> > > > > > > >
> > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > rate) and can be described as such?
> > > > > > > >
> > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > >
> > > > > > > > Am I missing something?
> > > > > > >
> > > > > > > I second that.
> > > > > > >
> > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > anything. It should be able to describe hardware that is
> > > > > > > available on given system, not list what hardware is not
> > > > > > > available.
> > > > > >
> > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > abstraction.
> > > > > >
> > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > into the clock core. This code could easily live in
> > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > >
> > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > describe
> > > > > > real hardware so there isn't much use for a dummy clock.
> > > > >
> > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > >
> > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > not
> > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > NULL
> > > > > > pointer?
> > > > >
> > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > >
> > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > was to provide devices a clock which the driver requests but is
> > > > not software controllable. We often have the case where the same
> > > > devices are on several SoCs, but not on all of them all clocks have
> > > > a bit to en/disable them.
> > > >
> > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > describe the real clocks.
> > >
> > > You could use a dummy clk for the Linux implementation, but the downside
> > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > have non-zero rates.
> > >
> > > It is probably better for you define a clock which only implements the
> > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> >
> > I doubt that rate of a dummy clock could ever change... unless it is a
> > rather smart dummy.
> >
> > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > to actual clocks we could also describe the unconnected inputs as
> > > > ground clocks with rate 0. This way we describe something which
> > > > is really there instead of dummy clocks ;)
> > >
> > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > rate of zero from the perspective of the Linux implementation.
> > >
> > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > That is not an entirely uncommon case.
> >
> > Well, how would that differ from skipping a clock from clocks list, i.e.
> > not specifying it in clock-names and clocks properties?
>
> The difference is that you can successfully grab it in your driver.
That's a driver-specific issue. The driver knows best which clocks it
can live without (if it's poking only a subset of the hardware, it may
not need some just yet, but could for extended functionality in future
when support is extended), and could assign a dummy to those clocks it
knows it doesn't need that aren't described. That doesn't need to be in
the dt, and shouldn't be, because it's OS and driver specific.
>
> >
> > > > Background to why it might be a good idea to connect a ground clock
> > > > to the unconnected input pins is that a driver has a chance to
> > > > successfully grab all clocks. Otherwise how does the driver
> > > > distinguish
> > > > between an unconnected and an erroneous clock?
> > >
> > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > based on the value returned from clk_get?
> >
> > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > clock specified, but there is a problem with it) from no clock (e.g. clock
> > not specified in DT, because it is not available on particular board).
>
> Yes, that's what I meant. To illustrate the problem for this driver:
>
> for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> sprintf(tmp, "rxtx%d", i);
> clk = devm_clk_get(&pdev->dev, tmp);
> if (IS_ERR(clk)) {
[...]
/*
* ERR_PTR(-ENOENT) returned when clock not
* present in the dt (i.e. not wired up). We can
* live without this clock, so assign a dummy
* (NULL) to simplify the rest of the code. If
* the clock is present but something else went
* wrong, we'll get a different ERR_PTR value
* and actually fail.
*/
if (clk == ERR_PTR(-ENOENT)
clk = NULL;
> }
> }
>
> This could be solved by always specifying all input clocks in the
> devicetree.
As far as I can see, the above is sufficient, and leaves the knowledge
of skippable clocks in the driver, where I believe it should be.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 12:58 ` Mark Rutland
0 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-23 12:58 UTC (permalink / raw)
To: Sascha Hauer
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, festevam, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo,
linuxppc-dev
On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > >
> > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > >
> > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > wrote:
> > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > >
> > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > wrote:
> > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > wrote:
> > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > wrote:
> > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > not
> > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > documented
> > > > > > > > > > > > > anywhere?
> > > > > > > > > > > >
> > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > >
> > > > > > > > > > > OK, thanks.
> > > > > > > > > > >
> > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > skipped clocks.
> > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > >
> > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > a generic
> > > > > > > > > > > way to specify it.
> > > > > > > > > >
> > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > have
> > > > > > > > > > bindings
> > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > simple
> > > > > > > > > > preconfigured clocks.
> > > > > > > > >
> > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > callbacks and
> > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > dummy
> > > > > > > > > regulator
> > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > clock core,
> > > > > > > > > as
> > > > > > > > > is done by the regulator core.
> > > > > > > >
> > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > code in
> > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > don't see why we need that in the DT:
> > > > > > > >
> > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > rate) and can be described as such?
> > > > > > > >
> > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > >
> > > > > > > > Am I missing something?
> > > > > > >
> > > > > > > I second that.
> > > > > > >
> > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > anything. It should be able to describe hardware that is
> > > > > > > available on given system, not list what hardware is not
> > > > > > > available.
> > > > > >
> > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > abstraction.
> > > > > >
> > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > into the clock core. This code could easily live in
> > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > >
> > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > describe
> > > > > > real hardware so there isn't much use for a dummy clock.
> > > > >
> > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > >
> > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > not
> > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > NULL
> > > > > > pointer?
> > > > >
> > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > >
> > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > was to provide devices a clock which the driver requests but is
> > > > not software controllable. We often have the case where the same
> > > > devices are on several SoCs, but not on all of them all clocks have
> > > > a bit to en/disable them.
> > > >
> > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > describe the real clocks.
> > >
> > > You could use a dummy clk for the Linux implementation, but the downside
> > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > have non-zero rates.
> > >
> > > It is probably better for you define a clock which only implements the
> > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> >
> > I doubt that rate of a dummy clock could ever change... unless it is a
> > rather smart dummy.
> >
> > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > to actual clocks we could also describe the unconnected inputs as
> > > > ground clocks with rate 0. This way we describe something which
> > > > is really there instead of dummy clocks ;)
> > >
> > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > rate of zero from the perspective of the Linux implementation.
> > >
> > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > That is not an entirely uncommon case.
> >
> > Well, how would that differ from skipping a clock from clocks list, i.e.
> > not specifying it in clock-names and clocks properties?
>
> The difference is that you can successfully grab it in your driver.
That's a driver-specific issue. The driver knows best which clocks it
can live without (if it's poking only a subset of the hardware, it may
not need some just yet, but could for extended functionality in future
when support is extended), and could assign a dummy to those clocks it
knows it doesn't need that aren't described. That doesn't need to be in
the dt, and shouldn't be, because it's OS and driver specific.
>
> >
> > > > Background to why it might be a good idea to connect a ground clock
> > > > to the unconnected input pins is that a driver has a chance to
> > > > successfully grab all clocks. Otherwise how does the driver
> > > > distinguish
> > > > between an unconnected and an erroneous clock?
> > >
> > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > based on the value returned from clk_get?
> >
> > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > clock specified, but there is a problem with it) from no clock (e.g. clock
> > not specified in DT, because it is not available on particular board).
>
> Yes, that's what I meant. To illustrate the problem for this driver:
>
> for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> sprintf(tmp, "rxtx%d", i);
> clk = devm_clk_get(&pdev->dev, tmp);
> if (IS_ERR(clk)) {
[...]
/*
* ERR_PTR(-ENOENT) returned when clock not
* present in the dt (i.e. not wired up). We can
* live without this clock, so assign a dummy
* (NULL) to simplify the rest of the code. If
* the clock is present but something else went
* wrong, we'll get a different ERR_PTR value
* and actually fail.
*/
if (clk == ERR_PTR(-ENOENT)
clk = NULL;
> }
> }
>
> This could be solved by always specifying all input clocks in the
> devicetree.
As far as I can see, the above is sufficient, and leaves the knowledge
of skippable clocks in the driver, where I believe it should be.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-23 12:58 ` Mark Rutland
(?)
@ 2013-08-23 14:01 ` Sascha Hauer
-1 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-23 14:01 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, festevam, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo,
linuxppc-dev
On Fri, Aug 23, 2013 at 01:58:15PM +0100, Mark Rutland wrote:
> On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> > On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > > >
> > > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > > >
> > > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > > wrote:
> > > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > > >
> > > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > > wrote:
> > > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > > wrote:
> > > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > > wrote:
> > > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > > not
> > > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > > documented
> > > > > > > > > > > > > > anywhere?
> > > > > > > > > > > > >
> > > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > > >
> > > > > > > > > > > > OK, thanks.
> > > > > > > > > > > >
> > > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > > skipped clocks.
> > > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > > >
> > > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > > a generic
> > > > > > > > > > > > way to specify it.
> > > > > > > > > > >
> > > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > > have
> > > > > > > > > > > bindings
> > > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > > simple
> > > > > > > > > > > preconfigured clocks.
> > > > > > > > > >
> > > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > > callbacks and
> > > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > > dummy
> > > > > > > > > > regulator
> > > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > > clock core,
> > > > > > > > > > as
> > > > > > > > > > is done by the regulator core.
> > > > > > > > >
> > > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > > code in
> > > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > > don't see why we need that in the DT:
> > > > > > > > >
> > > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > > rate) and can be described as such?
> > > > > > > > >
> > > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > > >
> > > > > > > > > Am I missing something?
> > > > > > > >
> > > > > > > > I second that.
> > > > > > > >
> > > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > > anything. It should be able to describe hardware that is
> > > > > > > > available on given system, not list what hardware is not
> > > > > > > > available.
> > > > > > >
> > > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > > abstraction.
> > > > > > >
> > > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > > into the clock core. This code could easily live in
> > > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > > >
> > > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > > describe
> > > > > > > real hardware so there isn't much use for a dummy clock.
> > > > > >
> > > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > > >
> > > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > > not
> > > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > > NULL
> > > > > > > pointer?
> > > > > >
> > > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > > >
> > > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > > was to provide devices a clock which the driver requests but is
> > > > > not software controllable. We often have the case where the same
> > > > > devices are on several SoCs, but not on all of them all clocks have
> > > > > a bit to en/disable them.
> > > > >
> > > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > > describe the real clocks.
> > > >
> > > > You could use a dummy clk for the Linux implementation, but the downside
> > > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > > have non-zero rates.
> > > >
> > > > It is probably better for you define a clock which only implements the
> > > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> > >
> > > I doubt that rate of a dummy clock could ever change... unless it is a
> > > rather smart dummy.
> > >
> > > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > > to actual clocks we could also describe the unconnected inputs as
> > > > > ground clocks with rate 0. This way we describe something which
> > > > > is really there instead of dummy clocks ;)
> > > >
> > > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > > rate of zero from the perspective of the Linux implementation.
> > > >
> > > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > > That is not an entirely uncommon case.
> > >
> > > Well, how would that differ from skipping a clock from clocks list, i.e.
> > > not specifying it in clock-names and clocks properties?
> >
> > The difference is that you can successfully grab it in your driver.
>
> That's a driver-specific issue. The driver knows best which clocks it
> can live without (if it's poking only a subset of the hardware, it may
> not need some just yet, but could for extended functionality in future
> when support is extended), and could assign a dummy to those clocks it
> knows it doesn't need that aren't described. That doesn't need to be in
> the dt, and shouldn't be, because it's OS and driver specific.
>
> >
> > >
> > > > > Background to why it might be a good idea to connect a ground clock
> > > > > to the unconnected input pins is that a driver has a chance to
> > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > distinguish
> > > > > between an unconnected and an erroneous clock?
> > > >
> > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > based on the value returned from clk_get?
> > >
> > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > not specified in DT, because it is not available on particular board).
> >
> > Yes, that's what I meant. To illustrate the problem for this driver:
> >
> > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > sprintf(tmp, "rxtx%d", i);
> > clk = devm_clk_get(&pdev->dev, tmp);
> > if (IS_ERR(clk)) {
>
> [...]
>
> /*
> * ERR_PTR(-ENOENT) returned when clock not
> * present in the dt (i.e. not wired up). We can
> * live without this clock, so assign a dummy
> * (NULL) to simplify the rest of the code. If
> * the clock is present but something else went
> * wrong, we'll get a different ERR_PTR value
> * and actually fail.
> */
> if (clk == ERR_PTR(-ENOENT)
> clk = NULL;
>
> > }
> > }
> >
> > This could be solved by always specifying all input clocks in the
> > devicetree.
>
> As far as I can see, the above is sufficient, and leaves the knowledge
> of skippable clocks in the driver, where I believe it should be.
You miss my point. Once a clock is specified in the devicetree it is no
longer optional. The driver currently can't find out whether a clock
hasn't been specified (and it's ok that it's not there) or a clock has
been specified, but some error prevents actually grabbing the clock (in
which case the driver should bail out)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 14:01 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-23 14:01 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, linuxppc-dev, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo, festevam
On Fri, Aug 23, 2013 at 01:58:15PM +0100, Mark Rutland wrote:
> On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> > On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > > >
> > > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > > >
> > > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > > wrote:
> > > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > > >
> > > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > > wrote:
> > > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > > wrote:
> > > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > > wrote:
> > > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > > not
> > > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > > documented
> > > > > > > > > > > > > > anywhere?
> > > > > > > > > > > > >
> > > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > > >
> > > > > > > > > > > > OK, thanks.
> > > > > > > > > > > >
> > > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > > skipped clocks.
> > > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > > >
> > > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > > a generic
> > > > > > > > > > > > way to specify it.
> > > > > > > > > > >
> > > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > > have
> > > > > > > > > > > bindings
> > > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > > simple
> > > > > > > > > > > preconfigured clocks.
> > > > > > > > > >
> > > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > > callbacks and
> > > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > > dummy
> > > > > > > > > > regulator
> > > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > > clock core,
> > > > > > > > > > as
> > > > > > > > > > is done by the regulator core.
> > > > > > > > >
> > > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > > code in
> > > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > > don't see why we need that in the DT:
> > > > > > > > >
> > > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > > rate) and can be described as such?
> > > > > > > > >
> > > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > > >
> > > > > > > > > Am I missing something?
> > > > > > > >
> > > > > > > > I second that.
> > > > > > > >
> > > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > > anything. It should be able to describe hardware that is
> > > > > > > > available on given system, not list what hardware is not
> > > > > > > > available.
> > > > > > >
> > > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > > abstraction.
> > > > > > >
> > > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > > into the clock core. This code could easily live in
> > > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > > >
> > > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > > describe
> > > > > > > real hardware so there isn't much use for a dummy clock.
> > > > > >
> > > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > > >
> > > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > > not
> > > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > > NULL
> > > > > > > pointer?
> > > > > >
> > > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > > >
> > > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > > was to provide devices a clock which the driver requests but is
> > > > > not software controllable. We often have the case where the same
> > > > > devices are on several SoCs, but not on all of them all clocks have
> > > > > a bit to en/disable them.
> > > > >
> > > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > > describe the real clocks.
> > > >
> > > > You could use a dummy clk for the Linux implementation, but the downside
> > > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > > have non-zero rates.
> > > >
> > > > It is probably better for you define a clock which only implements the
> > > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> > >
> > > I doubt that rate of a dummy clock could ever change... unless it is a
> > > rather smart dummy.
> > >
> > > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > > to actual clocks we could also describe the unconnected inputs as
> > > > > ground clocks with rate 0. This way we describe something which
> > > > > is really there instead of dummy clocks ;)
> > > >
> > > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > > rate of zero from the perspective of the Linux implementation.
> > > >
> > > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > > That is not an entirely uncommon case.
> > >
> > > Well, how would that differ from skipping a clock from clocks list, i.e.
> > > not specifying it in clock-names and clocks properties?
> >
> > The difference is that you can successfully grab it in your driver.
>
> That's a driver-specific issue. The driver knows best which clocks it
> can live without (if it's poking only a subset of the hardware, it may
> not need some just yet, but could for extended functionality in future
> when support is extended), and could assign a dummy to those clocks it
> knows it doesn't need that aren't described. That doesn't need to be in
> the dt, and shouldn't be, because it's OS and driver specific.
>
> >
> > >
> > > > > Background to why it might be a good idea to connect a ground clock
> > > > > to the unconnected input pins is that a driver has a chance to
> > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > distinguish
> > > > > between an unconnected and an erroneous clock?
> > > >
> > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > based on the value returned from clk_get?
> > >
> > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > not specified in DT, because it is not available on particular board).
> >
> > Yes, that's what I meant. To illustrate the problem for this driver:
> >
> > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > sprintf(tmp, "rxtx%d", i);
> > clk = devm_clk_get(&pdev->dev, tmp);
> > if (IS_ERR(clk)) {
>
> [...]
>
> /*
> * ERR_PTR(-ENOENT) returned when clock not
> * present in the dt (i.e. not wired up). We can
> * live without this clock, so assign a dummy
> * (NULL) to simplify the rest of the code. If
> * the clock is present but something else went
> * wrong, we'll get a different ERR_PTR value
> * and actually fail.
> */
> if (clk == ERR_PTR(-ENOENT)
> clk = NULL;
>
> > }
> > }
> >
> > This could be solved by always specifying all input clocks in the
> > devicetree.
>
> As far as I can see, the above is sufficient, and leaves the knowledge
> of skippable clocks in the driver, where I believe it should be.
You miss my point. Once a clock is specified in the devicetree it is no
longer optional. The driver currently can't find out whether a clock
hasn't been specified (and it's ok that it's not there) or a clock has
been specified, but some error prevents actually grabbing the clock (in
which case the driver should bail out)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 14:01 ` Sascha Hauer
0 siblings, 0 replies; 77+ messages in thread
From: Sascha Hauer @ 2013-08-23 14:01 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, linuxppc-dev, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo, festevam
On Fri, Aug 23, 2013 at 01:58:15PM +0100, Mark Rutland wrote:
> On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> > On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > > >
> > > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > > >
> > > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > > wrote:
> > > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > > >
> > > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > > wrote:
> > > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > > wrote:
> > > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > > wrote:
> > > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > > not
> > > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > > documented
> > > > > > > > > > > > > > anywhere?
> > > > > > > > > > > > >
> > > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > > >
> > > > > > > > > > > > OK, thanks.
> > > > > > > > > > > >
> > > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > > skipped clocks.
> > > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > > >
> > > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > > a generic
> > > > > > > > > > > > way to specify it.
> > > > > > > > > > >
> > > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > > have
> > > > > > > > > > > bindings
> > > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > > simple
> > > > > > > > > > > preconfigured clocks.
> > > > > > > > > >
> > > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > > callbacks and
> > > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > > dummy
> > > > > > > > > > regulator
> > > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > > clock core,
> > > > > > > > > > as
> > > > > > > > > > is done by the regulator core.
> > > > > > > > >
> > > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > > code in
> > > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > > don't see why we need that in the DT:
> > > > > > > > >
> > > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > > rate) and can be described as such?
> > > > > > > > >
> > > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > > >
> > > > > > > > > Am I missing something?
> > > > > > > >
> > > > > > > > I second that.
> > > > > > > >
> > > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > > anything. It should be able to describe hardware that is
> > > > > > > > available on given system, not list what hardware is not
> > > > > > > > available.
> > > > > > >
> > > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > > abstraction.
> > > > > > >
> > > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > > into the clock core. This code could easily live in
> > > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > > >
> > > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > > describe
> > > > > > > real hardware so there isn't much use for a dummy clock.
> > > > > >
> > > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > > >
> > > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > > not
> > > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > > NULL
> > > > > > > pointer?
> > > > > >
> > > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > > >
> > > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > > was to provide devices a clock which the driver requests but is
> > > > > not software controllable. We often have the case where the same
> > > > > devices are on several SoCs, but not on all of them all clocks have
> > > > > a bit to en/disable them.
> > > > >
> > > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > > describe the real clocks.
> > > >
> > > > You could use a dummy clk for the Linux implementation, but the downside
> > > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > > have non-zero rates.
> > > >
> > > > It is probably better for you define a clock which only implements the
> > > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> > >
> > > I doubt that rate of a dummy clock could ever change... unless it is a
> > > rather smart dummy.
> > >
> > > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > > to actual clocks we could also describe the unconnected inputs as
> > > > > ground clocks with rate 0. This way we describe something which
> > > > > is really there instead of dummy clocks ;)
> > > >
> > > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > > rate of zero from the perspective of the Linux implementation.
> > > >
> > > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > > That is not an entirely uncommon case.
> > >
> > > Well, how would that differ from skipping a clock from clocks list, i.e.
> > > not specifying it in clock-names and clocks properties?
> >
> > The difference is that you can successfully grab it in your driver.
>
> That's a driver-specific issue. The driver knows best which clocks it
> can live without (if it's poking only a subset of the hardware, it may
> not need some just yet, but could for extended functionality in future
> when support is extended), and could assign a dummy to those clocks it
> knows it doesn't need that aren't described. That doesn't need to be in
> the dt, and shouldn't be, because it's OS and driver specific.
>
> >
> > >
> > > > > Background to why it might be a good idea to connect a ground clock
> > > > > to the unconnected input pins is that a driver has a chance to
> > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > distinguish
> > > > > between an unconnected and an erroneous clock?
> > > >
> > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > based on the value returned from clk_get?
> > >
> > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > not specified in DT, because it is not available on particular board).
> >
> > Yes, that's what I meant. To illustrate the problem for this driver:
> >
> > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > sprintf(tmp, "rxtx%d", i);
> > clk = devm_clk_get(&pdev->dev, tmp);
> > if (IS_ERR(clk)) {
>
> [...]
>
> /*
> * ERR_PTR(-ENOENT) returned when clock not
> * present in the dt (i.e. not wired up). We can
> * live without this clock, so assign a dummy
> * (NULL) to simplify the rest of the code. If
> * the clock is present but something else went
> * wrong, we'll get a different ERR_PTR value
> * and actually fail.
> */
> if (clk == ERR_PTR(-ENOENT)
> clk = NULL;
>
> > }
> > }
> >
> > This could be solved by always specifying all input clocks in the
> > devicetree.
>
> As far as I can see, the above is sufficient, and leaves the knowledge
> of skippable clocks in the driver, where I believe it should be.
You miss my point. Once a clock is specified in the devicetree it is no
longer optional. The driver currently can't find out whether a clock
hasn't been specified (and it's ok that it's not there) or a clock has
been specified, but some error prevents actually grabbing the clock (in
which case the driver should bail out)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-23 14:01 ` Sascha Hauer
@ 2013-08-23 14:57 ` Mark Rutland
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-23 14:57 UTC (permalink / raw)
To: Sascha Hauer
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, festevam, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo,
linuxppc-dev
[trimming a bit of useless context]
> > > > > > Background to why it might be a good idea to connect a ground clock
> > > > > > to the unconnected input pins is that a driver has a chance to
> > > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > > distinguish
> > > > > > between an unconnected and an erroneous clock?
> > > > >
> > > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > > based on the value returned from clk_get?
> > > >
> > > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > > not specified in DT, because it is not available on particular board).
> > >
> > > Yes, that's what I meant. To illustrate the problem for this driver:
> > >
> > > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > > sprintf(tmp, "rxtx%d", i);
> > > clk = devm_clk_get(&pdev->dev, tmp);
> > > if (IS_ERR(clk)) {
> >
> > [...]
> >
> > /*
> > * ERR_PTR(-ENOENT) returned when clock not
> > * present in the dt (i.e. not wired up). We can
> > * live without this clock, so assign a dummy
> > * (NULL) to simplify the rest of the code. If
> > * the clock is present but something else went
> > * wrong, we'll get a different ERR_PTR value
> > * and actually fail.
> > */
> > if (clk == ERR_PTR(-ENOENT)
> > clk = NULL;
> >
> > > }
> > > }
> > >
> > > This could be solved by always specifying all input clocks in the
> > > devicetree.
> >
> > As far as I can see, the above is sufficient, and leaves the knowledge
> > of skippable clocks in the driver, where I believe it should be.
>
> You miss my point. Once a clock is specified in the devicetree it is no
> longer optional. The driver currently can't find out whether a clock
> hasn't been specified (and it's ok that it's not there) or a clock has
> been specified, but some error prevents actually grabbing the clock (in
> which case the driver should bail out)
Unless I've misunderstood, that's exactly what I was trying to implement
above. As I understand it, what we want is:
* If a clock is not specified in the DT, but it's a clock that we know
we can live without if not wired up, then continue along with a dummy
clock (NULL). This could be changed to a different dummy, what exactly
is needed is driver-specific.
* If a clock is not specified in the DT, but it's *not* an optional
clock, then we must fail. Whether or not a clock is optional is
knowledge only the driver can have.
* If a clock is specified in the DT, but we can't get it for some
reason, fail.
* If a clock is specified in the DT, and we get it, use it.
I see we might also get PTR_ERR(-ENOENT) indirectly from
__of_parse_phandle_with_args, if the "clocks" property isn't present
(but clock-names is), or we're given the empty phandle. The empty
phandle case is arguable, but it would be possible to add a check for
the clocks property in of_clk_get_by_name early on where we could return
-EINVAL to prevent that being a problem.
Otherwise, it's trivial to add a function to explicitly test for this
case (see below). I don't see that we need to leak what is a Linux issue
into the dt.
Thanks,
Mark.
---->8----
>From f0d46f36426ded4ba3609d79664888852f9925e2 Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Fri, 23 Aug 2013 15:46:33 +0100
Subject: [PATCH] clk: add of_clk_is_specified
There's currently no way to perfectly distinguish between an
of_clk_get_by_name that failed because a clock was not provided in
clock-names, or for some other reason (e.g. the clocks property itself
was missing). This is problematic for drivers for some pieces of
hardware that have optional clocks -- those which must be used if wired,
but may not be wired in all cases.
This patch adds a new function of_clk_is_specified, which may be used to
distinguish these cases.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clk/clkdev.c | 11 +++++++++++
include/linux/clk.h | 5 +++++
2 files changed, 16 insertions(+)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..7fdeca9 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -91,6 +91,17 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
return clk;
}
EXPORT_SYMBOL(of_clk_get_by_name);
+
+/**
+ *
+ * of_clk_is_specified - Test if a clock was provided by name in a device node
+ * @np: pointer to the clock consumer node
+ * @name: name of the consumer's clock input. Not NULL.
+ */
+bool of_clk_is_specified(struct device_node *np, const char *name)
+{
+ return of_property_match_string(np, "clock-names", name) >= 0;
+}
#endif
/*
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 9a6d045..bf44d94 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -368,6 +368,7 @@ struct of_phandle_args;
struct clk *of_clk_get(struct device_node *np, int index);
struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);
+bool of_clk_is_specified(struct device_node *np, const char *name);
#else
static inline struct clk *of_clk_get(struct device_node *np, int index)
{
@@ -378,6 +379,10 @@ static inline struct clk *of_clk_get_by_name(struct device_node *np,
{
return ERR_PTR(-ENOENT);
}
+static bool of_clk_is_specified(struct device_node *np, const char *name)
+{
+ return false;
+}
#endif
#endif
--
1.8.1.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 14:57 ` Mark Rutland
0 siblings, 0 replies; 77+ messages in thread
From: Mark Rutland @ 2013-08-23 14:57 UTC (permalink / raw)
To: Sascha Hauer
Cc: devicetree, alsa-devel, lars, Mike Turquette, ian.campbell,
Pawel Moll, swarren, linuxppc-dev, Nicolin Chen, Tomasz Figa,
rob.herring, timur, broonie, p.zabel, galak, shawn.guo, festevam
[trimming a bit of useless context]
> > > > > > Background to why it might be a good idea to connect a ground clock
> > > > > > to the unconnected input pins is that a driver has a chance to
> > > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > > distinguish
> > > > > > between an unconnected and an erroneous clock?
> > > > >
> > > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > > based on the value returned from clk_get?
> > > >
> > > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > > not specified in DT, because it is not available on particular board).
> > >
> > > Yes, that's what I meant. To illustrate the problem for this driver:
> > >
> > > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > > sprintf(tmp, "rxtx%d", i);
> > > clk = devm_clk_get(&pdev->dev, tmp);
> > > if (IS_ERR(clk)) {
> >
> > [...]
> >
> > /*
> > * ERR_PTR(-ENOENT) returned when clock not
> > * present in the dt (i.e. not wired up). We can
> > * live without this clock, so assign a dummy
> > * (NULL) to simplify the rest of the code. If
> > * the clock is present but something else went
> > * wrong, we'll get a different ERR_PTR value
> > * and actually fail.
> > */
> > if (clk == ERR_PTR(-ENOENT)
> > clk = NULL;
> >
> > > }
> > > }
> > >
> > > This could be solved by always specifying all input clocks in the
> > > devicetree.
> >
> > As far as I can see, the above is sufficient, and leaves the knowledge
> > of skippable clocks in the driver, where I believe it should be.
>
> You miss my point. Once a clock is specified in the devicetree it is no
> longer optional. The driver currently can't find out whether a clock
> hasn't been specified (and it's ok that it's not there) or a clock has
> been specified, but some error prevents actually grabbing the clock (in
> which case the driver should bail out)
Unless I've misunderstood, that's exactly what I was trying to implement
above. As I understand it, what we want is:
* If a clock is not specified in the DT, but it's a clock that we know
we can live without if not wired up, then continue along with a dummy
clock (NULL). This could be changed to a different dummy, what exactly
is needed is driver-specific.
* If a clock is not specified in the DT, but it's *not* an optional
clock, then we must fail. Whether or not a clock is optional is
knowledge only the driver can have.
* If a clock is specified in the DT, but we can't get it for some
reason, fail.
* If a clock is specified in the DT, and we get it, use it.
I see we might also get PTR_ERR(-ENOENT) indirectly from
__of_parse_phandle_with_args, if the "clocks" property isn't present
(but clock-names is), or we're given the empty phandle. The empty
phandle case is arguable, but it would be possible to add a check for
the clocks property in of_clk_get_by_name early on where we could return
-EINVAL to prevent that being a problem.
Otherwise, it's trivial to add a function to explicitly test for this
case (see below). I don't see that we need to leak what is a Linux issue
into the dt.
Thanks,
Mark.
---->8----
>From f0d46f36426ded4ba3609d79664888852f9925e2 Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Fri, 23 Aug 2013 15:46:33 +0100
Subject: [PATCH] clk: add of_clk_is_specified
There's currently no way to perfectly distinguish between an
of_clk_get_by_name that failed because a clock was not provided in
clock-names, or for some other reason (e.g. the clocks property itself
was missing). This is problematic for drivers for some pieces of
hardware that have optional clocks -- those which must be used if wired,
but may not be wired in all cases.
This patch adds a new function of_clk_is_specified, which may be used to
distinguish these cases.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clk/clkdev.c | 11 +++++++++++
include/linux/clk.h | 5 +++++
2 files changed, 16 insertions(+)
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 442a313..7fdeca9 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -91,6 +91,17 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
return clk;
}
EXPORT_SYMBOL(of_clk_get_by_name);
+
+/**
+ *
+ * of_clk_is_specified - Test if a clock was provided by name in a device node
+ * @np: pointer to the clock consumer node
+ * @name: name of the consumer's clock input. Not NULL.
+ */
+bool of_clk_is_specified(struct device_node *np, const char *name)
+{
+ return of_property_match_string(np, "clock-names", name) >= 0;
+}
#endif
/*
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 9a6d045..bf44d94 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -368,6 +368,7 @@ struct of_phandle_args;
struct clk *of_clk_get(struct device_node *np, int index);
struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);
+bool of_clk_is_specified(struct device_node *np, const char *name);
#else
static inline struct clk *of_clk_get(struct device_node *np, int index)
{
@@ -378,6 +379,10 @@ static inline struct clk *of_clk_get_by_name(struct device_node *np,
{
return ERR_PTR(-ENOENT);
}
+static bool of_clk_is_specified(struct device_node *np, const char *name)
+{
+ return false;
+}
#endif
#endif
--
1.8.1.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-23 14:01 ` Sascha Hauer
(?)
@ 2013-08-23 21:41 ` Mike Turquette
-1 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-23 21:41 UTC (permalink / raw)
To: Sascha Hauer, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
festevam, Nicolin Chen, Tomasz Figa, rob.herring, timur, broonie,
p.zabel, galak, shawn.guo, linuxppc-dev
Quoting Sascha Hauer (2013-08-23 07:01:28)
> On Fri, Aug 23, 2013 at 01:58:15PM +0100, Mark Rutland wrote:
> > On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> > > On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > > > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > > > >
> > > > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > > > >
> > > > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > > > wrote:
> > > > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > > > >
> > > > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > > > wrote:
> > > > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > > > wrote:
> > > > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > > > wrote:
> > > > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > > > not
> > > > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > > > documented
> > > > > > > > > > > > > > > anywhere?
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > > > >
> > > > > > > > > > > > > OK, thanks.
> > > > > > > > > > > > >
> > > > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > > > skipped clocks.
> > > > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > > > >
> > > > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > > > a generic
> > > > > > > > > > > > > way to specify it.
> > > > > > > > > > > >
> > > > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > > > have
> > > > > > > > > > > > bindings
> > > > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > > > simple
> > > > > > > > > > > > preconfigured clocks.
> > > > > > > > > > >
> > > > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > > > callbacks and
> > > > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > > > dummy
> > > > > > > > > > > regulator
> > > > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > > > clock core,
> > > > > > > > > > > as
> > > > > > > > > > > is done by the regulator core.
> > > > > > > > > >
> > > > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > > > code in
> > > > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > > > don't see why we need that in the DT:
> > > > > > > > > >
> > > > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > > > rate) and can be described as such?
> > > > > > > > > >
> > > > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > > > >
> > > > > > > > > > Am I missing something?
> > > > > > > > >
> > > > > > > > > I second that.
> > > > > > > > >
> > > > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > > > anything. It should be able to describe hardware that is
> > > > > > > > > available on given system, not list what hardware is not
> > > > > > > > > available.
> > > > > > > >
> > > > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > > > abstraction.
> > > > > > > >
> > > > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > > > into the clock core. This code could easily live in
> > > > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > > > >
> > > > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > > > describe
> > > > > > > > real hardware so there isn't much use for a dummy clock.
> > > > > > >
> > > > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > > > >
> > > > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > > > not
> > > > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > > > NULL
> > > > > > > > pointer?
> > > > > > >
> > > > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > > > >
> > > > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > > > was to provide devices a clock which the driver requests but is
> > > > > > not software controllable. We often have the case where the same
> > > > > > devices are on several SoCs, but not on all of them all clocks have
> > > > > > a bit to en/disable them.
> > > > > >
> > > > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > > > describe the real clocks.
> > > > >
> > > > > You could use a dummy clk for the Linux implementation, but the downside
> > > > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > > > have non-zero rates.
> > > > >
> > > > > It is probably better for you define a clock which only implements the
> > > > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> > > >
> > > > I doubt that rate of a dummy clock could ever change... unless it is a
> > > > rather smart dummy.
> > > >
> > > > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > > > to actual clocks we could also describe the unconnected inputs as
> > > > > > ground clocks with rate 0. This way we describe something which
> > > > > > is really there instead of dummy clocks ;)
> > > > >
> > > > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > > > rate of zero from the perspective of the Linux implementation.
> > > > >
> > > > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > > > That is not an entirely uncommon case.
> > > >
> > > > Well, how would that differ from skipping a clock from clocks list, i.e.
> > > > not specifying it in clock-names and clocks properties?
> > >
> > > The difference is that you can successfully grab it in your driver.
> >
> > That's a driver-specific issue. The driver knows best which clocks it
> > can live without (if it's poking only a subset of the hardware, it may
> > not need some just yet, but could for extended functionality in future
> > when support is extended), and could assign a dummy to those clocks it
> > knows it doesn't need that aren't described. That doesn't need to be in
> > the dt, and shouldn't be, because it's OS and driver specific.
> >
> > >
> > > >
> > > > > > Background to why it might be a good idea to connect a ground clock
> > > > > > to the unconnected input pins is that a driver has a chance to
> > > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > > distinguish
> > > > > > between an unconnected and an erroneous clock?
> > > > >
> > > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > > based on the value returned from clk_get?
> > > >
> > > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > > not specified in DT, because it is not available on particular board).
> > >
> > > Yes, that's what I meant. To illustrate the problem for this driver:
> > >
> > > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > > sprintf(tmp, "rxtx%d", i);
> > > clk = devm_clk_get(&pdev->dev, tmp);
> > > if (IS_ERR(clk)) {
> >
> > [...]
> >
> > /*
> > * ERR_PTR(-ENOENT) returned when clock not
> > * present in the dt (i.e. not wired up). We can
> > * live without this clock, so assign a dummy
> > * (NULL) to simplify the rest of the code. If
> > * the clock is present but something else went
> > * wrong, we'll get a different ERR_PTR value
> > * and actually fail.
> > */
> > if (clk == ERR_PTR(-ENOENT)
> > clk = NULL;
> >
> > > }
> > > }
> > >
> > > This could be solved by always specifying all input clocks in the
> > > devicetree.
> >
> > As far as I can see, the above is sufficient, and leaves the knowledge
> > of skippable clocks in the driver, where I believe it should be.
>
> You miss my point. Once a clock is specified in the devicetree it is no
> longer optional. The driver currently can't find out whether a clock
> hasn't been specified (and it's ok that it's not there) or a clock has
> been specified, but some error prevents actually grabbing the clock (in
> which case the driver should bail out)
Seems like the regulator framework is solving this with the new
regulator_get_optional() call. This leaves the
optional-versus-not-optional logic up to the driver.
Regards,
Mike
>
> Sascha
>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 21:41 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-23 21:41 UTC (permalink / raw)
To: Sascha Hauer, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
linuxppc-dev, Nicolin Chen, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, festevam
Quoting Sascha Hauer (2013-08-23 07:01:28)
> On Fri, Aug 23, 2013 at 01:58:15PM +0100, Mark Rutland wrote:
> > On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> > > On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > > > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > > > >
> > > > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrote:
> > > > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > > > >
> > > > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrote:
> > > > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquette
> > > > wrote:
> > > > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > > > >
> > > > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Figa
> > > > wrote:
> > > > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hauer
> > > > wrote:
> > > > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomasz Figa
> > > > wrote:
> > > > > > > > > > > > > > > > > > Also I would make this option required. Use a
> > > > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > > > inputs that are grounded for a specific SoC.
> > > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > > Some clocks are not from CCM and we haven't
> > > > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > > > so in most cases we can't provide a phandle for
> > > > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > > > looks more flexible to me and a default one is
> > > > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be used for
> > > > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > > > not
> > > > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > > > documented
> > > > > > > > > > > > > > > anywhere?
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > This is how all i.MX clock bindings currently are. See
> > > > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-clock.txt
> > > > > > > > > > > > >
> > > > > > > > > > > > > OK, thanks.
> > > > > > > > > > > > >
> > > > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > > > skipped clocks.
> > > > > > > > > > > > > I think we want some consistency on this, don't we?
> > > > > > > > > > > > >
> > > > > > > > > > > > > If we really need a dummy clock, then we might also want
> > > > > > > > > > > > > a generic
> > > > > > > > > > > > > way to specify it.
> > > > > > > > > > > >
> > > > > > > > > > > > What do we actually mean by a "dummy clock"? We already
> > > > > > > > > > > > have
> > > > > > > > > > > > bindings
> > > > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > > > simple
> > > > > > > > > > > > preconfigured clocks.
> > > > > > > > > > >
> > > > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > > > callbacks and
> > > > > > > > > > > basically doesn't do anything. This is analogous to the
> > > > > > > > > > > dummy
> > > > > > > > > > > regulator
> > > > > > > > > > > implementation. A central one could be registered by the
> > > > > > > > > > > clock core,
> > > > > > > > > > > as
> > > > > > > > > > > is done by the regulator core.
> > > > > > > > > >
> > > > > > > > > > When you say some platforms, you presumably mean the platform
> > > > > > > > > > code in
> > > > > > > > > > Linux? A dummy clock sounds like a completely Linux-specific
> > > > > > > > > > abstraction rather than a description of the hardware, and I
> > > > > > > > > > don't see why we need that in the DT:
> > > > > > > > > >
> > > > > > > > > > * If a clock is wired up and running (as presumably the dummy
> > > > > > > > > > clock is), then surely it's a fixed-clock (it's running, we
> > > > > > > > > > and we have no control over it, but we presumably know its
> > > > > > > > > > rate) and can be described as such?
> > > > > > > > > >
> > > > > > > > > > * If no clock is wired up, then we should be able to describe
> > > > > > > > > > that. If a driver believes that a clock is required when it
> > > > > > > > > > isn't (for some level of functionality), then that driver
> > > > > > > > > > should be fixed up to support the clock as being optional.
> > > > > > > > > >
> > > > > > > > > > Am I missing something?
> > > > > > > > >
> > > > > > > > > I second that.
> > > > > > > > >
> > > > > > > > > Moreover, I don't think that device tree should deal with dummy
> > > > > > > > > anything. It should be able to describe hardware that is
> > > > > > > > > available on given system, not list what hardware is not
> > > > > > > > > available.
> > > > > > > >
> > > > > > > > I wasn't clear. The dummy clock IS a completely Linux-specific
> > > > > > > > abstraction.
> > > > > > > >
> > > > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > > > consolidation of the implementation of a clock that does nothing
> > > > > > > > into the clock core. This code could easily live in
> > > > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > > > >
> > > > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > > > describe
> > > > > > > > real hardware so there isn't much use for a dummy clock.
> > > > > > >
> > > > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > > > >
> > > > > > > > I'm guessing one of the reasons for such a clock are drivers do
> > > > > > > > not
> > > > > > > > honor the clk.h api and they freak out when clk_get gives them a
> > > > > > > > NULL
> > > > > > > > pointer?
> > > > > > >
> > > > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > > > >
> > > > > > The original reason introducing the dummy clocks in the i.MX dtbs
> > > > > > was to provide devices a clock which the driver requests but is
> > > > > > not software controllable. We often have the case where the same
> > > > > > devices are on several SoCs, but not on all of them all clocks have
> > > > > > a bit to en/disable them.
> > > > > >
> > > > > > Anyway, to accomplish this we don't need dummy clocks. We can just
> > > > > > describe the real clocks.
> > > > >
> > > > > You could use a dummy clk for the Linux implementation, but the downside
> > > > > is that a dummy clock has a rate of 0 always and a your clocks likely
> > > > > have non-zero rates.
> > > > >
> > > > > It is probably better for you define a clock which only implements the
> > > > > .recalc_rate callback. If the rate of this clock changes without Linux
> > > > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> > > >
> > > > I doubt that rate of a dummy clock could ever change... unless it is a
> > > > rather smart dummy.
> > > >
> > > > > > BTW with the S/PDIF core on which not all mux inputs are connected
> > > > > > to actual clocks we could also describe the unconnected inputs as
> > > > > > ground clocks with rate 0. This way we describe something which
> > > > > > is really there instead of dummy clocks ;)
> > > > >
> > > > > Again you could use a dummy clock for this OR a fixed-rate clock with a
> > > > > rate of zero from the perspective of the Linux implementation.
> > > > >
> > > > > Do you think it worthwhile to have a DT binding for a grounded clock?
> > > > > That is not an entirely uncommon case.
> > > >
> > > > Well, how would that differ from skipping a clock from clocks list, i.e.
> > > > not specifying it in clock-names and clocks properties?
> > >
> > > The difference is that you can successfully grab it in your driver.
> >
> > That's a driver-specific issue. The driver knows best which clocks it
> > can live without (if it's poking only a subset of the hardware, it may
> > not need some just yet, but could for extended functionality in future
> > when support is extended), and could assign a dummy to those clocks it
> > knows it doesn't need that aren't described. That doesn't need to be in
> > the dt, and shouldn't be, because it's OS and driver specific.
> >
> > >
> > > >
> > > > > > Background to why it might be a good idea to connect a ground clock
> > > > > > to the unconnected input pins is that a driver has a chance to
> > > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > > distinguish
> > > > > > between an unconnected and an erroneous clock?
> > > > >
> > > > > Sorry, I don't follow this last question. Do you mean how to distinguish
> > > > > based on the value returned from clk_get?
> > > >
> > > > Hmm, in theory, a driver could want to distinguish an error case (e.g.
> > > > clock specified, but there is a problem with it) from no clock (e.g. clock
> > > > not specified in DT, because it is not available on particular board).
> > >
> > > Yes, that's what I meant. To illustrate the problem for this driver:
> > >
> > > for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
> > > sprintf(tmp, "rxtx%d", i);
> > > clk = devm_clk_get(&pdev->dev, tmp);
> > > if (IS_ERR(clk)) {
> >
> > [...]
> >
> > /*
> > * ERR_PTR(-ENOENT) returned when clock not
> > * present in the dt (i.e. not wired up). We can
> > * live without this clock, so assign a dummy
> > * (NULL) to simplify the rest of the code. If
> > * the clock is present but something else went
> > * wrong, we'll get a different ERR_PTR value
> > * and actually fail.
> > */
> > if (clk == ERR_PTR(-ENOENT)
> > clk = NULL;
> >
> > > }
> > > }
> > >
> > > This could be solved by always specifying all input clocks in the
> > > devicetree.
> >
> > As far as I can see, the above is sufficient, and leaves the knowledge
> > of skippable clocks in the driver, where I believe it should be.
>
> You miss my point. Once a clock is specified in the devicetree it is no
> longer optional. The driver currently can't find out whether a clock
> hasn't been specified (and it's ok that it's not there) or a clock has
> been specified, but some error prevents actually grabbing the clock (in
> which case the driver should bail out)
Seems like the regulator framework is solving this with the new
regulator_get_optional() call. This leaves the
optional-versus-not-optional logic up to the driver.
Regards,
Mike
>
> Sascha
>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-23 21:41 ` Mike Turquette
0 siblings, 0 replies; 77+ messages in thread
From: Mike Turquette @ 2013-08-23 21:41 UTC (permalink / raw)
To: Sascha Hauer, Mark Rutland
Cc: devicetree, alsa-devel, lars, ian.campbell, Pawel Moll, swarren,
linuxppc-dev, Nicolin Chen, Tomasz Figa, rob.herring, timur,
broonie, p.zabel, galak, shawn.guo, festevam
Quoting Sascha Hauer (2013-08-23 07:01:28)
> On Fri, Aug 23, 2013 at 01:58:15PM +0100, Mark Rutland wrote:
> > On Fri, Aug 23, 2013 at 07:34:21AM +0100, Sascha Hauer wrote:
> > > On Fri, Aug 23, 2013 at 12:49:19AM +0200, Tomasz Figa wrote:
> > > > On Thursday 22 of August 2013 15:43:31 Mike Turquette wrote:
> > > > > Quoting Sascha Hauer (2013-08-22 14:00:35)
> > > > > =
> > > > > > On Thu, Aug 22, 2013 at 01:09:31PM +0100, Mark Rutland wrote:
> > > > > > > On Thu, Aug 22, 2013 at 08:19:10AM +0100, Mike Turquette wrot=
e:
> > > > > > > > Quoting Tomasz Figa (2013-08-21 14:34:55)
> > > > > > > > =
> > > > > > > > > On Wednesday 21 of August 2013 09:50:15 Mark Rutland wrot=
e:
> > > > > > > > > > On Tue, Aug 20, 2013 at 01:06:25AM +0100, Mike Turquett=
e =
> > > > wrote:
> > > > > > > > > > > Quoting Mark Rutland (2013-08-19 02:35:43)
> > > > > > > > > > > =
> > > > > > > > > > > > On Sat, Aug 17, 2013 at 04:17:18PM +0100, Tomasz Fi=
ga =
> > > > wrote:
> > > > > > > > > > > > > On Saturday 17 of August 2013 16:53:16 Sascha Hau=
er =
> > > > wrote:
> > > > > > > > > > > > > > On Sat, Aug 17, 2013 at 02:28:04PM +0200, Tomas=
z Figa =
> > > > wrote:
> > > > > > > > > > > > > > > > > > Also I would make this option required.=
Use a
> > > > > > > > > > > > > > > > > > dummy
> > > > > > > > > > > > > > > > > > clock for
> > > > > > > > > > > > > > > > > > mux
> > > > > > > > > > > > > > > > > > inputs that are grounded for a specific=
SoC.
> > > > > > > > > > > > > > > > > =
> > > > > > > > > > > > > > > > > Some clocks are not from CCM and we haven=
't
> > > > > > > > > > > > > > > > > defined in
> > > > > > > > > > > > > > > > > imx6q-clk.txt,
> > > > > > > > > > > > > > > > > so in most cases we can't provide a phand=
le for
> > > > > > > > > > > > > > > > > them, eg:
> > > > > > > > > > > > > > > > > spdif_ext.
> > > > > > > > > > > > > > > > > I think it's a bit hard to force it to be
> > > > > > > > > > > > > > > > > 'required'. An
> > > > > > > > > > > > > > > > > 'optional'
> > > > > > > > > > > > > > > > > looks more flexible to me and a default o=
ne is
> > > > > > > > > > > > > > > > > ensured
> > > > > > > > > > > > > > > > > even if
> > > > > > > > > > > > > > > > > it's
> > > > > > > > > > > > > > > > > missing.
> > > > > > > > > > > > > > > > =
> > > > > > > > > > > > > > > > <&clks 0> is the dummy clock. This can be u=
sed for
> > > > > > > > > > > > > > > > all input
> > > > > > > > > > > > > > > > clocks
> > > > > > > > > > > > > > > > not
> > > > > > > > > > > > > > > > defined by the SoC.
> > > > > > > > > > > > > > > =
> > > > > > > > > > > > > > > Where does this assumption come from? Is it
> > > > > > > > > > > > > > > documented
> > > > > > > > > > > > > > > anywhere?
> > > > > > > > > > > > > > =
> > > > > > > > > > > > > > This is how all i.MX clock bindings currently a=
re. See
> > > > > > > > > > > > > > Documentation/devicetree/bindings/clock/imx*-cl=
ock.txt
> > > > > > > > > > > > > =
> > > > > > > > > > > > > OK, thanks.
> > > > > > > > > > > > > =
> > > > > > > > > > > > > I guess we need some discussion on dummy clocks vs
> > > > > > > > > > > > > skipped clocks.
> > > > > > > > > > > > > I think we want some consistency on this, don't w=
e?
> > > > > > > > > > > > > =
> > > > > > > > > > > > > If we really need a dummy clock, then we might al=
so want
> > > > > > > > > > > > > a generic
> > > > > > > > > > > > > way to specify it.
> > > > > > > > > > > > =
> > > > > > > > > > > > What do we actually mean by a "dummy clock"? We alr=
eady
> > > > > > > > > > > > have
> > > > > > > > > > > > bindings
> > > > > > > > > > > > for "fixed-clock" and co friends describe relatively
> > > > > > > > > > > > simple
> > > > > > > > > > > > preconfigured clocks.
> > > > > > > > > > > =
> > > > > > > > > > > Some platforms have a fake clock which defines noops
> > > > > > > > > > > callbacks and
> > > > > > > > > > > basically doesn't do anything. This is analogous to t=
he
> > > > > > > > > > > dummy
> > > > > > > > > > > regulator
> > > > > > > > > > > implementation. A central one could be registered by =
the
> > > > > > > > > > > clock core,
> > > > > > > > > > > as
> > > > > > > > > > > is done by the regulator core.
> > > > > > > > > > =
> > > > > > > > > > When you say some platforms, you presumably mean the pl=
atform
> > > > > > > > > > code in
> > > > > > > > > > Linux? A dummy clock sounds like a completely Linux-spe=
cific
> > > > > > > > > > abstraction rather than a description of the hardware, =
and I
> > > > > > > > > > don't see why we need that in the DT:
> > > > > > > > > > =
> > > > > > > > > > * If a clock is wired up and running (as presumably the=
dummy
> > > > > > > > > > clock is), then surely it's a fixed-clock (it's running=
, we
> > > > > > > > > > and we have no control over it, but we presumably know =
its
> > > > > > > > > > rate) and can be described as such?
> > > > > > > > > > =
> > > > > > > > > > * If no clock is wired up, then we should be able to de=
scribe
> > > > > > > > > > that. If a driver believes that a clock is required whe=
n it
> > > > > > > > > > isn't (for some level of functionality), then that driv=
er
> > > > > > > > > > should be fixed up to support the clock as being option=
al.
> > > > > > > > > > =
> > > > > > > > > > Am I missing something?
> > > > > > > > > =
> > > > > > > > > I second that.
> > > > > > > > > =
> > > > > > > > > Moreover, I don't think that device tree should deal with=
dummy
> > > > > > > > > anything. It should be able to describe hardware that is
> > > > > > > > > available on given system, not list what hardware is not
> > > > > > > > > available.
> > > > > > > > =
> > > > > > > > I wasn't clear. The dummy clock IS a completely Linux-speci=
fic
> > > > > > > > abstraction.
> > > > > > > > =
> > > > > > > > I'm not advocating a dummy clock in DT. I am advocating
> > > > > > > > consolidation of the implementation of a clock that does no=
thing
> > > > > > > > into the clock core. This code could easily live in
> > > > > > > > drivers/clk/clk.c instead of having everyone open-code it.
> > > > > > > > =
> > > > > > > > As far as specifying a dummy clock in DT? I dunno. DT should
> > > > > > > > describe
> > > > > > > > real hardware so there isn't much use for a dummy clock.
> > > > > > > =
> > > > > > > Sorry, I misunderstood. Good to hear we're on the same page :)
> > > > > > > =
> > > > > > > > I'm guessing one of the reasons for such a clock are driver=
s do
> > > > > > > > not
> > > > > > > > honor the clk.h api and they freak out when clk_get gives t=
hem a
> > > > > > > > NULL
> > > > > > > > pointer?
> > > > > > > =
> > > > > > > I'm not sure. Sascha, could you shed some light on the matter?
> > > > > > =
> > > > > > The original reason introducing the dummy clocks in the i.MX dt=
bs
> > > > > > was to provide devices a clock which the driver requests but is
> > > > > > not software controllable. We often have the case where the same
> > > > > > devices are on several SoCs, but not on all of them all clocks =
have
> > > > > > a bit to en/disable them.
> > > > > > =
> > > > > > Anyway, to accomplish this we don't need dummy clocks. We can j=
ust
> > > > > > describe the real clocks.
> > > > > =
> > > > > You could use a dummy clk for the Linux implementation, but the d=
ownside
> > > > > is that a dummy clock has a rate of 0 always and a your clocks li=
kely
> > > > > have non-zero rates.
> > > > > =
> > > > > It is probably better for you define a clock which only implement=
s the
> > > > > .recalc_rate callback. If the rate of this clock changes without =
Linux
> > > > > having knowledge of it you can use the CLK_GET_RATE_NOCACHE flag.
> > > > =
> > > > I doubt that rate of a dummy clock could ever change... unless it i=
s a =
> > > > rather smart dummy.
> > > > =
> > > > > > BTW with the S/PDIF core on which not all mux inputs are connec=
ted
> > > > > > to actual clocks we could also describe the unconnected inputs =
as
> > > > > > ground clocks with rate 0. This way we describe something which
> > > > > > is really there instead of dummy clocks ;)
> > > > > =
> > > > > Again you could use a dummy clock for this OR a fixed-rate clock =
with a
> > > > > rate of zero from the perspective of the Linux implementation.
> > > > > =
> > > > > Do you think it worthwhile to have a DT binding for a grounded cl=
ock?
> > > > > That is not an entirely uncommon case.
> > > > =
> > > > Well, how would that differ from skipping a clock from clocks list,=
i.e. =
> > > > not specifying it in clock-names and clocks properties?
> > > =
> > > The difference is that you can successfully grab it in your driver.
> > =
> > That's a driver-specific issue. The driver knows best which clocks it
> > can live without (if it's poking only a subset of the hardware, it may
> > not need some just yet, but could for extended functionality in future
> > when support is extended), and could assign a dummy to those clocks it
> > knows it doesn't need that aren't described. That doesn't need to be in
> > the dt, and shouldn't be, because it's OS and driver specific.
> > =
> > > =
> > > > =
> > > > > > Background to why it might be a good idea to connect a ground c=
lock
> > > > > > to the unconnected input pins is that a driver has a chance to
> > > > > > successfully grab all clocks. Otherwise how does the driver
> > > > > > distinguish
> > > > > > between an unconnected and an erroneous clock?
> > > > > =
> > > > > Sorry, I don't follow this last question. Do you mean how to dist=
inguish
> > > > > based on the value returned from clk_get?
> > > > =
> > > > Hmm, in theory, a driver could want to distinguish an error case (e=
.g. =
> > > > clock specified, but there is a problem with it) from no clock (e.g=
. clock =
> > > > not specified in DT, because it is not available on particular boar=
d).
> > > =
> > > Yes, that's what I meant. To illustrate the problem for this driver:
> > > =
> > > for (i =3D 0; i < STC_TXCLK_SRC_MAX; i++) {
> > > sprintf(tmp, "rxtx%d", i);
> > > clk =3D devm_clk_get(&pdev->dev, tmp);
> > > if (IS_ERR(clk)) {
> > =
> > [...]
> > =
> > /*
> > * ERR_PTR(-ENOENT) returned when clock not
> > * present in the dt (i.e. not wired up). We can
> > * live without this clock, so assign a dummy
> > * (NULL) to simplify the rest of the code. If
> > * the clock is present but something else went
> > * wrong, we'll get a different ERR_PTR value
> > * and actually fail.
> > */
> > if (clk =3D=3D ERR_PTR(-ENOENT)
> > clk =3D NULL;
> > =
> > > }
> > > }
> > > =
> > > This could be solved by always specifying all input clocks in the
> > > devicetree.
> > =
> > As far as I can see, the above is sufficient, and leaves the knowledge
> > of skippable clocks in the driver, where I believe it should be.
> =
> You miss my point. Once a clock is specified in the devicetree it is no
> longer optional. The driver currently can't find out whether a clock
> hasn't been specified (and it's ok that it's not there) or a clock has
> been specified, but some error prevents actually grabbing the clock (in
> which case the driver should bail out)
Seems like the regulator framework is solving this with the new
regulator_get_optional() call. This leaves the
optional-versus-not-optional logic up to the driver.
Regards,
Mike
> =
> Sascha
> =
> =
> -- =
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
2013-08-23 21:41 ` Mike Turquette
(?)
@ 2013-08-24 0:20 ` Mark Brown
-1 siblings, 0 replies; 77+ messages in thread
From: Mark Brown @ 2013-08-24 0:20 UTC (permalink / raw)
To: Mike Turquette
Cc: Sascha Hauer, Mark Rutland, devicetree, alsa-devel, lars,
ian.campbell, Pawel Moll, swarren, festevam, Nicolin Chen,
Tomasz Figa, rob.herring, timur, p.zabel, galak, shawn.guo,
linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1288 bytes --]
On Fri, Aug 23, 2013 at 02:41:44PM -0700, Mike Turquette wrote:
> Seems like the regulator framework is solving this with the new
> regulator_get_optional() call. This leaves the
> optional-versus-not-optional logic up to the driver.
That is possibly for a slightly different case but perhaps not...
The problem we've got with the regulator API is that an awful lot of
regulators are always on and people generally don't want to go and hook
everything up, especially when drivers don't yet have regulator support.
This means that we end up with lots of complaints about having to add
regultors and lots of pain adding regulator support to widely used
devices, or drivers that just ignore errors which is not awesome.
We don't want to provide dummies since if the driver genuinely does have
optional regulators they tend to break them so we're adding that call to
allow the core to know if it can just provide a stub and assume the
board data was lazy.
My impression with clocks on most platforms is that there are fewer of
this sort of always on clock, though that said I know there has been a
bit of an issue with some of the IP clocks when IPs are used in SoCs
from less power sensitive environments that don't bother implementing
gating even in hardware.
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^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-24 0:20 ` Mark Brown
0 siblings, 0 replies; 77+ messages in thread
From: Mark Brown @ 2013-08-24 0:20 UTC (permalink / raw)
To: Mike Turquette
Cc: Mark Rutland, devicetree, alsa-devel, lars, ian.campbell,
Pawel Moll, swarren, linuxppc-dev, Sascha Hauer, Nicolin Chen,
Tomasz Figa, rob.herring, timur, p.zabel, galak, shawn.guo,
festevam
[-- Attachment #1.1: Type: text/plain, Size: 1288 bytes --]
On Fri, Aug 23, 2013 at 02:41:44PM -0700, Mike Turquette wrote:
> Seems like the regulator framework is solving this with the new
> regulator_get_optional() call. This leaves the
> optional-versus-not-optional logic up to the driver.
That is possibly for a slightly different case but perhaps not...
The problem we've got with the regulator API is that an awful lot of
regulators are always on and people generally don't want to go and hook
everything up, especially when drivers don't yet have regulator support.
This means that we end up with lots of complaints about having to add
regultors and lots of pain adding regulator support to widely used
devices, or drivers that just ignore errors which is not awesome.
We don't want to provide dummies since if the driver genuinely does have
optional regulators they tend to break them so we're adding that call to
allow the core to know if it can just provide a stub and assume the
board data was lazy.
My impression with clocks on most platforms is that there are fewer of
this sort of always on clock, though that said I know there has been a
bit of an issue with some of the IP clocks when IPs are used in SoCs
from less power sensitive environments that don't bother implementing
gating even in hardware.
[-- Attachment #1.2: Digital signature --]
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^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [alsa-devel] [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver
@ 2013-08-24 0:20 ` Mark Brown
0 siblings, 0 replies; 77+ messages in thread
From: Mark Brown @ 2013-08-24 0:20 UTC (permalink / raw)
To: Mike Turquette
Cc: Mark Rutland, devicetree, alsa-devel, lars, ian.campbell,
Pawel Moll, swarren, linuxppc-dev, Sascha Hauer, Nicolin Chen,
Tomasz Figa, rob.herring, timur, p.zabel, galak, shawn.guo,
festevam
[-- Attachment #1: Type: text/plain, Size: 1288 bytes --]
On Fri, Aug 23, 2013 at 02:41:44PM -0700, Mike Turquette wrote:
> Seems like the regulator framework is solving this with the new
> regulator_get_optional() call. This leaves the
> optional-versus-not-optional logic up to the driver.
That is possibly for a slightly different case but perhaps not...
The problem we've got with the regulator API is that an awful lot of
regulators are always on and people generally don't want to go and hook
everything up, especially when drivers don't yet have regulator support.
This means that we end up with lots of complaints about having to add
regultors and lots of pain adding regulator support to widely used
devices, or drivers that just ignore errors which is not awesome.
We don't want to provide dummies since if the driver genuinely does have
optional regulators they tend to break them so we're adding that call to
allow the core to know if it can just provide a stub and assume the
board data was lazy.
My impression with clocks on most platforms is that there are fewer of
this sort of always on clock, though that said I know there has been a
bit of an issue with some of the IP clocks when IPs are used in SoCs
from less power sensitive environments that don't bother implementing
gating even in hardware.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 77+ messages in thread
end of thread, other threads:[~2013-08-24 0:20 UTC | newest]
Thread overview: 77+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-08-15 11:26 [PATCH v5 0/2] Add freescale S/PDIF CPU DAI and machine drivers Nicolin Chen
2013-08-15 11:26 ` Nicolin Chen
2013-08-15 11:26 ` Nicolin Chen
2013-08-15 11:26 ` [PATCH v5 1/2] ASoC: fsl: Add S/PDIF CPU DAI driver Nicolin Chen
2013-08-15 11:26 ` Nicolin Chen
2013-08-15 11:26 ` Nicolin Chen
2013-08-15 12:18 ` Tomasz Figa
2013-08-15 12:18 ` Tomasz Figa
2013-08-15 12:18 ` Tomasz Figa
2013-08-16 4:43 ` Nicolin Chen
2013-08-16 7:08 ` Sascha Hauer
2013-08-16 8:01 ` Nicolin Chen
2013-08-16 8:56 ` Sascha Hauer
2013-08-16 9:53 ` Nicolin Chen
2013-08-16 10:11 ` Sascha Hauer
2013-08-16 10:16 ` Nicolin Chen
2013-08-17 12:28 ` Tomasz Figa
2013-08-17 12:28 ` Tomasz Figa
2013-08-17 14:53 ` Sascha Hauer
2013-08-17 14:53 ` Sascha Hauer
2013-08-17 15:17 ` Tomasz Figa
2013-08-17 15:17 ` Tomasz Figa
2013-08-19 9:35 ` Mark Rutland
2013-08-19 9:35 ` Mark Rutland
2013-08-20 0:06 ` Mike Turquette
2013-08-20 0:06 ` Mike Turquette
2013-08-20 0:06 ` Mike Turquette
2013-08-21 8:50 ` Mark Rutland
2013-08-21 8:50 ` Mark Rutland
2013-08-21 21:34 ` Tomasz Figa
2013-08-21 21:34 ` Tomasz Figa
2013-08-22 7:19 ` Mike Turquette
2013-08-22 7:19 ` Mike Turquette
2013-08-22 7:19 ` Mike Turquette
2013-08-22 12:09 ` Mark Rutland
2013-08-22 12:09 ` Mark Rutland
2013-08-22 21:00 ` Sascha Hauer
2013-08-22 21:00 ` Sascha Hauer
2013-08-22 22:43 ` Mike Turquette
2013-08-22 22:43 ` Mike Turquette
2013-08-22 22:43 ` Mike Turquette
2013-08-22 22:49 ` Tomasz Figa
2013-08-22 22:49 ` Tomasz Figa
2013-08-23 6:34 ` Sascha Hauer
2013-08-23 6:34 ` Sascha Hauer
2013-08-23 12:58 ` Mark Rutland
2013-08-23 12:58 ` Mark Rutland
2013-08-23 14:01 ` [alsa-devel] " Sascha Hauer
2013-08-23 14:01 ` Sascha Hauer
2013-08-23 14:01 ` Sascha Hauer
2013-08-23 14:57 ` [alsa-devel] " Mark Rutland
2013-08-23 14:57 ` Mark Rutland
2013-08-23 21:41 ` Mike Turquette
2013-08-23 21:41 ` Mike Turquette
2013-08-23 21:41 ` Mike Turquette
2013-08-24 0:20 ` [alsa-devel] " Mark Brown
2013-08-24 0:20 ` Mark Brown
2013-08-24 0:20 ` Mark Brown
2013-08-23 12:44 ` Mark Rutland
2013-08-23 12:44 ` Mark Rutland
2013-08-17 12:26 ` Tomasz Figa
2013-08-17 12:26 ` Tomasz Figa
2013-08-17 15:00 ` Sascha Hauer
2013-08-17 15:00 ` Sascha Hauer
2013-08-17 15:13 ` Tomasz Figa
2013-08-17 15:13 ` Tomasz Figa
2013-08-17 15:14 ` Sascha Hauer
2013-08-17 15:14 ` Sascha Hauer
2013-08-17 12:56 ` Tomasz Figa
2013-08-17 12:56 ` Tomasz Figa
2013-08-17 15:14 ` Sascha Hauer
2013-08-17 15:14 ` Sascha Hauer
2013-08-17 15:38 ` Tomasz Figa
2013-08-17 15:38 ` Tomasz Figa
2013-08-15 11:26 ` [PATCH v5 2/2] ASoC: fsl: Add S/PDIF machine driver Nicolin Chen
2013-08-15 11:26 ` Nicolin Chen
2013-08-15 11:26 ` Nicolin Chen
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