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* [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
@ 2014-02-06  4:44 ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, linux-arm-kernel, devicetree, linux-ide,
	linux-pci, spear-devel, linux-kernel

First three patches are improvement and fixes for SPEAr13xx support.
Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
wrapper. Patch 7 add support for SPEAr13xx PCIe.

These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk@ti.com>
Date:   Mon Jan 20 16:41:27 2014 +0200

    ata: ahci_platform: Manage SATA PHY

Tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Modifications for SATA are tested with SPEAr1340-evb board

Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3

Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
  the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall() 
 
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
 pcie designware driver improvements,fixes for IO translation bug, PCIe dw
 driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
 platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.

PCIe driver support for SPEAr1310/40 platform board is added.

These patches are tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-kernel@vger.kernel.org

Mohit Kumar (2):
  SPEAr13xx: defconfig: Update
  MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

Pratyush Anand (6):
  clk: SPEAr13xx: Fix pcie clock name
  SPEAr13xx: Fix static mapping table
  phy: st-miphy-40lp: Add skeleton driver
  SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  pcie: SPEAr13xx: Add designware pcie support

 .../devicetree/bindings/arm/spear-misc.txt         |   4 +
 .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
 .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 +
 MAINTAINERS                                        |   6 +
 arch/arm/boot/dts/spear1310-evb.dts                |   4 +
 arch/arm/boot/dts/spear1310.dtsi                   |  96 +++-
 arch/arm/boot/dts/spear1340-evb.dts                |   4 +
 arch/arm/boot/dts/spear1340.dtsi                   |  32 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |  10 +-
 arch/arm/configs/spear13xx_defconfig               |  15 +
 arch/arm/mach-spear/Kconfig                        |   3 +
 arch/arm/mach-spear/include/mach/spear.h           |   4 +-
 arch/arm/mach-spear/spear1340.c                    | 127 +----
 arch/arm/mach-spear/spear13xx.c                    |   2 +-
 drivers/clk/spear/spear1310_clock.c                |   6 +-
 drivers/clk/spear/spear1340_clock.c                |   2 +-
 drivers/pci/host/Kconfig                           |   5 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pcie-spear13xx.c                  | 414 ++++++++++++++++
 drivers/phy/Kconfig                                |   6 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-miphy40lp.c                        | 544 +++++++++++++++++++++
 22 files changed, 1166 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
 create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/pci/host/pcie-spear13xx.c
 create mode 100644 drivers/phy/phy-miphy40lp.c

-- 
1.8.1.2


^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
@ 2014-02-06  4:44 ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, linux-arm-kernel, devicetree, linux-ide,
	linux-pci, spear-devel, linux-kernel

First three patches are improvement and fixes for SPEAr13xx support.
Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
wrapper. Patch 7 add support for SPEAr13xx PCIe.

These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk@ti.com>
Date:   Mon Jan 20 16:41:27 2014 +0200

    ata: ahci_platform: Manage SATA PHY

Tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Modifications for SATA are tested with SPEAr1340-evb board

Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3

Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
  the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall() 
 
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
 pcie designware driver improvements,fixes for IO translation bug, PCIe dw
 driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
 platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.

PCIe driver support for SPEAr1310/40 platform board is added.

These patches are tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-kernel@vger.kernel.org

Mohit Kumar (2):
  SPEAr13xx: defconfig: Update
  MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

Pratyush Anand (6):
  clk: SPEAr13xx: Fix pcie clock name
  SPEAr13xx: Fix static mapping table
  phy: st-miphy-40lp: Add skeleton driver
  SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  pcie: SPEAr13xx: Add designware pcie support

 .../devicetree/bindings/arm/spear-misc.txt         |   4 +
 .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
 .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 +
 MAINTAINERS                                        |   6 +
 arch/arm/boot/dts/spear1310-evb.dts                |   4 +
 arch/arm/boot/dts/spear1310.dtsi                   |  96 +++-
 arch/arm/boot/dts/spear1340-evb.dts                |   4 +
 arch/arm/boot/dts/spear1340.dtsi                   |  32 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |  10 +-
 arch/arm/configs/spear13xx_defconfig               |  15 +
 arch/arm/mach-spear/Kconfig                        |   3 +
 arch/arm/mach-spear/include/mach/spear.h           |   4 +-
 arch/arm/mach-spear/spear1340.c                    | 127 +----
 arch/arm/mach-spear/spear13xx.c                    |   2 +-
 drivers/clk/spear/spear1310_clock.c                |   6 +-
 drivers/clk/spear/spear1340_clock.c                |   2 +-
 drivers/pci/host/Kconfig                           |   5 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pcie-spear13xx.c                  | 414 ++++++++++++++++
 drivers/phy/Kconfig                                |   6 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-miphy40lp.c                        | 544 +++++++++++++++++++++
 22 files changed, 1166 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
 create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/pci/host/pcie-spear13xx.c
 create mode 100644 drivers/phy/phy-miphy40lp.c

-- 
1.8.1.2


^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
@ 2014-02-06  4:44 ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

First three patches are improvement and fixes for SPEAr13xx support.
Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
wrapper. Patch 7 add support for SPEAr13xx PCIe.

These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <balajitk@ti.com>
Date:   Mon Jan 20 16:41:27 2014 +0200

    ata: ahci_platform: Manage SATA PHY

Tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Modifications for SATA are tested with SPEAr1340-evb board

Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3

Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
  the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall() 
 
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
 pcie designware driver improvements,fixes for IO translation bug, PCIe dw
 driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
 platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.

PCIe driver support for SPEAr1310/40 platform board is added.

These patches are tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch

Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
Cc: linux-pci at vger.kernel.org
Cc: spear-devel at list.st.com
Cc: linux-kernel at vger.kernel.org

Mohit Kumar (2):
  SPEAr13xx: defconfig: Update
  MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

Pratyush Anand (6):
  clk: SPEAr13xx: Fix pcie clock name
  SPEAr13xx: Fix static mapping table
  phy: st-miphy-40lp: Add skeleton driver
  SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  pcie: SPEAr13xx: Add designware pcie support

 .../devicetree/bindings/arm/spear-misc.txt         |   4 +
 .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
 .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 +
 MAINTAINERS                                        |   6 +
 arch/arm/boot/dts/spear1310-evb.dts                |   4 +
 arch/arm/boot/dts/spear1310.dtsi                   |  96 +++-
 arch/arm/boot/dts/spear1340-evb.dts                |   4 +
 arch/arm/boot/dts/spear1340.dtsi                   |  32 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |  10 +-
 arch/arm/configs/spear13xx_defconfig               |  15 +
 arch/arm/mach-spear/Kconfig                        |   3 +
 arch/arm/mach-spear/include/mach/spear.h           |   4 +-
 arch/arm/mach-spear/spear1340.c                    | 127 +----
 arch/arm/mach-spear/spear13xx.c                    |   2 +-
 drivers/clk/spear/spear1310_clock.c                |   6 +-
 drivers/clk/spear/spear1340_clock.c                |   2 +-
 drivers/pci/host/Kconfig                           |   5 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pcie-spear13xx.c                  | 414 ++++++++++++++++
 drivers/phy/Kconfig                                |   6 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-miphy40lp.c                        | 544 +++++++++++++++++++++
 22 files changed, 1166 insertions(+), 139 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
 create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/pci/host/pcie-spear13xx.c
 create mode 100644 drivers/phy/phy-miphy40lp.c

-- 
1.8.1.2

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 1/8] clk: SPEAr13xx: Fix pcie clock name
  2014-02-06  4:44 ` Pratyush Anand
  (?)
  (?)
@ 2014-02-06  4:44 ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

Follow dt clock naming convention for PCIe clocks.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/clk/spear/spear1310_clock.c | 6 +++---
 drivers/clk/spear/spear1340_clock.c | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.0");
+	clk_register_clkdev(clk, NULL, "b1000000.pcie");
 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.1");
+	clk_register_clkdev(clk, NULL, "b1800000.pcie");
 	clk_register_clkdev(clk, NULL, "b1800000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.2");
+	clk_register_clkdev(clk, NULL, "b4000000.pcie");
 	clk_register_clkdev(clk, NULL, "b4000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie");
+	clk_register_clkdev(clk, NULL, "b1000000.pcie");
 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 2/8] SPEAr13xx: Fix static mapping table
  2014-02-06  4:44 ` Pratyush Anand
                   ` (2 preceding siblings ...)
  (?)
@ 2014-02-06  4:44 ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

SPEAr13xx was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: stable at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h | 4 ++--
 arch/arm/mach-spear/spear13xx.c          | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..f2d6a01 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
 #ifdef CONFIG_ARCH_SPEAR13XX
 
 #define PERIP_GRP2_BASE				UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE			IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE			IOMEM(0xF9000000)
 #define MCIF_SDHCI_BASE				UL(0xB3000000)
 #define SYSRAM0_BASE				UL(0xB3800000)
-#define VA_SYSRAM0_BASE				IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE				IOMEM(0xF9800000)
 #define SYS_LOCATION				(VA_SYSRAM0_BASE + 0x600)
 
 #define PERIP_GRP1_BASE				UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..89212ff 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)
 /*
  * Following will create 16MB static virtual/physical mappings
  * PHYSICAL		VIRTUAL
- * 0xB3000000		0xFE000000
+ * 0xB3000000		0xF9000000
  * 0xE0000000		0xFD000000
  * 0xEC000000		0xFC000000
  * 0xED000000		0xFB000000
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 3/8] SPEAr13xx: defconfig: Update
  2014-02-06  4:44 ` Pratyush Anand
                   ` (3 preceding siblings ...)
  (?)
@ 2014-02-06  4:44 ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

From: Mohit Kumar <mohit.kumar@st.com>

Enable EABI, VFP and NFS configs in default configuration file for
SPEAr13xx.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/configs/spear13xx_defconfig | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..1e0bb6f 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -14,10 +14,18 @@ CONFIG_MACH_SPEAR1340=y
 CONFIG_SMP=y
 # CONFIG_SMP_ON_UP is not set
 # CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_OF_PARTS=y
@@ -27,6 +35,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
 CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +75,7 @@ CONFIG_USB=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +89,14 @@ CONFIG_EXT2_FS_SECURITY=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_SECURITY=y
 CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
  2014-02-06  4:44 ` Pratyush Anand
  (?)
@ 2014-02-06  4:44   ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, Kishon Vijay Abraham I, spear-devel,
	linux-arm-kernel, devicetree, linux-kernel

ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
skeleton support for the same.

Currently phy ops are returning -EINVAL. They can be elaborated
depending on the SOC being supported in future.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
 drivers/phy/Kconfig                                |   6 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
 4 files changed, 193 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/phy/phy-miphy40lp.c

diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..d0c7096
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,12 @@
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+	Other supported soc specific compatible:
+		"st,spear1310-miphy"
+		"st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- 1st cell: phandle to the phy node.
+	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+	  and 2 for Super Speed USB.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..2f58993 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
 	help
 	  Enable this to support the Broadcom Kona USB 2.0 PHY.
 
+config PHY_ST_MIPHY40LP
+	tristate "ST MIPHY 40LP driver"
+	help
+	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
+	select GENERIC_PHY
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..c061091 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
new file mode 100644
index 0000000..d478c14
--- /dev/null
+++ b/drivers/phy/phy-miphy40lp.c
@@ -0,0 +1,174 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+enum phy_mode {
+	SATA,
+	PCIE,
+	SS_USB,
+};
+
+struct st_miphy40lp_priv {
+	/* regmap for any soc specific misc registers */
+	struct regmap		*misc;
+	/* phy struct pointer */
+	struct phy		*phy;
+	/* device node pointer */
+	struct device_node	*np;
+	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+	enum phy_mode		mode;
+	/* instance id of this phy */
+	u32			id;
+};
+
+static int miphy40lp_init(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_exit(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_power_off(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_power_on(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static const struct of_device_id st_miphy40lp_of_match[] = {
+	{ .compatible = "st,miphy40lp-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
+
+static struct phy_ops st_miphy40lp_ops = {
+	.init = miphy40lp_init,
+	.exit = miphy40lp_exit,
+	.power_off = miphy40lp_power_off,
+	.power_on = miphy40lp_power_on,
+	.owner		= THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_resume(struct device *dev)
+{
+	return -EINVAL;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+		miphy40lp_resume);
+
+static struct phy *st_miphy40lp_xlate(struct device *dev,
+					struct of_phandle_args *args)
+{
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (args->args_count < 1) {
+		dev_err(dev, "DT did not pass correct no of args\n");
+		return NULL;
+	}
+
+	phypriv->mode = args->args[0];
+
+	return phypriv->phy;
+}
+
+static int __init st_miphy40lp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct st_miphy40lp_priv *phypriv;
+	struct phy_provider *phy_provider;
+
+	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+	if (!phypriv) {
+		dev_err(dev, "can't alloc miphy40lp private date memory\n");
+		return -ENOMEM;
+	}
+
+	phypriv->np = dev->of_node;
+
+	phypriv->misc =
+		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+	if (IS_ERR(phypriv->misc)) {
+		dev_err(dev, "failed to find misc regmap\n");
+		return PTR_ERR(phypriv->misc);
+	}
+
+	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
+		dev_err(dev, "failed to find phy id\n");
+		return -EINVAL;
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "failed to register phy provider\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
+	if (IS_ERR(phypriv->phy)) {
+		dev_err(dev, "failed to create SATA PCIe PHY\n");
+		return PTR_ERR(phypriv->phy);
+	}
+
+	dev_set_drvdata(dev, phypriv);
+	phy_set_drvdata(phypriv->phy, phypriv);
+
+	return 0;
+}
+
+static int __exit st_miphy40lp_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver st_miphy40lp_driver = {
+	.remove		= __exit_p(st_miphy40lp_remove),
+	.driver = {
+		.name = "miphy40lp-phy",
+		.owner = THIS_MODULE,
+		.pm = &miphy40lp_pm_ops,
+		.of_match_table = of_match_ptr(st_miphy40lp_of_match),
+	},
+};
+
+static int __init st_miphy40lp_init(void)
+{
+
+	return platform_driver_probe(&st_miphy40lp_driver,
+				st_miphy40lp_probe);
+}
+module_init(st_miphy40lp_init);
+
+MODULE_DESCRIPTION("ST MIPHY-40LP driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.2


^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  4:44   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, Kishon Vijay Abraham I, spear-devel,
	linux-arm-kernel, devicetree, linux-kernel

ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
skeleton support for the same.

Currently phy ops are returning -EINVAL. They can be elaborated
depending on the SOC being supported in future.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
 drivers/phy/Kconfig                                |   6 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
 4 files changed, 193 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/phy/phy-miphy40lp.c

diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..d0c7096
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,12 @@
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+	Other supported soc specific compatible:
+		"st,spear1310-miphy"
+		"st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- 1st cell: phandle to the phy node.
+	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+	  and 2 for Super Speed USB.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..2f58993 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
 	help
 	  Enable this to support the Broadcom Kona USB 2.0 PHY.
 
+config PHY_ST_MIPHY40LP
+	tristate "ST MIPHY 40LP driver"
+	help
+	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
+	select GENERIC_PHY
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..c061091 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
new file mode 100644
index 0000000..d478c14
--- /dev/null
+++ b/drivers/phy/phy-miphy40lp.c
@@ -0,0 +1,174 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+enum phy_mode {
+	SATA,
+	PCIE,
+	SS_USB,
+};
+
+struct st_miphy40lp_priv {
+	/* regmap for any soc specific misc registers */
+	struct regmap		*misc;
+	/* phy struct pointer */
+	struct phy		*phy;
+	/* device node pointer */
+	struct device_node	*np;
+	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+	enum phy_mode		mode;
+	/* instance id of this phy */
+	u32			id;
+};
+
+static int miphy40lp_init(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_exit(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_power_off(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_power_on(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static const struct of_device_id st_miphy40lp_of_match[] = {
+	{ .compatible = "st,miphy40lp-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
+
+static struct phy_ops st_miphy40lp_ops = {
+	.init = miphy40lp_init,
+	.exit = miphy40lp_exit,
+	.power_off = miphy40lp_power_off,
+	.power_on = miphy40lp_power_on,
+	.owner		= THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_resume(struct device *dev)
+{
+	return -EINVAL;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+		miphy40lp_resume);
+
+static struct phy *st_miphy40lp_xlate(struct device *dev,
+					struct of_phandle_args *args)
+{
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (args->args_count < 1) {
+		dev_err(dev, "DT did not pass correct no of args\n");
+		return NULL;
+	}
+
+	phypriv->mode = args->args[0];
+
+	return phypriv->phy;
+}
+
+static int __init st_miphy40lp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct st_miphy40lp_priv *phypriv;
+	struct phy_provider *phy_provider;
+
+	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+	if (!phypriv) {
+		dev_err(dev, "can't alloc miphy40lp private date memory\n");
+		return -ENOMEM;
+	}
+
+	phypriv->np = dev->of_node;
+
+	phypriv->misc =
+		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+	if (IS_ERR(phypriv->misc)) {
+		dev_err(dev, "failed to find misc regmap\n");
+		return PTR_ERR(phypriv->misc);
+	}
+
+	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
+		dev_err(dev, "failed to find phy id\n");
+		return -EINVAL;
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "failed to register phy provider\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
+	if (IS_ERR(phypriv->phy)) {
+		dev_err(dev, "failed to create SATA PCIe PHY\n");
+		return PTR_ERR(phypriv->phy);
+	}
+
+	dev_set_drvdata(dev, phypriv);
+	phy_set_drvdata(phypriv->phy, phypriv);
+
+	return 0;
+}
+
+static int __exit st_miphy40lp_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver st_miphy40lp_driver = {
+	.remove		= __exit_p(st_miphy40lp_remove),
+	.driver = {
+		.name = "miphy40lp-phy",
+		.owner = THIS_MODULE,
+		.pm = &miphy40lp_pm_ops,
+		.of_match_table = of_match_ptr(st_miphy40lp_of_match),
+	},
+};
+
+static int __init st_miphy40lp_init(void)
+{
+
+	return platform_driver_probe(&st_miphy40lp_driver,
+				st_miphy40lp_probe);
+}
+module_init(st_miphy40lp_init);
+
+MODULE_DESCRIPTION("ST MIPHY-40LP driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  4:44   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
skeleton support for the same.

Currently phy ops are returning -EINVAL. They can be elaborated
depending on the SOC being supported in future.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
---
 .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
 drivers/phy/Kconfig                                |   6 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
 4 files changed, 193 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
 create mode 100644 drivers/phy/phy-miphy40lp.c

diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..d0c7096
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,12 @@
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+	Other supported soc specific compatible:
+		"st,spear1310-miphy"
+		"st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- 1st cell: phandle to the phy node.
+	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+	  and 2 for Super Speed USB.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..2f58993 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
 	help
 	  Enable this to support the Broadcom Kona USB 2.0 PHY.
 
+config PHY_ST_MIPHY40LP
+	tristate "ST MIPHY 40LP driver"
+	help
+	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
+	select GENERIC_PHY
+
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..c061091 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
 obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
 obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
 obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
new file mode 100644
index 0000000..d478c14
--- /dev/null
+++ b/drivers/phy/phy-miphy40lp.c
@@ -0,0 +1,174 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+enum phy_mode {
+	SATA,
+	PCIE,
+	SS_USB,
+};
+
+struct st_miphy40lp_priv {
+	/* regmap for any soc specific misc registers */
+	struct regmap		*misc;
+	/* phy struct pointer */
+	struct phy		*phy;
+	/* device node pointer */
+	struct device_node	*np;
+	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+	enum phy_mode		mode;
+	/* instance id of this phy */
+	u32			id;
+};
+
+static int miphy40lp_init(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_exit(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_power_off(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_power_on(struct phy *phy)
+{
+	return -EINVAL;
+}
+
+static const struct of_device_id st_miphy40lp_of_match[] = {
+	{ .compatible = "st,miphy40lp-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
+
+static struct phy_ops st_miphy40lp_ops = {
+	.init = miphy40lp_init,
+	.exit = miphy40lp_exit,
+	.power_off = miphy40lp_power_off,
+	.power_on = miphy40lp_power_on,
+	.owner		= THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev)
+{
+	return -EINVAL;
+}
+
+static int miphy40lp_resume(struct device *dev)
+{
+	return -EINVAL;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+		miphy40lp_resume);
+
+static struct phy *st_miphy40lp_xlate(struct device *dev,
+					struct of_phandle_args *args)
+{
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (args->args_count < 1) {
+		dev_err(dev, "DT did not pass correct no of args\n");
+		return NULL;
+	}
+
+	phypriv->mode = args->args[0];
+
+	return phypriv->phy;
+}
+
+static int __init st_miphy40lp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct st_miphy40lp_priv *phypriv;
+	struct phy_provider *phy_provider;
+
+	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+	if (!phypriv) {
+		dev_err(dev, "can't alloc miphy40lp private date memory\n");
+		return -ENOMEM;
+	}
+
+	phypriv->np = dev->of_node;
+
+	phypriv->misc =
+		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+	if (IS_ERR(phypriv->misc)) {
+		dev_err(dev, "failed to find misc regmap\n");
+		return PTR_ERR(phypriv->misc);
+	}
+
+	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
+		dev_err(dev, "failed to find phy id\n");
+		return -EINVAL;
+	}
+
+	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
+	if (IS_ERR(phy_provider)) {
+		dev_err(dev, "failed to register phy provider\n");
+		return PTR_ERR(phy_provider);
+	}
+
+	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
+	if (IS_ERR(phypriv->phy)) {
+		dev_err(dev, "failed to create SATA PCIe PHY\n");
+		return PTR_ERR(phypriv->phy);
+	}
+
+	dev_set_drvdata(dev, phypriv);
+	phy_set_drvdata(phypriv->phy, phypriv);
+
+	return 0;
+}
+
+static int __exit st_miphy40lp_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver st_miphy40lp_driver = {
+	.remove		= __exit_p(st_miphy40lp_remove),
+	.driver = {
+		.name = "miphy40lp-phy",
+		.owner = THIS_MODULE,
+		.pm = &miphy40lp_pm_ops,
+		.of_match_table = of_match_ptr(st_miphy40lp_of_match),
+	},
+};
+
+static int __init st_miphy40lp_init(void)
+{
+
+	return platform_driver_probe(&st_miphy40lp_driver,
+				st_miphy40lp_probe);
+}
+module_init(st_miphy40lp_init);
+
+MODULE_DESCRIPTION("ST MIPHY-40LP driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  2014-02-06  4:44 ` Pratyush Anand
  (?)
@ 2014-02-06  4:44   ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, Viresh Kumar, Tejun Heo, Kishon Vijay Abraham I,
	spear-devel, linux-arm-kernel, devicetree, linux-ide,
	linux-kernel

ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.

Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.

So move all these SATA platform code to phy-miphy40lp driver.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/spear-misc.txt         |   4 +
 arch/arm/boot/dts/spear1310-evb.dts                |   4 +
 arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
 arch/arm/boot/dts/spear1340-evb.dts                |   4 +
 arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
 arch/arm/mach-spear/Kconfig                        |   2 +
 arch/arm/mach-spear/spear1340.c                    | 127 +------------
 drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
 9 files changed, 266 insertions(+), 136 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt

diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..aacd36a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,4 @@
+* SPEAr Misc configuration
+** misc node required properties:
+- compatible Should be	"st,spear1340-misc", "syscon".
+- reg: Address range of misc space
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
 			status = "okay";
 		};
 
+		miphy@eb800000 {
+			status = "okay";
+		};
+
 		cf@b2800000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
 			#gpio-cells = <2>;
 		};
 
-		ahci@b1000000 {
+		miphy0: miphy@eb800000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy1: miphy@eb804000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb804000 0x4000>;
+			misc = <&misc>;
+			phy-id = <1>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy2: miphy@eb808000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb808000 0x4000>;
+			misc = <&misc>;
+			phy-id = <2>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci@b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 68 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci@b1800000 {
+		ahci1: ahci@b1800000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1800000 0x10000>;
 			interrupts = <0 69 0x4>;
+			phys = <&miphy1 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci@b4000000 {
+		ahci2: ahci@b4000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb4000000 0x10000>;
 			interrupts = <0 70 0x4>;
+			phys = <&miphy2 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
 			status = "okay";
 		};
 
+		miphy@eb800000 {
+			status = "okay";
+		};
+
 		dma@ea800000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..7e3a04b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,21 @@
 			status = "disabled";
 		};
 
-		ahci@b1000000 {
+		miphy0: miphy@eb800000 {
+			compatible = "st,miphy", "st,spear1340-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci@b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 72 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
 				  0xd8000000 0xd8000000 0x01000000
 				  0xe0000000 0xe0000000 0x10000000>;
 
+			misc: syscon@e0700000 {
+				compatible = "st,spear1340-misc", "syscon";
+				reg = <0xe0700000 0x1000>;
+			};
+
 			gpio0: gpio@e0600000 {
 				compatible = "arm,pl061", "arm,primecell";
 				reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e6..7e7f1b0 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
 	select USE_OF
+	select MFD_SYSCON
+	select PHY_ST_MIPHY40LP
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
  * warranty of any kind, whether express or implied.
  */
 
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
-	writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
-	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
-			SPEAR1340_PCIE_MIPHY_CFG);
-	/* Switch on sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-	/* Disable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-
-	return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
-	writel(0, SPEAR1340_PCIE_SATA_CFG);
-	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
-	/* Enable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-	/* Switch off sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_FREEZE)
-		return 0;
-
-	sata_miphy_exit(dev);
-
-	return 0;
-}
-
-int sata_resume(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_THAW)
-		return 0;
-
-	return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
-	.init = sata_miphy_init,
-	.exit = sata_miphy_exit,
-	.suspend = sata_suspend,
-	.resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
-			&sata_pdata),
-	{}
-};
 
 static void __init spear1340_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table,
-			spear1340_auxdata_lookup, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index d478c14..cc7f45d 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -8,6 +8,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
  */
 
 #include <linux/delay.h>
@@ -19,6 +20,60 @@
 #include <linux/phy/phy.h>
 #include <linux/regmap.h>
 
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG			0x100
+	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
+#define SPEAR1340_PCM_WKUP_CFG			0x104
+#define SPEAR1340_SWITCH_CTR			0x108
+
+#define SPEAR1340_PERIP1_SW_RST			0x318
+	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
+#define SPEAR1340_PERIP2_SW_RST			0x31C
+#define SPEAR1340_PERIP3_SW_RST			0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			0x424
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
+			SPEAR1340_SATA_CFG_PM_CLK_EN | \
+			SPEAR1340_SATA_CFG_POWERUP_RESET | \
+			SPEAR1340_SATA_CFG_RX_CLK_EN | \
+			SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG		0x428
+	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
 enum phy_mode {
 	SATA,
 	PCIE,
@@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
 	u32			id;
 };
 
+static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+	/* Switch on sata power domain */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN);
+	msleep(20);
+	/* Disable PCIE SATA Controller reset */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RST_SATA, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+	/* Enable PCIE SATA Controller reset */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RST_SATA,
+			SPEAR1340_PERIP1_SW_RST_SATA);
+	msleep(20);
+	/* Switch off sata power domain */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
 static int miphy40lp_init(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_init(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_exit(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_exit(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_power_off(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_power_off(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_power_on(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_power_on(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static const struct of_device_id st_miphy40lp_of_match[] = {
 	{ .compatible = "st,miphy40lp-phy" },
+	{ .compatible = "st,spear1340-miphy" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
@@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
 #ifdef CONFIG_PM_SLEEP
 static int miphy40lp_suspend(struct device *dev)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (dev->power.power_state.event == PM_EVENT_FREEZE)
+		return 0;
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_suspend(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_resume(struct device *dev)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (dev->power.power_state.event == PM_EVENT_THAW)
+		return 0;
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_resume(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 #endif
 
-- 
1.8.1.2


^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  4:44   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, Viresh Kumar, Tejun Heo, Kishon Vijay Abraham I,
	spear-devel, linux-arm-kernel, devicetree, linux-ide,
	linux-kernel

ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.

Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.

So move all these SATA platform code to phy-miphy40lp driver.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 .../devicetree/bindings/arm/spear-misc.txt         |   4 +
 arch/arm/boot/dts/spear1310-evb.dts                |   4 +
 arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
 arch/arm/boot/dts/spear1340-evb.dts                |   4 +
 arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
 arch/arm/mach-spear/Kconfig                        |   2 +
 arch/arm/mach-spear/spear1340.c                    | 127 +------------
 drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
 9 files changed, 266 insertions(+), 136 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt

diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..aacd36a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,4 @@
+* SPEAr Misc configuration
+** misc node required properties:
+- compatible Should be	"st,spear1340-misc", "syscon".
+- reg: Address range of misc space
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
 			status = "okay";
 		};
 
+		miphy@eb800000 {
+			status = "okay";
+		};
+
 		cf@b2800000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
 			#gpio-cells = <2>;
 		};
 
-		ahci@b1000000 {
+		miphy0: miphy@eb800000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy1: miphy@eb804000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb804000 0x4000>;
+			misc = <&misc>;
+			phy-id = <1>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy2: miphy@eb808000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb808000 0x4000>;
+			misc = <&misc>;
+			phy-id = <2>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci@b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 68 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci@b1800000 {
+		ahci1: ahci@b1800000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1800000 0x10000>;
 			interrupts = <0 69 0x4>;
+			phys = <&miphy1 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci@b4000000 {
+		ahci2: ahci@b4000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb4000000 0x10000>;
 			interrupts = <0 70 0x4>;
+			phys = <&miphy2 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
 			status = "okay";
 		};
 
+		miphy@eb800000 {
+			status = "okay";
+		};
+
 		dma@ea800000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..7e3a04b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,21 @@
 			status = "disabled";
 		};
 
-		ahci@b1000000 {
+		miphy0: miphy@eb800000 {
+			compatible = "st,miphy", "st,spear1340-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci@b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 72 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
 				  0xd8000000 0xd8000000 0x01000000
 				  0xe0000000 0xe0000000 0x10000000>;
 
+			misc: syscon@e0700000 {
+				compatible = "st,spear1340-misc", "syscon";
+				reg = <0xe0700000 0x1000>;
+			};
+
 			gpio0: gpio@e0600000 {
 				compatible = "arm,pl061", "arm,primecell";
 				reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e6..7e7f1b0 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
 	select USE_OF
+	select MFD_SYSCON
+	select PHY_ST_MIPHY40LP
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
  * warranty of any kind, whether express or implied.
  */
 
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
-	writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
-	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
-			SPEAR1340_PCIE_MIPHY_CFG);
-	/* Switch on sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-	/* Disable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-
-	return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
-	writel(0, SPEAR1340_PCIE_SATA_CFG);
-	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
-	/* Enable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-	/* Switch off sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_FREEZE)
-		return 0;
-
-	sata_miphy_exit(dev);
-
-	return 0;
-}
-
-int sata_resume(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_THAW)
-		return 0;
-
-	return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
-	.init = sata_miphy_init,
-	.exit = sata_miphy_exit,
-	.suspend = sata_suspend,
-	.resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
-			&sata_pdata),
-	{}
-};
 
 static void __init spear1340_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table,
-			spear1340_auxdata_lookup, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index d478c14..cc7f45d 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -8,6 +8,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
  */
 
 #include <linux/delay.h>
@@ -19,6 +20,60 @@
 #include <linux/phy/phy.h>
 #include <linux/regmap.h>
 
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG			0x100
+	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
+#define SPEAR1340_PCM_WKUP_CFG			0x104
+#define SPEAR1340_SWITCH_CTR			0x108
+
+#define SPEAR1340_PERIP1_SW_RST			0x318
+	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
+#define SPEAR1340_PERIP2_SW_RST			0x31C
+#define SPEAR1340_PERIP3_SW_RST			0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			0x424
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
+			SPEAR1340_SATA_CFG_PM_CLK_EN | \
+			SPEAR1340_SATA_CFG_POWERUP_RESET | \
+			SPEAR1340_SATA_CFG_RX_CLK_EN | \
+			SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG		0x428
+	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
 enum phy_mode {
 	SATA,
 	PCIE,
@@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
 	u32			id;
 };
 
+static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+	/* Switch on sata power domain */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN);
+	msleep(20);
+	/* Disable PCIE SATA Controller reset */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RST_SATA, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+	/* Enable PCIE SATA Controller reset */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RST_SATA,
+			SPEAR1340_PERIP1_SW_RST_SATA);
+	msleep(20);
+	/* Switch off sata power domain */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
 static int miphy40lp_init(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_init(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_exit(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_exit(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_power_off(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_power_off(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_power_on(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_power_on(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static const struct of_device_id st_miphy40lp_of_match[] = {
 	{ .compatible = "st,miphy40lp-phy" },
+	{ .compatible = "st,spear1340-miphy" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
@@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
 #ifdef CONFIG_PM_SLEEP
 static int miphy40lp_suspend(struct device *dev)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (dev->power.power_state.event == PM_EVENT_FREEZE)
+		return 0;
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_suspend(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_resume(struct device *dev)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (dev->power.power_state.event == PM_EVENT_THAW)
+		return 0;
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_resume(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 #endif
 
-- 
1.8.1.2


^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  4:44   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.

Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.

So move all these SATA platform code to phy-miphy40lp driver.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-ide at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
---
 .../devicetree/bindings/arm/spear-misc.txt         |   4 +
 arch/arm/boot/dts/spear1310-evb.dts                |   4 +
 arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
 arch/arm/boot/dts/spear1340-evb.dts                |   4 +
 arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
 arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
 arch/arm/mach-spear/Kconfig                        |   2 +
 arch/arm/mach-spear/spear1340.c                    | 127 +------------
 drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
 9 files changed, 266 insertions(+), 136 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt

diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..aacd36a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,4 @@
+* SPEAr Misc configuration
+** misc node required properties:
+- compatible Should be	"st,spear1340-misc", "syscon".
+- reg: Address range of misc space
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
 			status = "okay";
 		};
 
+		miphy at eb800000 {
+			status = "okay";
+		};
+
 		cf at b2800000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
 			#gpio-cells = <2>;
 		};
 
-		ahci at b1000000 {
+		miphy0: miphy at eb800000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy1: miphy at eb804000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb804000 0x4000>;
+			misc = <&misc>;
+			phy-id = <1>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		miphy2: miphy at eb808000 {
+			compatible = "st,miphy", "st,spear1310-miphy";
+			reg = <0xeb808000 0x4000>;
+			misc = <&misc>;
+			phy-id = <2>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci at b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 68 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci at b1800000 {
+		ahci1: ahci at b1800000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1800000 0x10000>;
 			interrupts = <0 69 0x4>;
+			phys = <&miphy1 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
-		ahci at b4000000 {
+		ahci2: ahci at b4000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb4000000 0x10000>;
 			interrupts = <0 70 0x4>;
+			phys = <&miphy2 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
 			status = "okay";
 		};
 
+		miphy at eb800000 {
+			status = "okay";
+		};
+
 		dma at ea800000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..7e3a04b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,21 @@
 			status = "disabled";
 		};
 
-		ahci at b1000000 {
+		miphy0: miphy at eb800000 {
+			compatible = "st,miphy", "st,spear1340-miphy";
+			reg = <0xeb800000 0x4000>;
+			misc = <&misc>;
+			phy-id = <0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
+		ahci0: ahci at b1000000 {
 			compatible = "snps,spear-ahci";
 			reg = <0xb1000000 0x10000>;
 			interrupts = <0 72 0x4>;
+			phys = <&miphy0 0>;
+			phy-names = "sata-phy";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
 				  0xd8000000 0xd8000000 0x01000000
 				  0xe0000000 0xe0000000 0x10000000>;
 
+			misc: syscon at e0700000 {
+				compatible = "st,spear1340-misc", "syscon";
+				reg = <0xe0700000 0x1000>;
+			};
+
 			gpio0: gpio at e0600000 {
 				compatible = "arm,pl061", "arm,primecell";
 				reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e6..7e7f1b0 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
 	select USE_OF
+	select MFD_SYSCON
+	select PHY_ST_MIPHY40LP
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
  * warranty of any kind, whether express or implied.
  */
 
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
-	writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
-	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
-			SPEAR1340_PCIE_MIPHY_CFG);
-	/* Switch on sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-	/* Disable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-
-	return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
-	writel(0, SPEAR1340_PCIE_SATA_CFG);
-	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
-	/* Enable PCIE SATA Controller reset */
-	writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
-			SPEAR1340_PERIP1_SW_RST);
-	msleep(20);
-	/* Switch off sata power domain */
-	writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
-	msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_FREEZE)
-		return 0;
-
-	sata_miphy_exit(dev);
-
-	return 0;
-}
-
-int sata_resume(struct device *dev)
-{
-	if (dev->power.power_state.event == PM_EVENT_THAW)
-		return 0;
-
-	return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
-	.init = sata_miphy_init,
-	.exit = sata_miphy_exit,
-	.suspend = sata_suspend,
-	.resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
-			&sata_pdata),
-	{}
-};
 
 static void __init spear1340_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table,
-			spear1340_auxdata_lookup, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index d478c14..cc7f45d 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -8,6 +8,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
  */
 
 #include <linux/delay.h>
@@ -19,6 +20,60 @@
 #include <linux/phy/phy.h>
 #include <linux/regmap.h>
 
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG			0x100
+	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
+#define SPEAR1340_PCM_WKUP_CFG			0x104
+#define SPEAR1340_SWITCH_CTR			0x108
+
+#define SPEAR1340_PERIP1_SW_RST			0x318
+	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
+#define SPEAR1340_PERIP2_SW_RST			0x31C
+#define SPEAR1340_PERIP3_SW_RST			0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			0x424
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
+			SPEAR1340_SATA_CFG_PM_CLK_EN | \
+			SPEAR1340_SATA_CFG_POWERUP_RESET | \
+			SPEAR1340_SATA_CFG_RX_CLK_EN | \
+			SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG		0x428
+	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
 enum phy_mode {
 	SATA,
 	PCIE,
@@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
 	u32			id;
 };
 
+static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+	/* Switch on sata power domain */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN);
+	msleep(20);
+	/* Disable PCIE SATA Controller reset */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RST_SATA, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+	/* Enable PCIE SATA Controller reset */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+			SPEAR1340_PERIP1_SW_RST_SATA,
+			SPEAR1340_PERIP1_SW_RST_SATA);
+	msleep(20);
+	/* Switch off sata power domain */
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+	msleep(20);
+
+	return 0;
+}
+
+static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_sata_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
 static int miphy40lp_init(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_init(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_exit(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_exit(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_power_off(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_power_off(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_power_on(struct phy *phy)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_power_on(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static const struct of_device_id st_miphy40lp_of_match[] = {
 	{ .compatible = "st,miphy40lp-phy" },
+	{ .compatible = "st,spear1340-miphy" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
@@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
 #ifdef CONFIG_PM_SLEEP
 static int miphy40lp_suspend(struct device *dev)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (dev->power.power_state.event == PM_EVENT_FREEZE)
+		return 0;
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_suspend(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 
 static int miphy40lp_resume(struct device *dev)
 {
-	return -EINVAL;
+	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+	if (dev->power.power_state.event == PM_EVENT_THAW)
+		return 0;
+
+	switch (phypriv->mode) {
+	case SATA:
+		return sata_miphy_resume(phypriv);
+	default:
+		return -EINVAL;
+	}
 }
 #endif
 
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  2014-02-06  4:44 ` Pratyush Anand
@ 2014-02-06  4:44   ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, Kishon Vijay Abraham I, spear-devel,
	linux-arm-kernel, linux-kernel

SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
support for the same.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/phy/phy-miphy40lp.c | 178 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index cc7f45d..61e94be 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  *
  * 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
  */
 
 #include <linux/delay.h>
@@ -73,6 +74,80 @@
 	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
 			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
 			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG			0x3A4
+	#define SPEAR1310_PCIE_SATA2_SEL_PCIE		(0 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_PCIE		(0 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_PCIE		(0 << 29)
+	#define SPEAR1310_PCIE_SATA2_SEL_SATA		(1 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_SATA		(1 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_SATA		(1 << 29)
+	#define SPEAR1310_SATA2_CFG_TX_CLK_EN		(1 << 27)
+	#define SPEAR1310_SATA2_CFG_RX_CLK_EN		(1 << 26)
+	#define SPEAR1310_SATA2_CFG_POWERUP_RESET	(1 << 25)
+	#define SPEAR1310_SATA2_CFG_PM_CLK_EN		(1 << 24)
+	#define SPEAR1310_SATA1_CFG_TX_CLK_EN		(1 << 23)
+	#define SPEAR1310_SATA1_CFG_RX_CLK_EN		(1 << 22)
+	#define SPEAR1310_SATA1_CFG_POWERUP_RESET	(1 << 21)
+	#define SPEAR1310_SATA1_CFG_PM_CLK_EN		(1 << 20)
+	#define SPEAR1310_SATA0_CFG_TX_CLK_EN		(1 << 19)
+	#define SPEAR1310_SATA0_CFG_RX_CLK_EN		(1 << 18)
+	#define SPEAR1310_SATA0_CFG_POWERUP_RESET	(1 << 17)
+	#define SPEAR1310_SATA0_CFG_PM_CLK_EN		(1 << 16)
+	#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1310_PCIE2_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT	(1 << 7)
+	#define SPEAR1310_PCIE1_CFG_POWERUP_RESET	(1 << 6)
+	#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN		(1 << 5)
+	#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN		(1 << 4)
+	#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT	(1 << 3)
+	#define SPEAR1310_PCIE0_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN		(1 << 1)
+	#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN		(1 << 0)
+
+	#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+	#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+			(1 << (x + 29)))
+	#define SPEAR1310_PCIE_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+			SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+	#define SPEAR1310_SATA_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+			SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1		0x3A8
+	#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT	(1 << 31)
+	#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2	(1 << 28)
+	#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)	(x << 16)
+	#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT	(1 << 15)
+	#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2	(1 << 12)
+	#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2		0x3AC
 
 enum phy_mode {
 	SATA,
@@ -181,6 +256,104 @@ static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
 		return -EINVAL;
 }
 
+static int spear1340_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+	return 0;
+}
+
+static int spear1340_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+	return 0;
+}
+
+static int spear1310_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	u32 mask, val;
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+	switch (phypriv->id) {
+	case 0:
+		mask = SPEAR1310_PCIE_CFG_MASK(0);
+		val = SPEAR1310_PCIE_CFG_VAL(0);
+		break;
+	case 1:
+		mask = SPEAR1310_PCIE_CFG_MASK(1);
+		val = SPEAR1310_PCIE_CFG_VAL(1);
+		break;
+	case 2:
+		mask = SPEAR1310_PCIE_CFG_MASK(2);
+		val = SPEAR1310_PCIE_CFG_VAL(2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG, mask, val);
+
+	return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	u32 mask;
+
+	switch (phypriv->id) {
+	case 0:
+		mask = SPEAR1310_PCIE_CFG_MASK(0);
+		break;
+	case 1:
+		mask = SPEAR1310_PCIE_CFG_MASK(1);
+		break;
+	case 2:
+		mask = SPEAR1310_PCIE_CFG_MASK(2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
+			SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+	return 0;
+}
+
+static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_pcie_miphy_init(phypriv);
+	else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+		return spear1310_pcie_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_pcie_miphy_exit(phypriv);
+	else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+		return spear1310_pcie_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
 static int miphy40lp_init(struct phy *phy)
 {
 	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
@@ -188,6 +361,8 @@ static int miphy40lp_init(struct phy *phy)
 	switch (phypriv->mode) {
 	case SATA:
 		return sata_miphy_init(phypriv);
+	case PCIE:
+		return pcie_miphy_init(phypriv);
 	default:
 		return -EINVAL;
 	}
@@ -200,6 +375,8 @@ static int miphy40lp_exit(struct phy *phy)
 	switch (phypriv->mode) {
 	case SATA:
 		return sata_miphy_exit(phypriv);
+	case PCIE:
+		return pcie_miphy_exit(phypriv);
 	default:
 		return -EINVAL;
 	}
@@ -232,6 +409,7 @@ static int miphy40lp_power_on(struct phy *phy)
 static const struct of_device_id st_miphy40lp_of_match[] = {
 	{ .compatible = "st,miphy40lp-phy" },
 	{ .compatible = "st,spear1340-miphy" },
+	{ .compatible = "st,spear1310-miphy" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
-- 
1.8.1.2


^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
@ 2014-02-06  4:44   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: linux-arm-kernel

SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
support for the same.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/phy/phy-miphy40lp.c | 178 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index cc7f45d..61e94be 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  *
  * 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
  */
 
 #include <linux/delay.h>
@@ -73,6 +74,80 @@
 	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
 			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
 			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG			0x3A4
+	#define SPEAR1310_PCIE_SATA2_SEL_PCIE		(0 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_PCIE		(0 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_PCIE		(0 << 29)
+	#define SPEAR1310_PCIE_SATA2_SEL_SATA		(1 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_SATA		(1 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_SATA		(1 << 29)
+	#define SPEAR1310_SATA2_CFG_TX_CLK_EN		(1 << 27)
+	#define SPEAR1310_SATA2_CFG_RX_CLK_EN		(1 << 26)
+	#define SPEAR1310_SATA2_CFG_POWERUP_RESET	(1 << 25)
+	#define SPEAR1310_SATA2_CFG_PM_CLK_EN		(1 << 24)
+	#define SPEAR1310_SATA1_CFG_TX_CLK_EN		(1 << 23)
+	#define SPEAR1310_SATA1_CFG_RX_CLK_EN		(1 << 22)
+	#define SPEAR1310_SATA1_CFG_POWERUP_RESET	(1 << 21)
+	#define SPEAR1310_SATA1_CFG_PM_CLK_EN		(1 << 20)
+	#define SPEAR1310_SATA0_CFG_TX_CLK_EN		(1 << 19)
+	#define SPEAR1310_SATA0_CFG_RX_CLK_EN		(1 << 18)
+	#define SPEAR1310_SATA0_CFG_POWERUP_RESET	(1 << 17)
+	#define SPEAR1310_SATA0_CFG_PM_CLK_EN		(1 << 16)
+	#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1310_PCIE2_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT	(1 << 7)
+	#define SPEAR1310_PCIE1_CFG_POWERUP_RESET	(1 << 6)
+	#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN		(1 << 5)
+	#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN		(1 << 4)
+	#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT	(1 << 3)
+	#define SPEAR1310_PCIE0_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN		(1 << 1)
+	#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN		(1 << 0)
+
+	#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+	#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+			(1 << (x + 29)))
+	#define SPEAR1310_PCIE_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+			SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+	#define SPEAR1310_SATA_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+			SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1		0x3A8
+	#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT	(1 << 31)
+	#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2	(1 << 28)
+	#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)	(x << 16)
+	#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT	(1 << 15)
+	#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2	(1 << 12)
+	#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2		0x3AC
 
 enum phy_mode {
 	SATA,
@@ -181,6 +256,104 @@ static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
 		return -EINVAL;
 }
 
+static int spear1340_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+	return 0;
+}
+
+static int spear1340_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+	return 0;
+}
+
+static int spear1310_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	u32 mask, val;
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+	switch (phypriv->id) {
+	case 0:
+		mask = SPEAR1310_PCIE_CFG_MASK(0);
+		val = SPEAR1310_PCIE_CFG_VAL(0);
+		break;
+	case 1:
+		mask = SPEAR1310_PCIE_CFG_MASK(1);
+		val = SPEAR1310_PCIE_CFG_VAL(1);
+		break;
+	case 2:
+		mask = SPEAR1310_PCIE_CFG_MASK(2);
+		val = SPEAR1310_PCIE_CFG_VAL(2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG, mask, val);
+
+	return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	u32 mask;
+
+	switch (phypriv->id) {
+	case 0:
+		mask = SPEAR1310_PCIE_CFG_MASK(0);
+		break;
+	case 1:
+		mask = SPEAR1310_PCIE_CFG_MASK(1);
+		break;
+	case 2:
+		mask = SPEAR1310_PCIE_CFG_MASK(2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
+			SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
+
+	regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+			SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+	return 0;
+}
+
+static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_pcie_miphy_init(phypriv);
+	else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+		return spear1310_pcie_miphy_init(phypriv);
+	else
+		return -EINVAL;
+}
+
+static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+		return spear1340_pcie_miphy_exit(phypriv);
+	else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+		return spear1310_pcie_miphy_exit(phypriv);
+	else
+		return -EINVAL;
+}
+
 static int miphy40lp_init(struct phy *phy)
 {
 	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
@@ -188,6 +361,8 @@ static int miphy40lp_init(struct phy *phy)
 	switch (phypriv->mode) {
 	case SATA:
 		return sata_miphy_init(phypriv);
+	case PCIE:
+		return pcie_miphy_init(phypriv);
 	default:
 		return -EINVAL;
 	}
@@ -200,6 +375,8 @@ static int miphy40lp_exit(struct phy *phy)
 	switch (phypriv->mode) {
 	case SATA:
 		return sata_miphy_exit(phypriv);
+	case PCIE:
+		return pcie_miphy_exit(phypriv);
 	default:
 		return -EINVAL;
 	}
@@ -232,6 +409,7 @@ static int miphy40lp_power_on(struct phy *phy)
 static const struct of_device_id st_miphy40lp_of_match[] = {
 	{ .compatible = "st,miphy40lp-phy" },
 	{ .compatible = "st,spear1340-miphy" },
+	{ .compatible = "st,spear1310-miphy" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
-- 
1.8.1.2

^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 7/8] pcie: SPEAr13xx: Add designware pcie support
  2014-02-06  4:44 ` Pratyush Anand
                   ` (7 preceding siblings ...)
  (?)
@ 2014-02-06  4:44 ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd
  Cc: Pratyush Anand, Mohit Kumar, Jingoo Han, Viresh Kumar,
	spear-devel, linux-pci

SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
SPEAr13xx PCIe driver based on designware controller driver.

SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
with ahci/sata pins. By default evaluation board of both controller
works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the
necessary modifications on board and enable (okay) pcie and miphy
from respective evb dtsi file.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
Cc: Arnd Bergmann <arnd@arndb.de>
---
 .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
 arch/arm/boot/dts/spear1310.dtsi                   |  57 +++
 arch/arm/boot/dts/spear1340.dtsi                   |  19 +
 arch/arm/boot/dts/spear13xx.dtsi                   |   5 +-
 arch/arm/configs/spear13xx_defconfig               |   2 +
 arch/arm/mach-spear/Kconfig                        |   1 +
 drivers/pci/host/Kconfig                           |   5 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pcie-spear13xx.c                  | 414 +++++++++++++++++++++
 9 files changed, 509 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
 create mode 100644 drivers/pci/host/pcie-spear13xx.c

diff --git a/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
new file mode 100644
index 0000000..dc8ae44
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
@@ -0,0 +1,7 @@
+Required properties:
+- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
+- pcie_is_gen1: pass <1> if forced gen1 initialization is needed to work with
+  some buggy cards else pass <0>.
+- phys		    : phandle to phy node associated with pcie controller
+- phy-names	    : must be "pcie-phy"
+- All other definitions as per generic PCI bindings
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 64e7dd5..8d7aefe 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -83,6 +83,63 @@
 			status = "disabled";
 		};
 
+		pcie0: pcie@b1000000 {
+			compatible = "st,spear1340-pcie", "snps,dw-pcie";
+			reg = <0xb1000000 0x4000>;
+			interrupts = <0 68 0x4>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0x0 0 &gic 68>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			phys = <&miphy0 1>;
+			phy-names = "pcie-phy";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+
+		pcie1: pcie@b1800000 {
+			compatible = "st,spear1340-pcie", "snps,dw-pcie";
+			reg = <0xb1800000 0x4000>;
+			interrupts = <0 69 0x4>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0x0 0 &gic 69>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			phys = <&miphy1 1>;
+			phy-names = "pcie-phy";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+
+		pcie2: pcie@b4000000 {
+			compatible = "st,spear1340-pcie", "snps,dw-pcie";
+			reg = <0xb4000000 0x4000>;
+			interrupts = <0 70 0x4>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0x0 0 &gic 70>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			phys = <&miphy2 1>;
+			phy-names = "pcie-phy";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+
 		gmac1: eth@5c400000 {
 			compatible = "st,spear600-gmac";
 			reg = <0x5c400000 0x8000>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 7e3a04b..4264067 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -49,6 +49,25 @@
 			status = "disabled";
 		};
 
+		pcie0: pcie@b1000000 {
+			compatible = "st,spear1340-pcie", "snps,dw-pcie";
+			reg = <0xb1000000 0x4000>;
+			interrupts = <0 68 0x4>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0x0 0 &gic 68>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			phys = <&miphy0 1>;
+			phy-names = "pcie-phy";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+
 		i2s-play@b2400000 {
 			compatible = "snps,designware-i2s";
 			reg = <0xb2400000 0x10000>;
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3a72508..ec7feaf 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges = <0x50000000 0x50000000 0x10000000
-			  0xb0000000 0xb0000000 0x10000000
-			  0xd0000000 0xd0000000 0x02000000
+			  0x80000000 0x80000000 0x20000000
+			  0xb0000000 0xb0000000 0x22000000
 			  0xd8000000 0xd8000000 0x01000000
 			  0xe0000000 0xe0000000 0x10000000>;
 
@@ -338,6 +338,7 @@
 				reg = <0xe07008c4 0x4>;
 				thermal_flags = <0x7000>;
 			};
+
 		};
 	};
 };
diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 1e0bb6f..96ede50 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,6 +11,8 @@ CONFIG_ARCH_SPEAR13XX=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
 CONFIG_SMP=y
 # CONFIG_SMP_ON_UP is not set
 # CONFIG_ARM_CPU_TOPOLOGY is not set
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 7e7f1b0..701b6c3 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -28,6 +28,7 @@ config ARCH_SPEAR13XX
 	select USE_OF
 	select MFD_SYSCON
 	select PHY_ST_MIPHY40LP
+	select PCI
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..df52fad 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2
 	  There are 3 internal PCI controllers available with a single
 	  built-in EHCI/OHCI host controller present on each one.
 
+config PCIE_SPEAR13XX
+	bool "STMicroelectronics SPEAr PCIe controller"
+	depends on ARCH_SPEAR13XX
+	select PCIEPORTBUS
+	select PCIE_DW
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..42a491d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..53c6094
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,414 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2014 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+	void __iomem		*app_base;
+	struct phy		*phy;
+	struct clk		*clk;
+	struct pcie_port	pp;
+	int			is_gen1;
+};
+
+struct pcie_app_reg {
+	u32	app_ctrl_0;		/*cr0*/
+	u32	app_ctrl_1;		/*cr1*/
+	u32	app_status_0;		/*cr2*/
+	u32	app_status_1;		/*cr3*/
+	u32	msg_status;		/*cr4*/
+	u32	msg_payload;		/*cr5*/
+	u32	int_sts;		/*cr6*/
+	u32	int_clr;		/*cr7*/
+	u32	int_mask;		/*cr8*/
+	u32	mst_bmisc;		/*cr9*/
+	u32	phy_ctrl;		/*cr10*/
+	u32	phy_status;		/*cr11*/
+	u32	cxpl_debug_info_0;	/*cr12*/
+	u32	cxpl_debug_info_1;	/*cr13*/
+	u32	ven_msg_ctrl_0;		/*cr14*/
+	u32	ven_msg_ctrl_1;		/*cr15*/
+	u32	ven_msg_data_0;		/*cr16*/
+	u32	ven_msg_data_1;		/*cr17*/
+	u32	ven_msi_0;		/*cr18*/
+	u32	ven_msi_1;		/*cr19*/
+	u32	mst_rmisc;		/*cr 20*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID			0
+#define TX_LANE_FLIP_EN_ID			1
+#define SYS_AUX_PWR_DET_ID			2
+#define APP_LTSSM_ENABLE_ID			3
+#define SYS_ATTEN_BUTTON_PRESSED_ID		4
+#define SYS_MRL_SENSOR_STATE_ID			5
+#define SYS_PWR_FAULT_DET_ID			6
+#define SYS_MRL_SENSOR_CHGED_ID			7
+#define SYS_PRE_DET_CHGED_ID			8
+#define SYS_CMD_CPLED_INT_ID			9
+#define APP_INIT_RST_0_ID			11
+#define APP_REQ_ENTR_L1_ID			12
+#define APP_READY_ENTR_L23_ID			13
+#define APP_REQ_EXIT_L1_ID			14
+#define DEVICE_TYPE_EP				(0 << 25)
+#define DEVICE_TYPE_LEP				(1 << 25)
+#define DEVICE_TYPE_RC				(4 << 25)
+#define SYS_INT_ID				29
+#define MISCTRL_EN_ID				30
+#define REG_TRANSLATION_ENABLE			31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID			2
+#define APPS_PM_XMT_PME_ID			5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
+#define XMLH_LTSSM_STATE_L0			0x11
+#define XMLH_LTSSM_STATE_L0S			0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define XMLH_LTSSM_STATE_L1_IDLE		0x14
+#define XMLH_LTSSM_STATE_L2_IDLE		0x15
+#define XMLH_LTSSM_STATE_L2_WAKE		0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
+#define XMLH_LTSSM_STATE_DISABLED		0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
+#define XMLH_LTSSM_STATE_MASK			0x3F
+#define XMLH_LINK_UP				(1 << 6)
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID				18
+
+/*CR6*/
+#define INTA_CTRL_INT				(1 << 7)
+#define INTB_CTRL_INT				(1 << 8)
+#define INTC_CTRL_INT				(1 << 9)
+#define INTD_CTRL_INT				(1 << 10)
+#define MSI_CTRL_INT				(1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID				11
+#define VEN_MSI_FUN_NUM_ID			8
+#define VEN_MSI_TC_ID				5
+#define VEN_MSI_VECTOR_ID			0
+#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET			0x70
+
+#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+	u32 val;
+	int count = 0;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+	if (dw_pcie_link_up(pp)) {
+		dev_err(pp->dev, "Link already up\n");
+		return 0;
+	}
+
+	/* setup root complex */
+	dw_pcie_setup_rc(pp);
+
+	/*
+	 * this controller support only 128 bytes read size, however its
+	 * default value in capability register is 512 bytes. So force
+	 * it to 128 here.
+	 */
+	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+	val &= ~PCI_EXP_DEVCTL_READRQ;
+	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+	/* program vid and did for RC */
+	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+	/*
+	 * if is_gen1 is set then handle it, so that some buggy card
+	 * also works
+	 */
+	if (spear13xx_pcie->is_gen1) {
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCAP, 4, val);
+		}
+
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCTL2, 4, val);
+		}
+	}
+
+	/* enable ltssm */
+	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+			| (1 << APP_LTSSM_ENABLE_ID)
+			| ((u32)1 << REG_TRANSLATION_ENABLE),
+			&app_reg->app_ctrl_0);
+
+	/* check if the link is up or not */
+	while (!dw_pcie_link_up(pp)) {
+		mdelay(100);
+		count++;
+		if (count == 10) {
+			dev_err(pp->dev, "Link Fail\n");
+			return -EINVAL;
+		}
+	}
+	dev_info(pp->dev, "Link up\n");
+
+	return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+	struct pcie_port *pp = arg;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	unsigned int status;
+
+	status = readl(&app_reg->int_sts);
+
+	if (status & MSI_CTRL_INT) {
+		if (!IS_ENABLED(CONFIG_PCI_MSI))
+			BUG();
+		dw_handle_msi_irq(pp);
+	}
+
+	writel(status, &app_reg->int_clr);
+
+	return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	/* Enable MSI interrupt */
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		dw_pcie_msi_init(pp);
+		writel(readl(&app_reg->int_mask) |
+				MSI_CTRL_INT, &app_reg->int_mask);
+	}
+
+	return;
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+		return 1;
+
+	return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+	spear13xx_pcie_establish_link(pp);
+	spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+	.link_up = spear13xx_pcie_link_up,
+	.host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	pp->irq = platform_get_irq(pdev, 0);
+	if (!pp->irq) {
+		dev_err(dev, "failed to get irq\n");
+		return -ENODEV;
+	}
+	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
+				IRQF_SHARED, "spear1340-pcie", pp);
+	if (ret) {
+		dev_err(dev, "failed to request irq\n");
+		return ret;
+	}
+
+	pp->root_bus_nr = -1;
+	pp->ops = &spear13xx_pcie_host_ops;
+
+	spin_lock_init(&pp->conf_lock);
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(dev, "failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie;
+	struct pcie_port *pp;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *dbi_base;
+	int ret;
+
+	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie),
+				GFP_KERNEL);
+	if (!spear13xx_pcie) {
+		dev_err(dev, "no memory for SPEAr13xx pcie\n");
+		return -ENOMEM;
+	}
+
+	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
+	if (IS_ERR(spear13xx_pcie->phy)) {
+		ret = PTR_ERR(spear13xx_pcie->phy);
+		switch (ret) {
+		case -EPROBE_DEFER:
+			dev_info(dev, "probe deferred\n");
+			return ret;
+		default:
+			dev_err(dev, "couldn't get pcie-phy\n");
+			return ret;
+		}
+	}
+
+	phy_init(spear13xx_pcie->phy);
+
+	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(spear13xx_pcie->clk)) {
+		dev_err(dev, "couldn't get clk for pcie\n");
+		return PTR_ERR(spear13xx_pcie->clk);
+	}
+	ret = clk_prepare_enable(spear13xx_pcie->clk);
+	if (ret) {
+		dev_err(dev, "couldn't enable clk for pcie\n");
+		return ret;
+	}
+
+	pp = &spear13xx_pcie->pp;
+
+	pp->dev = dev;
+
+	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
+	if (IS_ERR(pp->dbi_base)) {
+		dev_err(dev, "couldn't remap dbi base\n");
+		ret = PTR_ERR(pp->dbi_base);
+		goto fail_clk;
+	}
+	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+	of_property_read_u32(np, "pcie_is_gen1", &spear13xx_pcie->is_gen1);
+
+	ret = add_pcie_port(pp, pdev);
+	if (ret < 0)
+		goto fail_clk;
+
+	platform_set_drvdata(pdev, spear13xx_pcie);
+	return 0;
+
+fail_clk:
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	phy_exit(spear13xx_pcie->phy);
+
+	return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+	{ .compatible = "st,spear1340-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+	.remove		= __exit_p(spear13xx_pcie_remove),
+	.driver = {
+		.name	= "spear-pcie",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+	},
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+
+	return platform_driver_probe(&spear13xx_pcie_driver,
+				spear13xx_pcie_probe);
+}
+module_init(pcie_init);
+
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_LICENSE("GPL v2");
-- 
1.8.1.2


^ permalink raw reply related	[flat|nested] 49+ messages in thread

* [PATCH V4 8/8] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
  2014-02-06  4:44 ` Pratyush Anand
                   ` (8 preceding siblings ...)
  (?)
@ 2014-02-06  4:44 ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  4:44 UTC (permalink / raw)
  To: arnd; +Cc: Mohit Kumar, Pratyush Anand, linux-pci

From: Mohit Kumar <mohit.kumar@st.com>

Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci@vger.kernel.org
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b2cf5cf..ebdca89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6596,6 +6596,12 @@ L:	linux-pci@vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/*designware*
 
+PCIE DRIVER FOR ST SPEAR13XX
+M:	Mohit Kumar <mohit.kumar@st.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	drivers/pci/host/pcie-spear13xx.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia@lists.infradead.org
-- 
1.8.1.2


^ permalink raw reply related	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
  2014-02-06  4:44   ` Pratyush Anand
  (?)
@ 2014-02-06  6:01     ` Kishon Vijay Abraham I
  -1 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:01 UTC (permalink / raw)
  To: Pratyush Anand, arnd
  Cc: spear-devel, linux-arm-kernel, devicetree, linux-kernel

Hi,

On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> skeleton support for the same.
> 
> Currently phy ops are returning -EINVAL. They can be elaborated
> depending on the SOC being supported in future.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel@list.st.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
>  drivers/phy/Kconfig                                |   6 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
>  4 files changed, 193 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>  create mode 100644 drivers/phy/phy-miphy40lp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..d0c7096
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,12 @@
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> +	Other supported soc specific compatible:
> +		"st,spear1310-miphy"
> +		"st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> +	- 1st cell: phandle to the phy node.
> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> +	  and 2 for Super Speed USB.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index afa2354..2f58993 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>  	help
>  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
>  
> +config PHY_ST_MIPHY40LP
> +	tristate "ST MIPHY 40LP driver"
> +	help
> +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> +	select GENERIC_PHY
> +
>  endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..c061091 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> new file mode 100644
> index 0000000..d478c14
> --- /dev/null
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -0,0 +1,174 @@
> +/*
> + * ST MiPHY-40LP PHY driver
> + *
> + * Copyright (C) 2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +enum phy_mode {
> +	SATA,
> +	PCIE,
> +	SS_USB,
> +};
> +
> +struct st_miphy40lp_priv {
> +	/* regmap for any soc specific misc registers */
> +	struct regmap		*misc;
> +	/* phy struct pointer */
> +	struct phy		*phy;
> +	/* device node pointer */
> +	struct device_node	*np;
> +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> +	enum phy_mode		mode;
> +	/* instance id of this phy */
> +	u32			id;
> +};
> +
> +static int miphy40lp_init(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_exit(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_power_off(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_power_on(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static const struct of_device_id st_miphy40lp_of_match[] = {
> +	{ .compatible = "st,miphy40lp-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> +
> +static struct phy_ops st_miphy40lp_ops = {
> +	.init = miphy40lp_init,
> +	.exit = miphy40lp_exit,
> +	.power_off = miphy40lp_power_off,
> +	.power_on = miphy40lp_power_on,
> +	.owner		= THIS_MODULE,

Would prefer to either align all the fields or align none. Here only owner is
aligned.
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int miphy40lp_suspend(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_resume(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> +		miphy40lp_resume);
> +
> +static struct phy *st_miphy40lp_xlate(struct device *dev,
> +					struct of_phandle_args *args)
> +{
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (args->args_count < 1) {
> +		dev_err(dev, "DT did not pass correct no of args\n");
> +		return NULL;
> +	}
> +
> +	phypriv->mode = args->args[0];
> +
> +	return phypriv->phy;
> +}
> +
> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct st_miphy40lp_priv *phypriv;
> +	struct phy_provider *phy_provider;
> +
> +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> +	if (!phypriv) {
> +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	phypriv->np = dev->of_node;
> +
> +	phypriv->misc =
> +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> +	if (IS_ERR(phypriv->misc)) {
> +		dev_err(dev, "failed to find misc regmap\n");
> +		return PTR_ERR(phypriv->misc);
> +	}
> +
> +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> +		dev_err(dev, "failed to find phy id\n");
> +		return -EINVAL;
> +	}
Do we really need this phy id? How is it being used?

> +
> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "failed to register phy provider\n");
> +		return PTR_ERR(phy_provider);
> +	}

phy_provider_register should be the last step in registering the PHY. Or your
PHY call backs can be called before you create the PHY. Btw in your case you
should call dev_set_drvdata before doing phy_provider_register.
> +
> +	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> +	if (IS_ERR(phypriv->phy)) {
> +		dev_err(dev, "failed to create SATA PCIe PHY\n");
> +		return PTR_ERR(phypriv->phy);
> +	}
> +
> +	dev_set_drvdata(dev, phypriv);
> +	phy_set_drvdata(phypriv->phy, phypriv);
> +
> +	return 0;
> +}
> +
> +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}

I think you can remove this empty 'remove' callback.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:01     ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:01 UTC (permalink / raw)
  To: Pratyush Anand, arnd
  Cc: devicetree, spear-devel, linux-kernel, linux-arm-kernel

Hi,

On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> skeleton support for the same.
> 
> Currently phy ops are returning -EINVAL. They can be elaborated
> depending on the SOC being supported in future.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel@list.st.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
>  drivers/phy/Kconfig                                |   6 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
>  4 files changed, 193 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>  create mode 100644 drivers/phy/phy-miphy40lp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..d0c7096
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,12 @@
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> +	Other supported soc specific compatible:
> +		"st,spear1310-miphy"
> +		"st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> +	- 1st cell: phandle to the phy node.
> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> +	  and 2 for Super Speed USB.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index afa2354..2f58993 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>  	help
>  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
>  
> +config PHY_ST_MIPHY40LP
> +	tristate "ST MIPHY 40LP driver"
> +	help
> +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> +	select GENERIC_PHY
> +
>  endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..c061091 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> new file mode 100644
> index 0000000..d478c14
> --- /dev/null
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -0,0 +1,174 @@
> +/*
> + * ST MiPHY-40LP PHY driver
> + *
> + * Copyright (C) 2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +enum phy_mode {
> +	SATA,
> +	PCIE,
> +	SS_USB,
> +};
> +
> +struct st_miphy40lp_priv {
> +	/* regmap for any soc specific misc registers */
> +	struct regmap		*misc;
> +	/* phy struct pointer */
> +	struct phy		*phy;
> +	/* device node pointer */
> +	struct device_node	*np;
> +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> +	enum phy_mode		mode;
> +	/* instance id of this phy */
> +	u32			id;
> +};
> +
> +static int miphy40lp_init(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_exit(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_power_off(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_power_on(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static const struct of_device_id st_miphy40lp_of_match[] = {
> +	{ .compatible = "st,miphy40lp-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> +
> +static struct phy_ops st_miphy40lp_ops = {
> +	.init = miphy40lp_init,
> +	.exit = miphy40lp_exit,
> +	.power_off = miphy40lp_power_off,
> +	.power_on = miphy40lp_power_on,
> +	.owner		= THIS_MODULE,

Would prefer to either align all the fields or align none. Here only owner is
aligned.
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int miphy40lp_suspend(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_resume(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> +		miphy40lp_resume);
> +
> +static struct phy *st_miphy40lp_xlate(struct device *dev,
> +					struct of_phandle_args *args)
> +{
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (args->args_count < 1) {
> +		dev_err(dev, "DT did not pass correct no of args\n");
> +		return NULL;
> +	}
> +
> +	phypriv->mode = args->args[0];
> +
> +	return phypriv->phy;
> +}
> +
> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct st_miphy40lp_priv *phypriv;
> +	struct phy_provider *phy_provider;
> +
> +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> +	if (!phypriv) {
> +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	phypriv->np = dev->of_node;
> +
> +	phypriv->misc =
> +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> +	if (IS_ERR(phypriv->misc)) {
> +		dev_err(dev, "failed to find misc regmap\n");
> +		return PTR_ERR(phypriv->misc);
> +	}
> +
> +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> +		dev_err(dev, "failed to find phy id\n");
> +		return -EINVAL;
> +	}
Do we really need this phy id? How is it being used?

> +
> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "failed to register phy provider\n");
> +		return PTR_ERR(phy_provider);
> +	}

phy_provider_register should be the last step in registering the PHY. Or your
PHY call backs can be called before you create the PHY. Btw in your case you
should call dev_set_drvdata before doing phy_provider_register.
> +
> +	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> +	if (IS_ERR(phypriv->phy)) {
> +		dev_err(dev, "failed to create SATA PCIe PHY\n");
> +		return PTR_ERR(phypriv->phy);
> +	}
> +
> +	dev_set_drvdata(dev, phypriv);
> +	phy_set_drvdata(phypriv->phy, phypriv);
> +
> +	return 0;
> +}
> +
> +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}

I think you can remove this empty 'remove' callback.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:01     ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:01 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> skeleton support for the same.
> 
> Currently phy ops are returning -EINVAL. They can be elaborated
> depending on the SOC being supported in future.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
>  drivers/phy/Kconfig                                |   6 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
>  4 files changed, 193 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>  create mode 100644 drivers/phy/phy-miphy40lp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..d0c7096
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,12 @@
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> +	Other supported soc specific compatible:
> +		"st,spear1310-miphy"
> +		"st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> +	- 1st cell: phandle to the phy node.
> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> +	  and 2 for Super Speed USB.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index afa2354..2f58993 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>  	help
>  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
>  
> +config PHY_ST_MIPHY40LP
> +	tristate "ST MIPHY 40LP driver"
> +	help
> +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> +	select GENERIC_PHY
> +
>  endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..c061091 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> new file mode 100644
> index 0000000..d478c14
> --- /dev/null
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -0,0 +1,174 @@
> +/*
> + * ST MiPHY-40LP PHY driver
> + *
> + * Copyright (C) 2014 ST Microelectronics
> + * Pratyush Anand <pratyush.anand@st.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +enum phy_mode {
> +	SATA,
> +	PCIE,
> +	SS_USB,
> +};
> +
> +struct st_miphy40lp_priv {
> +	/* regmap for any soc specific misc registers */
> +	struct regmap		*misc;
> +	/* phy struct pointer */
> +	struct phy		*phy;
> +	/* device node pointer */
> +	struct device_node	*np;
> +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> +	enum phy_mode		mode;
> +	/* instance id of this phy */
> +	u32			id;
> +};
> +
> +static int miphy40lp_init(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_exit(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_power_off(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_power_on(struct phy *phy)
> +{
> +	return -EINVAL;
> +}
> +
> +static const struct of_device_id st_miphy40lp_of_match[] = {
> +	{ .compatible = "st,miphy40lp-phy" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> +
> +static struct phy_ops st_miphy40lp_ops = {
> +	.init = miphy40lp_init,
> +	.exit = miphy40lp_exit,
> +	.power_off = miphy40lp_power_off,
> +	.power_on = miphy40lp_power_on,
> +	.owner		= THIS_MODULE,

Would prefer to either align all the fields or align none. Here only owner is
aligned.
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int miphy40lp_suspend(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +
> +static int miphy40lp_resume(struct device *dev)
> +{
> +	return -EINVAL;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> +		miphy40lp_resume);
> +
> +static struct phy *st_miphy40lp_xlate(struct device *dev,
> +					struct of_phandle_args *args)
> +{
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (args->args_count < 1) {
> +		dev_err(dev, "DT did not pass correct no of args\n");
> +		return NULL;
> +	}
> +
> +	phypriv->mode = args->args[0];
> +
> +	return phypriv->phy;
> +}
> +
> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct st_miphy40lp_priv *phypriv;
> +	struct phy_provider *phy_provider;
> +
> +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> +	if (!phypriv) {
> +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	phypriv->np = dev->of_node;
> +
> +	phypriv->misc =
> +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> +	if (IS_ERR(phypriv->misc)) {
> +		dev_err(dev, "failed to find misc regmap\n");
> +		return PTR_ERR(phypriv->misc);
> +	}
> +
> +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> +		dev_err(dev, "failed to find phy id\n");
> +		return -EINVAL;
> +	}
Do we really need this phy id? How is it being used?

> +
> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> +	if (IS_ERR(phy_provider)) {
> +		dev_err(dev, "failed to register phy provider\n");
> +		return PTR_ERR(phy_provider);
> +	}

phy_provider_register should be the last step in registering the PHY. Or your
PHY call backs can be called before you create the PHY. Btw in your case you
should call dev_set_drvdata before doing phy_provider_register.
> +
> +	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> +	if (IS_ERR(phypriv->phy)) {
> +		dev_err(dev, "failed to create SATA PCIe PHY\n");
> +		return PTR_ERR(phypriv->phy);
> +	}
> +
> +	dev_set_drvdata(dev, phypriv);
> +	phy_set_drvdata(phypriv->phy, phypriv);
> +
> +	return 0;
> +}
> +
> +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> +{
> +	return 0;
> +}

I think you can remove this empty 'remove' callback.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:14       ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  6:14 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd, spear-devel, linux-arm-kernel, devicetree, linux-kernel

Hi Kishon,

On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> > 
> > Currently phy ops are returning -EINVAL. They can be elaborated
> > depending on the SOC being supported in future.
> > 
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> >  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
> >  drivers/phy/Kconfig                                |   6 +
> >  drivers/phy/Makefile                               |   1 +
> >  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
> >  4 files changed, 193 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> >  create mode 100644 drivers/phy/phy-miphy40lp.c
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..d0c7096
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,12 @@
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > +	Other supported soc specific compatible:
> > +		"st,spear1310-miphy"
> > +		"st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > +	- 1st cell: phandle to the phy node.
> > +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > +	  and 2 for Super Speed USB.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index afa2354..2f58993 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> >  	help
> >  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
> >  
> > +config PHY_ST_MIPHY40LP
> > +	tristate "ST MIPHY 40LP driver"
> > +	help
> > +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> > +	select GENERIC_PHY
> > +
> >  endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index b57c253..c061091 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> >  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
> >  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
> >  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> > +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > new file mode 100644
> > index 0000000..d478c14
> > --- /dev/null
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * ST MiPHY-40LP PHY driver
> > + *
> > + * Copyright (C) 2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand@st.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +enum phy_mode {
> > +	SATA,
> > +	PCIE,
> > +	SS_USB,
> > +};
> > +
> > +struct st_miphy40lp_priv {
> > +	/* regmap for any soc specific misc registers */
> > +	struct regmap		*misc;
> > +	/* phy struct pointer */
> > +	struct phy		*phy;
> > +	/* device node pointer */
> > +	struct device_node	*np;
> > +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> > +	enum phy_mode		mode;
> > +	/* instance id of this phy */
> > +	u32			id;
> > +};
> > +
> > +static int miphy40lp_init(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_exit(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_off(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_on(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id st_miphy40lp_of_match[] = {
> > +	{ .compatible = "st,miphy40lp-phy" },
> > +	{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > +
> > +static struct phy_ops st_miphy40lp_ops = {
> > +	.init = miphy40lp_init,
> > +	.exit = miphy40lp_exit,
> > +	.power_off = miphy40lp_power_off,
> > +	.power_on = miphy40lp_power_on,
> > +	.owner		= THIS_MODULE,
> 
> Would prefer to either align all the fields or align none. Here only owner is
> aligned.

ok.

> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int miphy40lp_suspend(struct device *dev)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_resume(struct device *dev)
> > +{
> > +	return -EINVAL;
> > +}
> > +#endif
> > +
> > +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> > +		miphy40lp_resume);
> > +
> > +static struct phy *st_miphy40lp_xlate(struct device *dev,
> > +					struct of_phandle_args *args)
> > +{
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (args->args_count < 1) {
> > +		dev_err(dev, "DT did not pass correct no of args\n");
> > +		return NULL;
> > +	}
> > +
> > +	phypriv->mode = args->args[0];
> > +
> > +	return phypriv->phy;
> > +}
> > +
> > +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct st_miphy40lp_priv *phypriv;
> > +	struct phy_provider *phy_provider;
> > +
> > +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> > +	if (!phypriv) {
> > +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	phypriv->np = dev->of_node;
> > +
> > +	phypriv->misc =
> > +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> > +	if (IS_ERR(phypriv->misc)) {
> > +		dev_err(dev, "failed to find misc regmap\n");
> > +		return PTR_ERR(phypriv->misc);
> > +	}
> > +
> > +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> > +		dev_err(dev, "failed to find phy id\n");
> > +		return -EINVAL;
> > +	}
> Do we really need this phy id? How is it being used?

Yes , it is being used by patch 6/8.

> 
> > +
> > +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> > +	if (IS_ERR(phy_provider)) {
> > +		dev_err(dev, "failed to register phy provider\n");
> > +		return PTR_ERR(phy_provider);
> > +	}
> 
> phy_provider_register should be the last step in registering the PHY. Or your
> PHY call backs can be called before you create the PHY. Btw in your case you

But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
other did it same way. First phy_provider_register and then
phy_create.

> should call dev_set_drvdata before doing phy_provider_register.

yes, I need to correct it.

> > +
> > +	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> > +	if (IS_ERR(phypriv->phy)) {
> > +		dev_err(dev, "failed to create SATA PCIe PHY\n");
> > +		return PTR_ERR(phypriv->phy);
> > +	}
> > +
> > +	dev_set_drvdata(dev, phypriv);
> > +	phy_set_drvdata(phypriv->phy, phypriv);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> > +{
> > +	return 0;
> > +}
> 
> I think you can remove this empty 'remove' callback.

Yaa.. Can be removed.

Rgds
Pratyush
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:14       ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  6:14 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd-r2nGTMty4D4, spear-devel,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

Hi Kishon,

On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> > 
> > Currently phy ops are returning -EINVAL. They can be elaborated
> > depending on the SOC being supported in future.
> > 
> > Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > Tested-by: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> > Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> > Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> > Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> > Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > ---
> >  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
> >  drivers/phy/Kconfig                                |   6 +
> >  drivers/phy/Makefile                               |   1 +
> >  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
> >  4 files changed, 193 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> >  create mode 100644 drivers/phy/phy-miphy40lp.c
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..d0c7096
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,12 @@
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > +	Other supported soc specific compatible:
> > +		"st,spear1310-miphy"
> > +		"st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > +	- 1st cell: phandle to the phy node.
> > +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > +	  and 2 for Super Speed USB.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index afa2354..2f58993 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> >  	help
> >  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
> >  
> > +config PHY_ST_MIPHY40LP
> > +	tristate "ST MIPHY 40LP driver"
> > +	help
> > +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> > +	select GENERIC_PHY
> > +
> >  endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index b57c253..c061091 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> >  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
> >  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
> >  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> > +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > new file mode 100644
> > index 0000000..d478c14
> > --- /dev/null
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * ST MiPHY-40LP PHY driver
> > + *
> > + * Copyright (C) 2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +enum phy_mode {
> > +	SATA,
> > +	PCIE,
> > +	SS_USB,
> > +};
> > +
> > +struct st_miphy40lp_priv {
> > +	/* regmap for any soc specific misc registers */
> > +	struct regmap		*misc;
> > +	/* phy struct pointer */
> > +	struct phy		*phy;
> > +	/* device node pointer */
> > +	struct device_node	*np;
> > +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> > +	enum phy_mode		mode;
> > +	/* instance id of this phy */
> > +	u32			id;
> > +};
> > +
> > +static int miphy40lp_init(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_exit(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_off(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_on(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id st_miphy40lp_of_match[] = {
> > +	{ .compatible = "st,miphy40lp-phy" },
> > +	{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > +
> > +static struct phy_ops st_miphy40lp_ops = {
> > +	.init = miphy40lp_init,
> > +	.exit = miphy40lp_exit,
> > +	.power_off = miphy40lp_power_off,
> > +	.power_on = miphy40lp_power_on,
> > +	.owner		= THIS_MODULE,
> 
> Would prefer to either align all the fields or align none. Here only owner is
> aligned.

ok.

> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int miphy40lp_suspend(struct device *dev)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_resume(struct device *dev)
> > +{
> > +	return -EINVAL;
> > +}
> > +#endif
> > +
> > +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> > +		miphy40lp_resume);
> > +
> > +static struct phy *st_miphy40lp_xlate(struct device *dev,
> > +					struct of_phandle_args *args)
> > +{
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (args->args_count < 1) {
> > +		dev_err(dev, "DT did not pass correct no of args\n");
> > +		return NULL;
> > +	}
> > +
> > +	phypriv->mode = args->args[0];
> > +
> > +	return phypriv->phy;
> > +}
> > +
> > +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct st_miphy40lp_priv *phypriv;
> > +	struct phy_provider *phy_provider;
> > +
> > +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> > +	if (!phypriv) {
> > +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	phypriv->np = dev->of_node;
> > +
> > +	phypriv->misc =
> > +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> > +	if (IS_ERR(phypriv->misc)) {
> > +		dev_err(dev, "failed to find misc regmap\n");
> > +		return PTR_ERR(phypriv->misc);
> > +	}
> > +
> > +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> > +		dev_err(dev, "failed to find phy id\n");
> > +		return -EINVAL;
> > +	}
> Do we really need this phy id? How is it being used?

Yes , it is being used by patch 6/8.

> 
> > +
> > +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> > +	if (IS_ERR(phy_provider)) {
> > +		dev_err(dev, "failed to register phy provider\n");
> > +		return PTR_ERR(phy_provider);
> > +	}
> 
> phy_provider_register should be the last step in registering the PHY. Or your
> PHY call backs can be called before you create the PHY. Btw in your case you

But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
other did it same way. First phy_provider_register and then
phy_create.

> should call dev_set_drvdata before doing phy_provider_register.

yes, I need to correct it.

> > +
> > +	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> > +	if (IS_ERR(phypriv->phy)) {
> > +		dev_err(dev, "failed to create SATA PCIe PHY\n");
> > +		return PTR_ERR(phypriv->phy);
> > +	}
> > +
> > +	dev_set_drvdata(dev, phypriv);
> > +	phy_set_drvdata(phypriv->phy, phypriv);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> > +{
> > +	return 0;
> > +}
> 
> I think you can remove this empty 'remove' callback.

Yaa.. Can be removed.

Rgds
Pratyush
> 
> Thanks
> Kishon
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^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:14       ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  6:14 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Kishon,

On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> > 
> > Currently phy ops are returning -EINVAL. They can be elaborated
> > depending on the SOC being supported in future.
> > 
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> >  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
> >  drivers/phy/Kconfig                                |   6 +
> >  drivers/phy/Makefile                               |   1 +
> >  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
> >  4 files changed, 193 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> >  create mode 100644 drivers/phy/phy-miphy40lp.c
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..d0c7096
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,12 @@
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > +	Other supported soc specific compatible:
> > +		"st,spear1310-miphy"
> > +		"st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > +	- 1st cell: phandle to the phy node.
> > +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > +	  and 2 for Super Speed USB.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index afa2354..2f58993 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> >  	help
> >  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
> >  
> > +config PHY_ST_MIPHY40LP
> > +	tristate "ST MIPHY 40LP driver"
> > +	help
> > +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> > +	select GENERIC_PHY
> > +
> >  endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index b57c253..c061091 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
> >  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
> >  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
> >  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
> > +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > new file mode 100644
> > index 0000000..d478c14
> > --- /dev/null
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * ST MiPHY-40LP PHY driver
> > + *
> > + * Copyright (C) 2014 ST Microelectronics
> > + * Pratyush Anand <pratyush.anand@st.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +enum phy_mode {
> > +	SATA,
> > +	PCIE,
> > +	SS_USB,
> > +};
> > +
> > +struct st_miphy40lp_priv {
> > +	/* regmap for any soc specific misc registers */
> > +	struct regmap		*misc;
> > +	/* phy struct pointer */
> > +	struct phy		*phy;
> > +	/* device node pointer */
> > +	struct device_node	*np;
> > +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> > +	enum phy_mode		mode;
> > +	/* instance id of this phy */
> > +	u32			id;
> > +};
> > +
> > +static int miphy40lp_init(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_exit(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_off(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_on(struct phy *phy)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id st_miphy40lp_of_match[] = {
> > +	{ .compatible = "st,miphy40lp-phy" },
> > +	{ },
> > +};
> > +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > +
> > +static struct phy_ops st_miphy40lp_ops = {
> > +	.init = miphy40lp_init,
> > +	.exit = miphy40lp_exit,
> > +	.power_off = miphy40lp_power_off,
> > +	.power_on = miphy40lp_power_on,
> > +	.owner		= THIS_MODULE,
> 
> Would prefer to either align all the fields or align none. Here only owner is
> aligned.

ok.

> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int miphy40lp_suspend(struct device *dev)
> > +{
> > +	return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_resume(struct device *dev)
> > +{
> > +	return -EINVAL;
> > +}
> > +#endif
> > +
> > +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> > +		miphy40lp_resume);
> > +
> > +static struct phy *st_miphy40lp_xlate(struct device *dev,
> > +					struct of_phandle_args *args)
> > +{
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (args->args_count < 1) {
> > +		dev_err(dev, "DT did not pass correct no of args\n");
> > +		return NULL;
> > +	}
> > +
> > +	phypriv->mode = args->args[0];
> > +
> > +	return phypriv->phy;
> > +}
> > +
> > +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> > +{
> > +	struct device *dev = &pdev->dev;
> > +	struct st_miphy40lp_priv *phypriv;
> > +	struct phy_provider *phy_provider;
> > +
> > +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> > +	if (!phypriv) {
> > +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	phypriv->np = dev->of_node;
> > +
> > +	phypriv->misc =
> > +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> > +	if (IS_ERR(phypriv->misc)) {
> > +		dev_err(dev, "failed to find misc regmap\n");
> > +		return PTR_ERR(phypriv->misc);
> > +	}
> > +
> > +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> > +		dev_err(dev, "failed to find phy id\n");
> > +		return -EINVAL;
> > +	}
> Do we really need this phy id? How is it being used?

Yes , it is being used by patch 6/8.

> 
> > +
> > +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> > +	if (IS_ERR(phy_provider)) {
> > +		dev_err(dev, "failed to register phy provider\n");
> > +		return PTR_ERR(phy_provider);
> > +	}
> 
> phy_provider_register should be the last step in registering the PHY. Or your
> PHY call backs can be called before you create the PHY. Btw in your case you

But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
other did it same way. First phy_provider_register and then
phy_create.

> should call dev_set_drvdata before doing phy_provider_register.

yes, I need to correct it.

> > +
> > +	phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> > +	if (IS_ERR(phypriv->phy)) {
> > +		dev_err(dev, "failed to create SATA PCIe PHY\n");
> > +		return PTR_ERR(phypriv->phy);
> > +	}
> > +
> > +	dev_set_drvdata(dev, phypriv);
> > +	phy_set_drvdata(phypriv->phy, phypriv);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> > +{
> > +	return 0;
> > +}
> 
> I think you can remove this empty 'remove' callback.

Yaa.. Can be removed.

Rgds
Pratyush
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
  2014-02-06  6:14       ` Pratyush Anand
  (?)
@ 2014-02-06  6:23         ` Kishon Vijay Abraham I
  -1 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:23 UTC (permalink / raw)
  To: Pratyush Anand
  Cc: arnd, spear-devel, linux-arm-kernel, devicetree, linux-kernel

Hi,

On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> Hi Kishon,
> 
> On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
>>> skeleton support for the same.
>>>
>>> Currently phy ops are returning -EINVAL. They can be elaborated
>>> depending on the SOC being supported in future.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel@list.st.com
>>> Cc: linux-arm-kernel@lists.infradead.org
>>> Cc: devicetree@vger.kernel.org
>>> Cc: linux-kernel@vger.kernel.org
>>> ---
>>>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
>>>  drivers/phy/Kconfig                                |   6 +
>>>  drivers/phy/Makefile                               |   1 +
>>>  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
>>>  4 files changed, 193 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>>  create mode 100644 drivers/phy/phy-miphy40lp.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> new file mode 100644
>>> index 0000000..d0c7096
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> @@ -0,0 +1,12 @@
>>> +Required properties:
>>> +- compatible : should be "st,miphy40lp-phy"
>>> +	Other supported soc specific compatible:
>>> +		"st,spear1310-miphy"
>>> +		"st,spear1340-miphy"
>>> +- reg : offset and length of the PHY register set.
>>> +- misc: phandle for the syscon node to access misc registers
>>> +- phy-id: Instance id of the phy.
>>> +- #phy-cells : from the generic PHY bindings, must be 1.
>>> +	- 1st cell: phandle to the phy node.
>>> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
>>> +	  and 2 for Super Speed USB.
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index afa2354..2f58993 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>>>  	help
>>>  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
>>>  
>>> +config PHY_ST_MIPHY40LP
>>> +	tristate "ST MIPHY 40LP driver"
>>> +	help
>>> +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
>>> +	select GENERIC_PHY
>>> +
>>>  endmenu
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index b57c253..c061091 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>>>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>>>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>>>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
>>> +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> new file mode 100644
>>> index 0000000..d478c14
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -0,0 +1,174 @@
>>> +/*
>>> + * ST MiPHY-40LP PHY driver
>>> + *
>>> + * Copyright (C) 2014 ST Microelectronics
>>> + * Pratyush Anand <pratyush.anand@st.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include <linux/delay.h>
>>> +#include <linux/dma-mapping.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +enum phy_mode {
>>> +	SATA,
>>> +	PCIE,
>>> +	SS_USB,
>>> +};
>>> +
>>> +struct st_miphy40lp_priv {
>>> +	/* regmap for any soc specific misc registers */
>>> +	struct regmap		*misc;
>>> +	/* phy struct pointer */
>>> +	struct phy		*phy;
>>> +	/* device node pointer */
>>> +	struct device_node	*np;
>>> +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
>>> +	enum phy_mode		mode;
>>> +	/* instance id of this phy */
>>> +	u32			id;
>>> +};
>>> +
>>> +static int miphy40lp_init(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_exit(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_off(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_on(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static const struct of_device_id st_miphy40lp_of_match[] = {
>>> +	{ .compatible = "st,miphy40lp-phy" },
>>> +	{ },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
>>> +
>>> +static struct phy_ops st_miphy40lp_ops = {
>>> +	.init = miphy40lp_init,
>>> +	.exit = miphy40lp_exit,
>>> +	.power_off = miphy40lp_power_off,
>>> +	.power_on = miphy40lp_power_on,
>>> +	.owner		= THIS_MODULE,
>>
>> Would prefer to either align all the fields or align none. Here only owner is
>> aligned.
> 
> ok.
> 
>>> +};
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int miphy40lp_suspend(struct device *dev)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_resume(struct device *dev)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +#endif
>>> +
>>> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
>>> +		miphy40lp_resume);
>>> +
>>> +static struct phy *st_miphy40lp_xlate(struct device *dev,
>>> +					struct of_phandle_args *args)
>>> +{
>>> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
>>> +
>>> +	if (args->args_count < 1) {
>>> +		dev_err(dev, "DT did not pass correct no of args\n");
>>> +		return NULL;
>>> +	}
>>> +
>>> +	phypriv->mode = args->args[0];
>>> +
>>> +	return phypriv->phy;
>>> +}
>>> +
>>> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
>>> +{
>>> +	struct device *dev = &pdev->dev;
>>> +	struct st_miphy40lp_priv *phypriv;
>>> +	struct phy_provider *phy_provider;
>>> +
>>> +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
>>> +	if (!phypriv) {
>>> +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
>>> +		return -ENOMEM;
>>> +	}
>>> +
>>> +	phypriv->np = dev->of_node;
>>> +
>>> +	phypriv->misc =
>>> +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
>>> +	if (IS_ERR(phypriv->misc)) {
>>> +		dev_err(dev, "failed to find misc regmap\n");
>>> +		return PTR_ERR(phypriv->misc);
>>> +	}
>>> +
>>> +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
>>> +		dev_err(dev, "failed to find phy id\n");
>>> +		return -EINVAL;
>>> +	}
>> Do we really need this phy id? How is it being used?
> 
> Yes , it is being used by patch 6/8.

Alright.
> 
>>
>>> +
>>> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
>>> +	if (IS_ERR(phy_provider)) {
>>> +		dev_err(dev, "failed to register phy provider\n");
>>> +		return PTR_ERR(phy_provider);
>>> +	}
>>
>> phy_provider_register should be the last step in registering the PHY. Or your
>> PHY call backs can be called before you create the PHY. Btw in your case you
> 
> But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
> other did it same way. First phy_provider_register and then
> phy_create.

That's a bug which we figured out very late. Will get it fixed in this -rc cycle.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:23         ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:23 UTC (permalink / raw)
  To: Pratyush Anand
  Cc: arnd-r2nGTMty4D4, spear-devel,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

Hi,

On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> Hi Kishon,
> 
> On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
>>> skeleton support for the same.
>>>
>>> Currently phy ops are returning -EINVAL. They can be elaborated
>>> depending on the SOC being supported in future.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
>>> Tested-by: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
>>> Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
>>> Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
>>> Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
>>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>> ---
>>>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
>>>  drivers/phy/Kconfig                                |   6 +
>>>  drivers/phy/Makefile                               |   1 +
>>>  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
>>>  4 files changed, 193 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>>  create mode 100644 drivers/phy/phy-miphy40lp.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> new file mode 100644
>>> index 0000000..d0c7096
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> @@ -0,0 +1,12 @@
>>> +Required properties:
>>> +- compatible : should be "st,miphy40lp-phy"
>>> +	Other supported soc specific compatible:
>>> +		"st,spear1310-miphy"
>>> +		"st,spear1340-miphy"
>>> +- reg : offset and length of the PHY register set.
>>> +- misc: phandle for the syscon node to access misc registers
>>> +- phy-id: Instance id of the phy.
>>> +- #phy-cells : from the generic PHY bindings, must be 1.
>>> +	- 1st cell: phandle to the phy node.
>>> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
>>> +	  and 2 for Super Speed USB.
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index afa2354..2f58993 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>>>  	help
>>>  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
>>>  
>>> +config PHY_ST_MIPHY40LP
>>> +	tristate "ST MIPHY 40LP driver"
>>> +	help
>>> +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
>>> +	select GENERIC_PHY
>>> +
>>>  endmenu
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index b57c253..c061091 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>>>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>>>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>>>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
>>> +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> new file mode 100644
>>> index 0000000..d478c14
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -0,0 +1,174 @@
>>> +/*
>>> + * ST MiPHY-40LP PHY driver
>>> + *
>>> + * Copyright (C) 2014 ST Microelectronics
>>> + * Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include <linux/delay.h>
>>> +#include <linux/dma-mapping.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +enum phy_mode {
>>> +	SATA,
>>> +	PCIE,
>>> +	SS_USB,
>>> +};
>>> +
>>> +struct st_miphy40lp_priv {
>>> +	/* regmap for any soc specific misc registers */
>>> +	struct regmap		*misc;
>>> +	/* phy struct pointer */
>>> +	struct phy		*phy;
>>> +	/* device node pointer */
>>> +	struct device_node	*np;
>>> +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
>>> +	enum phy_mode		mode;
>>> +	/* instance id of this phy */
>>> +	u32			id;
>>> +};
>>> +
>>> +static int miphy40lp_init(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_exit(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_off(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_on(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static const struct of_device_id st_miphy40lp_of_match[] = {
>>> +	{ .compatible = "st,miphy40lp-phy" },
>>> +	{ },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
>>> +
>>> +static struct phy_ops st_miphy40lp_ops = {
>>> +	.init = miphy40lp_init,
>>> +	.exit = miphy40lp_exit,
>>> +	.power_off = miphy40lp_power_off,
>>> +	.power_on = miphy40lp_power_on,
>>> +	.owner		= THIS_MODULE,
>>
>> Would prefer to either align all the fields or align none. Here only owner is
>> aligned.
> 
> ok.
> 
>>> +};
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int miphy40lp_suspend(struct device *dev)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_resume(struct device *dev)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +#endif
>>> +
>>> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
>>> +		miphy40lp_resume);
>>> +
>>> +static struct phy *st_miphy40lp_xlate(struct device *dev,
>>> +					struct of_phandle_args *args)
>>> +{
>>> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
>>> +
>>> +	if (args->args_count < 1) {
>>> +		dev_err(dev, "DT did not pass correct no of args\n");
>>> +		return NULL;
>>> +	}
>>> +
>>> +	phypriv->mode = args->args[0];
>>> +
>>> +	return phypriv->phy;
>>> +}
>>> +
>>> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
>>> +{
>>> +	struct device *dev = &pdev->dev;
>>> +	struct st_miphy40lp_priv *phypriv;
>>> +	struct phy_provider *phy_provider;
>>> +
>>> +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
>>> +	if (!phypriv) {
>>> +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
>>> +		return -ENOMEM;
>>> +	}
>>> +
>>> +	phypriv->np = dev->of_node;
>>> +
>>> +	phypriv->misc =
>>> +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
>>> +	if (IS_ERR(phypriv->misc)) {
>>> +		dev_err(dev, "failed to find misc regmap\n");
>>> +		return PTR_ERR(phypriv->misc);
>>> +	}
>>> +
>>> +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
>>> +		dev_err(dev, "failed to find phy id\n");
>>> +		return -EINVAL;
>>> +	}
>> Do we really need this phy id? How is it being used?
> 
> Yes , it is being used by patch 6/8.

Alright.
> 
>>
>>> +
>>> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
>>> +	if (IS_ERR(phy_provider)) {
>>> +		dev_err(dev, "failed to register phy provider\n");
>>> +		return PTR_ERR(phy_provider);
>>> +	}
>>
>> phy_provider_register should be the last step in registering the PHY. Or your
>> PHY call backs can be called before you create the PHY. Btw in your case you
> 
> But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
> other did it same way. First phy_provider_register and then
> phy_create.

That's a bug which we figured out very late. Will get it fixed in this -rc cycle.

Thanks
Kishon
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^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:23         ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:23 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> Hi Kishon,
> 
> On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
>>> skeleton support for the same.
>>>
>>> Currently phy ops are returning -EINVAL. They can be elaborated
>>> depending on the SOC being supported in future.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel at list.st.com
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: devicetree at vger.kernel.org
>>> Cc: linux-kernel at vger.kernel.org
>>> ---
>>>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 ++
>>>  drivers/phy/Kconfig                                |   6 +
>>>  drivers/phy/Makefile                               |   1 +
>>>  drivers/phy/phy-miphy40lp.c                        | 174 +++++++++++++++++++++
>>>  4 files changed, 193 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>>  create mode 100644 drivers/phy/phy-miphy40lp.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> new file mode 100644
>>> index 0000000..d0c7096
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> @@ -0,0 +1,12 @@
>>> +Required properties:
>>> +- compatible : should be "st,miphy40lp-phy"
>>> +	Other supported soc specific compatible:
>>> +		"st,spear1310-miphy"
>>> +		"st,spear1340-miphy"
>>> +- reg : offset and length of the PHY register set.
>>> +- misc: phandle for the syscon node to access misc registers
>>> +- phy-id: Instance id of the phy.
>>> +- #phy-cells : from the generic PHY bindings, must be 1.
>>> +	- 1st cell: phandle to the phy node.
>>> +	- 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
>>> +	  and 2 for Super Speed USB.
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index afa2354..2f58993 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>>>  	help
>>>  	  Enable this to support the Broadcom Kona USB 2.0 PHY.
>>>  
>>> +config PHY_ST_MIPHY40LP
>>> +	tristate "ST MIPHY 40LP driver"
>>> +	help
>>> +	  Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
>>> +	select GENERIC_PHY
>>> +
>>>  endmenu
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index b57c253..c061091 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)	+= phy-exynos-mipi-video.o
>>>  obj-$(CONFIG_PHY_MVEBU_SATA)		+= phy-mvebu-sata.o
>>>  obj-$(CONFIG_OMAP_USB2)			+= phy-omap-usb2.o
>>>  obj-$(CONFIG_TWL4030_USB)		+= phy-twl4030-usb.o
>>> +obj-$(CONFIG_PHY_ST_MIPHY40LP)		+= phy-miphy40lp.o
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> new file mode 100644
>>> index 0000000..d478c14
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -0,0 +1,174 @@
>>> +/*
>>> + * ST MiPHY-40LP PHY driver
>>> + *
>>> + * Copyright (C) 2014 ST Microelectronics
>>> + * Pratyush Anand <pratyush.anand@st.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include <linux/delay.h>
>>> +#include <linux/dma-mapping.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +enum phy_mode {
>>> +	SATA,
>>> +	PCIE,
>>> +	SS_USB,
>>> +};
>>> +
>>> +struct st_miphy40lp_priv {
>>> +	/* regmap for any soc specific misc registers */
>>> +	struct regmap		*misc;
>>> +	/* phy struct pointer */
>>> +	struct phy		*phy;
>>> +	/* device node pointer */
>>> +	struct device_node	*np;
>>> +	/* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
>>> +	enum phy_mode		mode;
>>> +	/* instance id of this phy */
>>> +	u32			id;
>>> +};
>>> +
>>> +static int miphy40lp_init(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_exit(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_off(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_on(struct phy *phy)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static const struct of_device_id st_miphy40lp_of_match[] = {
>>> +	{ .compatible = "st,miphy40lp-phy" },
>>> +	{ },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
>>> +
>>> +static struct phy_ops st_miphy40lp_ops = {
>>> +	.init = miphy40lp_init,
>>> +	.exit = miphy40lp_exit,
>>> +	.power_off = miphy40lp_power_off,
>>> +	.power_on = miphy40lp_power_on,
>>> +	.owner		= THIS_MODULE,
>>
>> Would prefer to either align all the fields or align none. Here only owner is
>> aligned.
> 
> ok.
> 
>>> +};
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int miphy40lp_suspend(struct device *dev)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_resume(struct device *dev)
>>> +{
>>> +	return -EINVAL;
>>> +}
>>> +#endif
>>> +
>>> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
>>> +		miphy40lp_resume);
>>> +
>>> +static struct phy *st_miphy40lp_xlate(struct device *dev,
>>> +					struct of_phandle_args *args)
>>> +{
>>> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
>>> +
>>> +	if (args->args_count < 1) {
>>> +		dev_err(dev, "DT did not pass correct no of args\n");
>>> +		return NULL;
>>> +	}
>>> +
>>> +	phypriv->mode = args->args[0];
>>> +
>>> +	return phypriv->phy;
>>> +}
>>> +
>>> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
>>> +{
>>> +	struct device *dev = &pdev->dev;
>>> +	struct st_miphy40lp_priv *phypriv;
>>> +	struct phy_provider *phy_provider;
>>> +
>>> +	phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
>>> +	if (!phypriv) {
>>> +		dev_err(dev, "can't alloc miphy40lp private date memory\n");
>>> +		return -ENOMEM;
>>> +	}
>>> +
>>> +	phypriv->np = dev->of_node;
>>> +
>>> +	phypriv->misc =
>>> +		syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
>>> +	if (IS_ERR(phypriv->misc)) {
>>> +		dev_err(dev, "failed to find misc regmap\n");
>>> +		return PTR_ERR(phypriv->misc);
>>> +	}
>>> +
>>> +	if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
>>> +		dev_err(dev, "failed to find phy id\n");
>>> +		return -EINVAL;
>>> +	}
>> Do we really need this phy id? How is it being used?
> 
> Yes , it is being used by patch 6/8.

Alright.
> 
>>
>>> +
>>> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
>>> +	if (IS_ERR(phy_provider)) {
>>> +		dev_err(dev, "failed to register phy provider\n");
>>> +		return PTR_ERR(phy_provider);
>>> +	}
>>
>> phy_provider_register should be the last step in registering the PHY. Or your
>> PHY call backs can be called before you create the PHY. Btw in your case you
> 
> But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
> other did it same way. First phy_provider_register and then
> phy_create.

That's a bug which we figured out very late. Will get it fixed in this -rc cycle.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:25           ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  6:25 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd, spear-devel, linux-arm-kernel, devicetree, linux-kernel

On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> > 
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds

[...]

> >>> +
> >>> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> >>> +	if (IS_ERR(phy_provider)) {
> >>> +		dev_err(dev, "failed to register phy provider\n");
> >>> +		return PTR_ERR(phy_provider);
> >>> +	}
> >>
> >> phy_provider_register should be the last step in registering the PHY. Or your
> >> PHY call backs can be called before you create the PHY. Btw in your case you
> > 
> > But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
> > other did it same way. First phy_provider_register and then
> > phy_create.
> 
> That's a bug which we figured out very late. Will get it fixed in this -rc cycle.

Ok..I ll correct in mine too. :)

Rgds
Pratyush
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:25           ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  6:25 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd-r2nGTMty4D4, spear-devel,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> > 
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds

[...]

> >>> +
> >>> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> >>> +	if (IS_ERR(phy_provider)) {
> >>> +		dev_err(dev, "failed to register phy provider\n");
> >>> +		return PTR_ERR(phy_provider);
> >>> +	}
> >>
> >> phy_provider_register should be the last step in registering the PHY. Or your
> >> PHY call backs can be called before you create the PHY. Btw in your case you
> > 
> > But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
> > other did it same way. First phy_provider_register and then
> > phy_create.
> 
> That's a bug which we figured out very late. Will get it fixed in this -rc cycle.

Ok..I ll correct in mine too. :)

Rgds
Pratyush
> 
> Thanks
> Kishon
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^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver
@ 2014-02-06  6:25           ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  6:25 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> > 
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds

[...]

> >>> +
> >>> +	phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> >>> +	if (IS_ERR(phy_provider)) {
> >>> +		dev_err(dev, "failed to register phy provider\n");
> >>> +		return PTR_ERR(phy_provider);
> >>> +	}
> >>
> >> phy_provider_register should be the last step in registering the PHY. Or your
> >> PHY call backs can be called before you create the PHY. Btw in your case you
> > 
> > But every one else like  phy-exynos-mipi-video or phy-omap-usb2 or any
> > other did it same way. First phy_provider_register and then
> > phy_create.
> 
> That's a bug which we figured out very late. Will get it fixed in this -rc cycle.

Ok..I ll correct in mine too. :)

Rgds
Pratyush
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  2014-02-06  4:44   ` Pratyush Anand
  (?)
@ 2014-02-06  6:32     ` Kishon Vijay Abraham I
  -1 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:32 UTC (permalink / raw)
  To: Pratyush Anand, arnd
  Cc: Viresh Kumar, Tejun Heo, spear-devel, linux-arm-kernel,
	devicetree, linux-ide, linux-kernel

Hi,

On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
> 
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
> 
> So move all these SATA platform code to phy-miphy40lp driver.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel@list.st.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ide@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
>  arch/arm/mach-spear/Kconfig                        |   2 +
>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-

It would be better if you can split this patch. Keep arch/ in separate patch
and drivers/ in separate patch.
>  9 files changed, 266 insertions(+), 136 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> 
.
.
<snip>
.
.
>  static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index d478c14..cc7f45d 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,6 +8,7 @@
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
>   *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>   */
>  
>  #include <linux/delay.h>
> @@ -19,6 +20,60 @@
>  #include <linux/phy/phy.h>
>  #include <linux/regmap.h>
>  
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG			0x100
> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> +#define SPEAR1340_PCM_WKUP_CFG			0x104
> +#define SPEAR1340_SWITCH_CTR			0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST			0x318
> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> +#define SPEAR1340_PERIP2_SW_RST			0x31C
> +#define SPEAR1340_PERIP3_SW_RST			0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG			0x424
> +	/* PCIE CFG MASks */
> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)

use BIT() wherever possible.
> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
>  enum phy_mode {
>  	SATA,
>  	PCIE,
> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>  	u32			id;
>  };
>  
> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)

The function name format here differs from what you have already added. It will
be good to have consistent name in the file.
> +{
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
> +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> +	/* Switch on sata power domain */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
> +	msleep(20);
> +	/* Disable PCIE SATA Controller reset */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
> +	msleep(20);
> +
> +	return 0;
> +}
> +
> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> +	/* Enable PCIE SATA Controller reset */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> +			SPEAR1340_PERIP1_SW_RST_SATA,
> +			SPEAR1340_PERIP1_SW_RST_SATA);
> +	msleep(20);
> +	/* Switch off sata power domain */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> +	msleep(20);
> +
> +	return 0;
> +}
> +
> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))

This compatible value is a bit confusing since it doesn't have 'sata' in it.
spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> +		return spear1340_sata_miphy_init(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_exit(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return 0;
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return 0;
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_exit(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_init(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
>  static int miphy40lp_init(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_init(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_exit(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_exit(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_power_off(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_power_off(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_power_on(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_power_on(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static const struct of_device_id st_miphy40lp_of_match[] = {
>  	{ .compatible = "st,miphy40lp-phy" },
> +	{ .compatible = "st,spear1340-miphy" },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
>  #ifdef CONFIG_PM_SLEEP
>  static int miphy40lp_suspend(struct device *dev)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (dev->power.power_state.event == PM_EVENT_FREEZE)
> +		return 0;

I'm not sure if you should be accessing it from the drivers. Will be good to
check with PM guys.
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_suspend(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_resume(struct device *dev)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (dev->power.power_state.event == PM_EVENT_THAW)
> +		return 0;

Same here.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  6:32     ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:32 UTC (permalink / raw)
  To: Pratyush Anand, arnd
  Cc: Viresh Kumar, Tejun Heo, spear-devel, linux-arm-kernel,
	devicetree, linux-ide, linux-kernel

Hi,

On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
> 
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
> 
> So move all these SATA platform code to phy-miphy40lp driver.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel@list.st.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ide@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
>  arch/arm/mach-spear/Kconfig                        |   2 +
>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-

It would be better if you can split this patch. Keep arch/ in separate patch
and drivers/ in separate patch.
>  9 files changed, 266 insertions(+), 136 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> 
.
.
<snip>
.
.
>  static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index d478c14..cc7f45d 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,6 +8,7 @@
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
>   *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>   */
>  
>  #include <linux/delay.h>
> @@ -19,6 +20,60 @@
>  #include <linux/phy/phy.h>
>  #include <linux/regmap.h>
>  
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG			0x100
> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> +#define SPEAR1340_PCM_WKUP_CFG			0x104
> +#define SPEAR1340_SWITCH_CTR			0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST			0x318
> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> +#define SPEAR1340_PERIP2_SW_RST			0x31C
> +#define SPEAR1340_PERIP3_SW_RST			0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG			0x424
> +	/* PCIE CFG MASks */
> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)

use BIT() wherever possible.
> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
>  enum phy_mode {
>  	SATA,
>  	PCIE,
> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>  	u32			id;
>  };
>  
> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)

The function name format here differs from what you have already added. It will
be good to have consistent name in the file.
> +{
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
> +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> +	/* Switch on sata power domain */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
> +	msleep(20);
> +	/* Disable PCIE SATA Controller reset */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
> +	msleep(20);
> +
> +	return 0;
> +}
> +
> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> +	/* Enable PCIE SATA Controller reset */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> +			SPEAR1340_PERIP1_SW_RST_SATA,
> +			SPEAR1340_PERIP1_SW_RST_SATA);
> +	msleep(20);
> +	/* Switch off sata power domain */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> +	msleep(20);
> +
> +	return 0;
> +}
> +
> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))

This compatible value is a bit confusing since it doesn't have 'sata' in it.
spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> +		return spear1340_sata_miphy_init(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_exit(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return 0;
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return 0;
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_exit(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_init(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
>  static int miphy40lp_init(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_init(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_exit(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_exit(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_power_off(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_power_off(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_power_on(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_power_on(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static const struct of_device_id st_miphy40lp_of_match[] = {
>  	{ .compatible = "st,miphy40lp-phy" },
> +	{ .compatible = "st,spear1340-miphy" },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
>  #ifdef CONFIG_PM_SLEEP
>  static int miphy40lp_suspend(struct device *dev)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (dev->power.power_state.event == PM_EVENT_FREEZE)
> +		return 0;

I'm not sure if you should be accessing it from the drivers. Will be good to
check with PM guys.
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_suspend(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_resume(struct device *dev)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (dev->power.power_state.event == PM_EVENT_THAW)
> +		return 0;

Same here.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  6:32     ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  6:32 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
> 
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
> 
> So move all these SATA platform code to phy-miphy40lp driver.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Cc: Viresh Kumar <viresh.linux@gmail.com>
> Cc: Tejun Heo <tj@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-ide at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> ---
>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
>  arch/arm/mach-spear/Kconfig                        |   2 +
>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-

It would be better if you can split this patch. Keep arch/ in separate patch
and drivers/ in separate patch.
>  9 files changed, 266 insertions(+), 136 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> 
.
.
<snip>
.
.
>  static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index d478c14..cc7f45d 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,6 +8,7 @@
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
>   *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>   */
>  
>  #include <linux/delay.h>
> @@ -19,6 +20,60 @@
>  #include <linux/phy/phy.h>
>  #include <linux/regmap.h>
>  
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG			0x100
> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> +#define SPEAR1340_PCM_WKUP_CFG			0x104
> +#define SPEAR1340_SWITCH_CTR			0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST			0x318
> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> +#define SPEAR1340_PERIP2_SW_RST			0x31C
> +#define SPEAR1340_PERIP3_SW_RST			0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG			0x424
> +	/* PCIE CFG MASks */
> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)

use BIT() wherever possible.
> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
>  enum phy_mode {
>  	SATA,
>  	PCIE,
> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>  	u32			id;
>  };
>  
> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)

The function name format here differs from what you have already added. It will
be good to have consistent name in the file.
> +{
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
> +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> +	/* Switch on sata power domain */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
> +	msleep(20);
> +	/* Disable PCIE SATA Controller reset */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
> +	msleep(20);
> +
> +	return 0;
> +}
> +
> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> +	/* Enable PCIE SATA Controller reset */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> +			SPEAR1340_PERIP1_SW_RST_SATA,
> +			SPEAR1340_PERIP1_SW_RST_SATA);
> +	msleep(20);
> +	/* Switch off sata power domain */
> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> +	msleep(20);
> +
> +	return 0;
> +}
> +
> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))

This compatible value is a bit confusing since it doesn't have 'sata' in it.
spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> +		return spear1340_sata_miphy_init(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_exit(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return 0;
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return 0;
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_exit(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
> +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> +{
> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +		return spear1340_sata_miphy_init(phypriv);
> +	else
> +		return -EINVAL;
> +}
> +
>  static int miphy40lp_init(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_init(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_exit(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_exit(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_power_off(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_power_off(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_power_on(struct phy *phy)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_power_on(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static const struct of_device_id st_miphy40lp_of_match[] = {
>  	{ .compatible = "st,miphy40lp-phy" },
> +	{ .compatible = "st,spear1340-miphy" },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
>  #ifdef CONFIG_PM_SLEEP
>  static int miphy40lp_suspend(struct device *dev)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (dev->power.power_state.event == PM_EVENT_FREEZE)
> +		return 0;

I'm not sure if you should be accessing it from the drivers. Will be good to
check with PM guys.
> +
> +	switch (phypriv->mode) {
> +	case SATA:
> +		return sata_miphy_suspend(phypriv);
> +	default:
> +		return -EINVAL;
> +	}
>  }
>  
>  static int miphy40lp_resume(struct device *dev)
>  {
> -	return -EINVAL;
> +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> +	if (dev->power.power_state.event == PM_EVENT_THAW)
> +		return 0;

Same here.

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  2014-02-06  6:32     ` Kishon Vijay Abraham I
  (?)
@ 2014-02-06  7:00       ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  7:00 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd, Viresh Kumar, Tejun Heo, spear-devel, linux-arm-kernel,
	devicetree, linux-ide, linux-kernel

On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now these functions were
> > present in a platform driver with a fixme notes.
> > 
> > Similar functions modifying same set of registers will also be needed in
> > case of PCIe phy init/exit.
> > 
> > So move all these SATA platform code to phy-miphy40lp driver.
> > 
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Tejun Heo <tj@kernel.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-ide@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> >  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
> >  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
> >  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
> >  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
> >  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
> >  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
> >  arch/arm/mach-spear/Kconfig                        |   2 +
> >  arch/arm/mach-spear/spear1340.c                    | 127 +------------
> >  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
> 
> It would be better if you can split this patch. Keep arch/ in separate patch
> and drivers/ in separate patch.

Code is actually moving from arch to driver. Therefore I kept it in
same patch.

> >  9 files changed, 266 insertions(+), 136 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> > 
> .
> .
> <snip>
> .
> .
> >  static const char * const spear1340_dt_board_compat[] = {
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > index d478c14..cc7f45d 100644
> > --- a/drivers/phy/phy-miphy40lp.c
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -8,6 +8,7 @@
> >   * it under the terms of the GNU General Public License version 2 as
> >   * published by the Free Software Foundation.
> >   *
> > + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >   */
> >  
> >  #include <linux/delay.h>
> > @@ -19,6 +20,60 @@
> >  #include <linux/phy/phy.h>
> >  #include <linux/regmap.h>
> >  
> > +/* SPEAr1340 Registers */
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG			0x100
> > +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> > +#define SPEAR1340_PCM_WKUP_CFG			0x104
> > +#define SPEAR1340_SWITCH_CTR			0x108
> > +
> > +#define SPEAR1340_PERIP1_SW_RST			0x318
> > +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> > +#define SPEAR1340_PERIP2_SW_RST			0x31C
> > +#define SPEAR1340_PERIP3_SW_RST			0x320
> > +
> > +/* PCIE - SATA configuration registers */
> > +#define SPEAR1340_PCIE_SATA_CFG			0x424
> > +	/* PCIE CFG MASks */
> > +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> 
> use BIT() wherever possible.

OK.

> > +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> > +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> > +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> > +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> > +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> > +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> > +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> > +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> > +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> > +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> > +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> > +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> > +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> > +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> > +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> > +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> > +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> > +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> > +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> > +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> > +
> > +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> > +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> > +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> > +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> > +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> > +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> > +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> > +
> >  enum phy_mode {
> >  	SATA,
> >  	PCIE,
> > @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >  	u32			id;
> >  };
> >  
> > +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> 
> The function name format here differs from what you have already added. It will
> be good to have consistent name in the file.

You mean to pass "struct phy *phy" in all the internal functions too?

> > +{
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > +	/* Switch on sata power domain */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > +	msleep(20);
> > +	/* Disable PCIE SATA Controller reset */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > +	msleep(20);
> > +
> > +	return 0;
> > +}
> > +
> > +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> > +
> > +	/* Enable PCIE SATA Controller reset */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > +			SPEAR1340_PERIP1_SW_RST_SATA,
> > +			SPEAR1340_PERIP1_SW_RST_SATA);
> > +	msleep(20);
> > +	/* Switch off sata power domain */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> > +	msleep(20);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> 
> This compatible value is a bit confusing since it doesn't have 'sata' in it.
> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?

same spear1340 miphy is used for sata as well as for pcie. sata or
pcie mode is selected using mode args passed in phys.


> > +		return spear1340_sata_miphy_init(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_exit(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return 0;
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return 0;
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_exit(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_init(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> >  static int miphy40lp_init(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_init(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_exit(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_exit(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_power_off(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_power_off(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_power_on(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_power_on(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static const struct of_device_id st_miphy40lp_of_match[] = {
> >  	{ .compatible = "st,miphy40lp-phy" },
> > +	{ .compatible = "st,spear1340-miphy" },
> >  	{ },
> >  };
> >  MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> >  #ifdef CONFIG_PM_SLEEP
> >  static int miphy40lp_suspend(struct device *dev)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (dev->power.power_state.event == PM_EVENT_FREEZE)
> > +		return 0;
> 
> I'm not sure if you should be accessing it from the drivers. Will be good to
> check with PM guys.

+ linux-pm mailing list.

Rgds
Pratyush

> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_suspend(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_resume(struct device *dev)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (dev->power.power_state.event == PM_EVENT_THAW)
> > +		return 0;
> 
> Same here.
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  7:00       ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  7:00 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd, Viresh Kumar, Tejun Heo, spear-devel, linux-arm-kernel,
	devicetree, linux-ide, linux-kernel

On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now these functions were
> > present in a platform driver with a fixme notes.
> > 
> > Similar functions modifying same set of registers will also be needed in
> > case of PCIe phy init/exit.
> > 
> > So move all these SATA platform code to phy-miphy40lp driver.
> > 
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Tejun Heo <tj@kernel.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: devicetree@vger.kernel.org
> > Cc: linux-ide@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> >  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
> >  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
> >  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
> >  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
> >  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
> >  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
> >  arch/arm/mach-spear/Kconfig                        |   2 +
> >  arch/arm/mach-spear/spear1340.c                    | 127 +------------
> >  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
> 
> It would be better if you can split this patch. Keep arch/ in separate patch
> and drivers/ in separate patch.

Code is actually moving from arch to driver. Therefore I kept it in
same patch.

> >  9 files changed, 266 insertions(+), 136 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> > 
> .
> .
> <snip>
> .
> .
> >  static const char * const spear1340_dt_board_compat[] = {
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > index d478c14..cc7f45d 100644
> > --- a/drivers/phy/phy-miphy40lp.c
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -8,6 +8,7 @@
> >   * it under the terms of the GNU General Public License version 2 as
> >   * published by the Free Software Foundation.
> >   *
> > + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >   */
> >  
> >  #include <linux/delay.h>
> > @@ -19,6 +20,60 @@
> >  #include <linux/phy/phy.h>
> >  #include <linux/regmap.h>
> >  
> > +/* SPEAr1340 Registers */
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG			0x100
> > +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> > +#define SPEAR1340_PCM_WKUP_CFG			0x104
> > +#define SPEAR1340_SWITCH_CTR			0x108
> > +
> > +#define SPEAR1340_PERIP1_SW_RST			0x318
> > +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> > +#define SPEAR1340_PERIP2_SW_RST			0x31C
> > +#define SPEAR1340_PERIP3_SW_RST			0x320
> > +
> > +/* PCIE - SATA configuration registers */
> > +#define SPEAR1340_PCIE_SATA_CFG			0x424
> > +	/* PCIE CFG MASks */
> > +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> 
> use BIT() wherever possible.

OK.

> > +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> > +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> > +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> > +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> > +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> > +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> > +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> > +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> > +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> > +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> > +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> > +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> > +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> > +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> > +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> > +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> > +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> > +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> > +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> > +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> > +
> > +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> > +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> > +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> > +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> > +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> > +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> > +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> > +
> >  enum phy_mode {
> >  	SATA,
> >  	PCIE,
> > @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >  	u32			id;
> >  };
> >  
> > +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> 
> The function name format here differs from what you have already added. It will
> be good to have consistent name in the file.

You mean to pass "struct phy *phy" in all the internal functions too?

> > +{
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > +	/* Switch on sata power domain */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > +	msleep(20);
> > +	/* Disable PCIE SATA Controller reset */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > +	msleep(20);
> > +
> > +	return 0;
> > +}
> > +
> > +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> > +
> > +	/* Enable PCIE SATA Controller reset */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > +			SPEAR1340_PERIP1_SW_RST_SATA,
> > +			SPEAR1340_PERIP1_SW_RST_SATA);
> > +	msleep(20);
> > +	/* Switch off sata power domain */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> > +	msleep(20);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> 
> This compatible value is a bit confusing since it doesn't have 'sata' in it.
> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?

same spear1340 miphy is used for sata as well as for pcie. sata or
pcie mode is selected using mode args passed in phys.


> > +		return spear1340_sata_miphy_init(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_exit(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return 0;
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return 0;
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_exit(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_init(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> >  static int miphy40lp_init(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_init(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_exit(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_exit(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_power_off(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_power_off(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_power_on(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_power_on(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static const struct of_device_id st_miphy40lp_of_match[] = {
> >  	{ .compatible = "st,miphy40lp-phy" },
> > +	{ .compatible = "st,spear1340-miphy" },
> >  	{ },
> >  };
> >  MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> >  #ifdef CONFIG_PM_SLEEP
> >  static int miphy40lp_suspend(struct device *dev)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (dev->power.power_state.event == PM_EVENT_FREEZE)
> > +		return 0;
> 
> I'm not sure if you should be accessing it from the drivers. Will be good to
> check with PM guys.

+ linux-pm mailing list.

Rgds
Pratyush

> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_suspend(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_resume(struct device *dev)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (dev->power.power_state.event == PM_EVENT_THAW)
> > +		return 0;
> 
> Same here.
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  7:00       ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  7:00 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now these functions were
> > present in a platform driver with a fixme notes.
> > 
> > Similar functions modifying same set of registers will also be needed in
> > case of PCIe phy init/exit.
> > 
> > So move all these SATA platform code to phy-miphy40lp driver.
> > 
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Tested-by: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Viresh Kumar <viresh.linux@gmail.com>
> > Cc: Tejun Heo <tj@kernel.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > Cc: linux-ide at vger.kernel.org
> > Cc: linux-kernel at vger.kernel.org
> > ---
> >  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
> >  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
> >  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
> >  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
> >  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
> >  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
> >  arch/arm/mach-spear/Kconfig                        |   2 +
> >  arch/arm/mach-spear/spear1340.c                    | 127 +------------
> >  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
> 
> It would be better if you can split this patch. Keep arch/ in separate patch
> and drivers/ in separate patch.

Code is actually moving from arch to driver. Therefore I kept it in
same patch.

> >  9 files changed, 266 insertions(+), 136 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> > 
> .
> .
> <snip>
> .
> .
> >  static const char * const spear1340_dt_board_compat[] = {
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > index d478c14..cc7f45d 100644
> > --- a/drivers/phy/phy-miphy40lp.c
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -8,6 +8,7 @@
> >   * it under the terms of the GNU General Public License version 2 as
> >   * published by the Free Software Foundation.
> >   *
> > + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >   */
> >  
> >  #include <linux/delay.h>
> > @@ -19,6 +20,60 @@
> >  #include <linux/phy/phy.h>
> >  #include <linux/regmap.h>
> >  
> > +/* SPEAr1340 Registers */
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG			0x100
> > +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> > +#define SPEAR1340_PCM_WKUP_CFG			0x104
> > +#define SPEAR1340_SWITCH_CTR			0x108
> > +
> > +#define SPEAR1340_PERIP1_SW_RST			0x318
> > +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> > +#define SPEAR1340_PERIP2_SW_RST			0x31C
> > +#define SPEAR1340_PERIP3_SW_RST			0x320
> > +
> > +/* PCIE - SATA configuration registers */
> > +#define SPEAR1340_PCIE_SATA_CFG			0x424
> > +	/* PCIE CFG MASks */
> > +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> 
> use BIT() wherever possible.

OK.

> > +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> > +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> > +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> > +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> > +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> > +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> > +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> > +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> > +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> > +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> > +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> > +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> > +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> > +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> > +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> > +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> > +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> > +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> > +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> > +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> > +
> > +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> > +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> > +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> > +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> > +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> > +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> > +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> > +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> > +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> > +
> >  enum phy_mode {
> >  	SATA,
> >  	PCIE,
> > @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >  	u32			id;
> >  };
> >  
> > +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> 
> The function name format here differs from what you have already added. It will
> be good to have consistent name in the file.

You mean to pass "struct phy *phy" in all the internal functions too?

> > +{
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > +	/* Switch on sata power domain */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > +	msleep(20);
> > +	/* Disable PCIE SATA Controller reset */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > +	msleep(20);
> > +
> > +	return 0;
> > +}
> > +
> > +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> > +
> > +	/* Enable PCIE SATA Controller reset */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > +			SPEAR1340_PERIP1_SW_RST_SATA,
> > +			SPEAR1340_PERIP1_SW_RST_SATA);
> > +	msleep(20);
> > +	/* Switch off sata power domain */
> > +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> > +	msleep(20);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> 
> This compatible value is a bit confusing since it doesn't have 'sata' in it.
> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?

same spear1340 miphy is used for sata as well as for pcie. sata or
pcie mode is selected using mode args passed in phys.


> > +		return spear1340_sata_miphy_init(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_exit(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return 0;
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return 0;
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_exit(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> > +{
> > +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +		return spear1340_sata_miphy_init(phypriv);
> > +	else
> > +		return -EINVAL;
> > +}
> > +
> >  static int miphy40lp_init(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_init(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_exit(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_exit(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_power_off(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_power_off(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_power_on(struct phy *phy)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_power_on(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static const struct of_device_id st_miphy40lp_of_match[] = {
> >  	{ .compatible = "st,miphy40lp-phy" },
> > +	{ .compatible = "st,spear1340-miphy" },
> >  	{ },
> >  };
> >  MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> >  #ifdef CONFIG_PM_SLEEP
> >  static int miphy40lp_suspend(struct device *dev)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (dev->power.power_state.event == PM_EVENT_FREEZE)
> > +		return 0;
> 
> I'm not sure if you should be accessing it from the drivers. Will be good to
> check with PM guys.

+ linux-pm mailing list.

Rgds
Pratyush

> > +
> > +	switch (phypriv->mode) {
> > +	case SATA:
> > +		return sata_miphy_suspend(phypriv);
> > +	default:
> > +		return -EINVAL;
> > +	}
> >  }
> >  
> >  static int miphy40lp_resume(struct device *dev)
> >  {
> > -	return -EINVAL;
> > +	struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > +	if (dev->power.power_state.event == PM_EVENT_THAW)
> > +		return 0;
> 
> Same here.
> 
> Thanks
> Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  2014-02-06  7:00       ` Pratyush Anand
  (?)
@ 2014-02-06  8:01         ` Kishon Vijay Abraham I
  -1 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  8:01 UTC (permalink / raw)
  To: Pratyush Anand
  Cc: devicetree, arnd, spear-devel, linux-kernel, linux-ide,
	Viresh Kumar, Tejun Heo, linux-arm-kernel

Hi,

On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ahci driver needs some platform specific functions which are called at
>>> init, exit, suspend and resume conditions. Till now these functions were
>>> present in a platform driver with a fixme notes.
>>>
>>> Similar functions modifying same set of registers will also be needed in
>>> case of PCIe phy init/exit.
>>>
>>> So move all these SATA platform code to phy-miphy40lp driver.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Viresh Kumar <viresh.linux@gmail.com>
>>> Cc: Tejun Heo <tj@kernel.org>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel@list.st.com
>>> Cc: linux-arm-kernel@lists.infradead.org
>>> Cc: devicetree@vger.kernel.org
>>> Cc: linux-ide@vger.kernel.org
>>> Cc: linux-kernel@vger.kernel.org
>>> ---
>>>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>>>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>>>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
>>>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>>>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
>>>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
>>>  arch/arm/mach-spear/Kconfig                        |   2 +
>>>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
>>>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
>>
>> It would be better if you can split this patch. Keep arch/ in separate patch
>> and drivers/ in separate patch.
> 
> Code is actually moving from arch to driver. Therefore I kept it in
> same patch.
> 
>>>  9 files changed, 266 insertions(+), 136 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>>  static const char * const spear1340_dt_board_compat[] = {
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> index d478c14..cc7f45d 100644
>>> --- a/drivers/phy/phy-miphy40lp.c
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -8,6 +8,7 @@
>>>   * it under the terms of the GNU General Public License version 2 as
>>>   * published by the Free Software Foundation.
>>>   *
>>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>>>   */
>>>  
>>>  #include <linux/delay.h>
>>> @@ -19,6 +20,60 @@
>>>  #include <linux/phy/phy.h>
>>>  #include <linux/regmap.h>
>>>  
>>> +/* SPEAr1340 Registers */
>>> +/* Power Management Registers */
>>> +#define SPEAR1340_PCM_CFG			0x100
>>> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
>>> +#define SPEAR1340_PCM_WKUP_CFG			0x104
>>> +#define SPEAR1340_SWITCH_CTR			0x108
>>> +
>>> +#define SPEAR1340_PERIP1_SW_RST			0x318
>>> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
>>> +#define SPEAR1340_PERIP2_SW_RST			0x31C
>>> +#define SPEAR1340_PERIP3_SW_RST			0x320
>>> +
>>> +/* PCIE - SATA configuration registers */
>>> +#define SPEAR1340_PCIE_SATA_CFG			0x424
>>> +	/* PCIE CFG MASks */
>>> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
>>
>> use BIT() wherever possible.
> 
> OK.
> 
>>> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
>>> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
>>> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
>>> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
>>> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
>>> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
>>> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
>>> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
>>> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
>>> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
>>> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
>>> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
>>> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
>>> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
>>> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
>>> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
>>> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
>>> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
>>> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
>>> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
>>> +
>>> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
>>> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
>>> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
>>> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
>>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
>>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
>>> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
>>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>>> +
>>>  enum phy_mode {
>>>  	SATA,
>>>  	PCIE,
>>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>>>  	u32			id;
>>>  };
>>>  
>>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>
>> The function name format here differs from what you have already added. It will
>> be good to have consistent name in the file.
> 
> You mean to pass "struct phy *phy" in all the internal functions too?

No. I meant let all the function names begin with miphy40lp_.
> 
>>> +{
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> +	/* Switch on sata power domain */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> +	msleep(20);
>>> +	/* Disable PCIE SATA Controller reset */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
>>> +	msleep(20);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
>>> +
>>> +	/* Enable PCIE SATA Controller reset */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA);
>>> +	msleep(20);
>>> +	/* Switch off sata power domain */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
>>> +	msleep(20);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>>
>> This compatible value is a bit confusing since it doesn't have 'sata' in it.
>> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> 
> same spear1340 miphy is used for sata as well as for pcie. sata or
> pcie mode is selected using mode args passed in phys.

Alright. Got it while reading the next patch ;-)

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  8:01         ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  8:01 UTC (permalink / raw)
  To: Pratyush Anand
  Cc: arnd, Viresh Kumar, Tejun Heo, spear-devel, linux-arm-kernel,
	devicetree, linux-ide, linux-kernel

Hi,

On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ahci driver needs some platform specific functions which are called at
>>> init, exit, suspend and resume conditions. Till now these functions were
>>> present in a platform driver with a fixme notes.
>>>
>>> Similar functions modifying same set of registers will also be needed in
>>> case of PCIe phy init/exit.
>>>
>>> So move all these SATA platform code to phy-miphy40lp driver.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Viresh Kumar <viresh.linux@gmail.com>
>>> Cc: Tejun Heo <tj@kernel.org>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel@list.st.com
>>> Cc: linux-arm-kernel@lists.infradead.org
>>> Cc: devicetree@vger.kernel.org
>>> Cc: linux-ide@vger.kernel.org
>>> Cc: linux-kernel@vger.kernel.org
>>> ---
>>>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>>>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>>>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
>>>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>>>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
>>>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
>>>  arch/arm/mach-spear/Kconfig                        |   2 +
>>>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
>>>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
>>
>> It would be better if you can split this patch. Keep arch/ in separate patch
>> and drivers/ in separate patch.
> 
> Code is actually moving from arch to driver. Therefore I kept it in
> same patch.
> 
>>>  9 files changed, 266 insertions(+), 136 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>>  static const char * const spear1340_dt_board_compat[] = {
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> index d478c14..cc7f45d 100644
>>> --- a/drivers/phy/phy-miphy40lp.c
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -8,6 +8,7 @@
>>>   * it under the terms of the GNU General Public License version 2 as
>>>   * published by the Free Software Foundation.
>>>   *
>>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>>>   */
>>>  
>>>  #include <linux/delay.h>
>>> @@ -19,6 +20,60 @@
>>>  #include <linux/phy/phy.h>
>>>  #include <linux/regmap.h>
>>>  
>>> +/* SPEAr1340 Registers */
>>> +/* Power Management Registers */
>>> +#define SPEAR1340_PCM_CFG			0x100
>>> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
>>> +#define SPEAR1340_PCM_WKUP_CFG			0x104
>>> +#define SPEAR1340_SWITCH_CTR			0x108
>>> +
>>> +#define SPEAR1340_PERIP1_SW_RST			0x318
>>> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
>>> +#define SPEAR1340_PERIP2_SW_RST			0x31C
>>> +#define SPEAR1340_PERIP3_SW_RST			0x320
>>> +
>>> +/* PCIE - SATA configuration registers */
>>> +#define SPEAR1340_PCIE_SATA_CFG			0x424
>>> +	/* PCIE CFG MASks */
>>> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
>>
>> use BIT() wherever possible.
> 
> OK.
> 
>>> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
>>> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
>>> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
>>> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
>>> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
>>> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
>>> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
>>> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
>>> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
>>> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
>>> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
>>> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
>>> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
>>> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
>>> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
>>> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
>>> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
>>> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
>>> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
>>> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
>>> +
>>> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
>>> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
>>> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
>>> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
>>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
>>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
>>> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
>>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>>> +
>>>  enum phy_mode {
>>>  	SATA,
>>>  	PCIE,
>>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>>>  	u32			id;
>>>  };
>>>  
>>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>
>> The function name format here differs from what you have already added. It will
>> be good to have consistent name in the file.
> 
> You mean to pass "struct phy *phy" in all the internal functions too?

No. I meant let all the function names begin with miphy40lp_.
> 
>>> +{
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> +	/* Switch on sata power domain */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> +	msleep(20);
>>> +	/* Disable PCIE SATA Controller reset */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
>>> +	msleep(20);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
>>> +
>>> +	/* Enable PCIE SATA Controller reset */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA);
>>> +	msleep(20);
>>> +	/* Switch off sata power domain */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
>>> +	msleep(20);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>>
>> This compatible value is a bit confusing since it doesn't have 'sata' in it.
>> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> 
> same spear1340 miphy is used for sata as well as for pcie. sata or
> pcie mode is selected using mode args passed in phys.

Alright. Got it while reading the next patch ;-)

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  8:01         ` Kishon Vijay Abraham I
  0 siblings, 0 replies; 49+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-06  8:01 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ahci driver needs some platform specific functions which are called at
>>> init, exit, suspend and resume conditions. Till now these functions were
>>> present in a platform driver with a fixme notes.
>>>
>>> Similar functions modifying same set of registers will also be needed in
>>> case of PCIe phy init/exit.
>>>
>>> So move all these SATA platform code to phy-miphy40lp driver.
>>>
>>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>>> Cc: Viresh Kumar <viresh.linux@gmail.com>
>>> Cc: Tejun Heo <tj@kernel.org>
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
>>> Cc: spear-devel at list.st.com
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: devicetree at vger.kernel.org
>>> Cc: linux-ide at vger.kernel.org
>>> Cc: linux-kernel at vger.kernel.org
>>> ---
>>>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>>>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>>>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
>>>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>>>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
>>>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
>>>  arch/arm/mach-spear/Kconfig                        |   2 +
>>>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
>>>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
>>
>> It would be better if you can split this patch. Keep arch/ in separate patch
>> and drivers/ in separate patch.
> 
> Code is actually moving from arch to driver. Therefore I kept it in
> same patch.
> 
>>>  9 files changed, 266 insertions(+), 136 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>>  static const char * const spear1340_dt_board_compat[] = {
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> index d478c14..cc7f45d 100644
>>> --- a/drivers/phy/phy-miphy40lp.c
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -8,6 +8,7 @@
>>>   * it under the terms of the GNU General Public License version 2 as
>>>   * published by the Free Software Foundation.
>>>   *
>>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>>>   */
>>>  
>>>  #include <linux/delay.h>
>>> @@ -19,6 +20,60 @@
>>>  #include <linux/phy/phy.h>
>>>  #include <linux/regmap.h>
>>>  
>>> +/* SPEAr1340 Registers */
>>> +/* Power Management Registers */
>>> +#define SPEAR1340_PCM_CFG			0x100
>>> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
>>> +#define SPEAR1340_PCM_WKUP_CFG			0x104
>>> +#define SPEAR1340_SWITCH_CTR			0x108
>>> +
>>> +#define SPEAR1340_PERIP1_SW_RST			0x318
>>> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
>>> +#define SPEAR1340_PERIP2_SW_RST			0x31C
>>> +#define SPEAR1340_PERIP3_SW_RST			0x320
>>> +
>>> +/* PCIE - SATA configuration registers */
>>> +#define SPEAR1340_PCIE_SATA_CFG			0x424
>>> +	/* PCIE CFG MASks */
>>> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
>>
>> use BIT() wherever possible.
> 
> OK.
> 
>>> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
>>> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
>>> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
>>> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
>>> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
>>> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
>>> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
>>> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
>>> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
>>> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
>>> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
>>> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
>>> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
>>> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
>>> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
>>> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
>>> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
>>> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
>>> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
>>> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
>>> +
>>> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
>>> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
>>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
>>> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
>>> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
>>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
>>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
>>> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
>>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
>>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>>> +
>>>  enum phy_mode {
>>>  	SATA,
>>>  	PCIE,
>>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>>>  	u32			id;
>>>  };
>>>  
>>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>
>> The function name format here differs from what you have already added. It will
>> be good to have consistent name in the file.
> 
> You mean to pass "struct phy *phy" in all the internal functions too?

No. I meant let all the function names begin with miphy40lp_.
> 
>>> +{
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> +			SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> +			SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> +			SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> +	/* Switch on sata power domain */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> +	msleep(20);
>>> +	/* Disable PCIE SATA Controller reset */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA, 0);
>>> +	msleep(20);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> +			SPEAR1340_PCIE_SATA_CFG_MASK, 0);
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> +			SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
>>> +
>>> +	/* Enable PCIE SATA Controller reset */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA,
>>> +			SPEAR1340_PERIP1_SW_RST_SATA);
>>> +	msleep(20);
>>> +	/* Switch off sata power domain */
>>> +	regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> +			SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
>>> +	msleep(20);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> +	if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>>
>> This compatible value is a bit confusing since it doesn't have 'sata' in it.
>> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> 
> same spear1340 miphy is used for sata as well as for pcie. sata or
> pcie mode is selected using mode args passed in phys.

Alright. Got it while reading the next patch ;-)

Thanks
Kishon

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
  2014-02-06  8:01         ` Kishon Vijay Abraham I
  (?)
@ 2014-02-06  8:07             ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  8:07 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd-r2nGTMty4D4, Viresh Kumar, Tejun Heo, spear-devel,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-ide-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

On Thu, Feb 06, 2014 at 04:01:25PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> > On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ahci driver needs some platform specific functions which are called at
> >>> init, exit, suspend and resume conditions. Till now these functions were
> >>> present in a platform driver with a fixme notes.
> >>>
> >>> Similar functions modifying same set of registers will also be needed in
> >>> case of PCIe phy init/exit.
> >>>
> >>> So move all these SATA platform code to phy-miphy40lp driver.
> >>>
> >>> Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> >>> Tested-by: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> >>> Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >>> Cc: Tejun Heo <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >>> Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> >>> Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> >>> Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> >>> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> >>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >>> Cc: linux-ide-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >>> ---
> >>>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
> >>>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
> >>>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
> >>>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
> >>>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
> >>>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
> >>>  arch/arm/mach-spear/Kconfig                        |   2 +
> >>>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
> >>>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
> >>
> >> It would be better if you can split this patch. Keep arch/ in separate patch
> >> and drivers/ in separate patch.
> > 
> > Code is actually moving from arch to driver. Therefore I kept it in
> > same patch.
> > 
> >>>  9 files changed, 266 insertions(+), 136 deletions(-)
> >>>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >>>
> >> .
> >> .
> >> <snip>
> >> .
> >> .
> >>>  static const char * const spear1340_dt_board_compat[] = {
> >>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> >>> index d478c14..cc7f45d 100644
> >>> --- a/drivers/phy/phy-miphy40lp.c
> >>> +++ b/drivers/phy/phy-miphy40lp.c
> >>> @@ -8,6 +8,7 @@
> >>>   * it under the terms of the GNU General Public License version 2 as
> >>>   * published by the Free Software Foundation.
> >>>   *
> >>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >>>   */
> >>>  
> >>>  #include <linux/delay.h>
> >>> @@ -19,6 +20,60 @@
> >>>  #include <linux/phy/phy.h>
> >>>  #include <linux/regmap.h>
> >>>  
> >>> +/* SPEAr1340 Registers */
> >>> +/* Power Management Registers */
> >>> +#define SPEAR1340_PCM_CFG			0x100
> >>> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> >>> +#define SPEAR1340_PCM_WKUP_CFG			0x104
> >>> +#define SPEAR1340_SWITCH_CTR			0x108
> >>> +
> >>> +#define SPEAR1340_PERIP1_SW_RST			0x318
> >>> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> >>> +#define SPEAR1340_PERIP2_SW_RST			0x31C
> >>> +#define SPEAR1340_PERIP3_SW_RST			0x320
> >>> +
> >>> +/* PCIE - SATA configuration registers */
> >>> +#define SPEAR1340_PCIE_SATA_CFG			0x424
> >>> +	/* PCIE CFG MASks */
> >>> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> >>
> >> use BIT() wherever possible.
> > 
> > OK.
> > 
> >>> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> >>> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> >>> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> >>> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> >>> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> >>> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> >>> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> >>> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> >>> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> >>> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> >>> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> >>> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> >>> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> >>> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> >>> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> >>> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> >>> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> >>> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> >>> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> >>> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> >>> +
> >>> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> >>> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> >>> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> >>> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> >>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> >>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> >>> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> >>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> >>> +
> >>>  enum phy_mode {
> >>>  	SATA,
> >>>  	PCIE,
> >>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >>>  	u32			id;
> >>>  };
> >>>  
> >>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> >>
> >> The function name format here differs from what you have already added. It will
> >> be good to have consistent name in the file.
> > 
> > You mean to pass "struct phy *phy" in all the internal functions too?
> 
> No. I meant let all the function names begin with miphy40lp_.

okkk.. miphy40lp_spear1340_sata_init looks better :)

Rgds
Pratyush

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^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  8:07             ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  8:07 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: arnd, Viresh Kumar, Tejun Heo, spear-devel, linux-arm-kernel,
	devicetree, linux-ide, linux-kernel

On Thu, Feb 06, 2014 at 04:01:25PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> > On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ahci driver needs some platform specific functions which are called at
> >>> init, exit, suspend and resume conditions. Till now these functions were
> >>> present in a platform driver with a fixme notes.
> >>>
> >>> Similar functions modifying same set of registers will also be needed in
> >>> case of PCIe phy init/exit.
> >>>
> >>> So move all these SATA platform code to phy-miphy40lp driver.
> >>>
> >>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> >>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> >>> Cc: Viresh Kumar <viresh.linux@gmail.com>
> >>> Cc: Tejun Heo <tj@kernel.org>
> >>> Cc: Arnd Bergmann <arnd@arndb.de>
> >>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> >>> Cc: spear-devel@list.st.com
> >>> Cc: linux-arm-kernel@lists.infradead.org
> >>> Cc: devicetree@vger.kernel.org
> >>> Cc: linux-ide@vger.kernel.org
> >>> Cc: linux-kernel@vger.kernel.org
> >>> ---
> >>>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
> >>>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
> >>>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
> >>>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
> >>>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
> >>>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
> >>>  arch/arm/mach-spear/Kconfig                        |   2 +
> >>>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
> >>>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
> >>
> >> It would be better if you can split this patch. Keep arch/ in separate patch
> >> and drivers/ in separate patch.
> > 
> > Code is actually moving from arch to driver. Therefore I kept it in
> > same patch.
> > 
> >>>  9 files changed, 266 insertions(+), 136 deletions(-)
> >>>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >>>
> >> .
> >> .
> >> <snip>
> >> .
> >> .
> >>>  static const char * const spear1340_dt_board_compat[] = {
> >>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> >>> index d478c14..cc7f45d 100644
> >>> --- a/drivers/phy/phy-miphy40lp.c
> >>> +++ b/drivers/phy/phy-miphy40lp.c
> >>> @@ -8,6 +8,7 @@
> >>>   * it under the terms of the GNU General Public License version 2 as
> >>>   * published by the Free Software Foundation.
> >>>   *
> >>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >>>   */
> >>>  
> >>>  #include <linux/delay.h>
> >>> @@ -19,6 +20,60 @@
> >>>  #include <linux/phy/phy.h>
> >>>  #include <linux/regmap.h>
> >>>  
> >>> +/* SPEAr1340 Registers */
> >>> +/* Power Management Registers */
> >>> +#define SPEAR1340_PCM_CFG			0x100
> >>> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> >>> +#define SPEAR1340_PCM_WKUP_CFG			0x104
> >>> +#define SPEAR1340_SWITCH_CTR			0x108
> >>> +
> >>> +#define SPEAR1340_PERIP1_SW_RST			0x318
> >>> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> >>> +#define SPEAR1340_PERIP2_SW_RST			0x31C
> >>> +#define SPEAR1340_PERIP3_SW_RST			0x320
> >>> +
> >>> +/* PCIE - SATA configuration registers */
> >>> +#define SPEAR1340_PCIE_SATA_CFG			0x424
> >>> +	/* PCIE CFG MASks */
> >>> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> >>
> >> use BIT() wherever possible.
> > 
> > OK.
> > 
> >>> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> >>> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> >>> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> >>> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> >>> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> >>> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> >>> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> >>> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> >>> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> >>> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> >>> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> >>> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> >>> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> >>> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> >>> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> >>> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> >>> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> >>> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> >>> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> >>> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> >>> +
> >>> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> >>> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> >>> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> >>> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> >>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> >>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> >>> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> >>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> >>> +
> >>>  enum phy_mode {
> >>>  	SATA,
> >>>  	PCIE,
> >>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >>>  	u32			id;
> >>>  };
> >>>  
> >>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> >>
> >> The function name format here differs from what you have already added. It will
> >> be good to have consistent name in the file.
> > 
> > You mean to pass "struct phy *phy" in all the internal functions too?
> 
> No. I meant let all the function names begin with miphy40lp_.

okkk.. miphy40lp_spear1340_sata_init looks better :)

Rgds
Pratyush


^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
@ 2014-02-06  8:07             ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06  8:07 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Feb 06, 2014 at 04:01:25PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> > On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ahci driver needs some platform specific functions which are called at
> >>> init, exit, suspend and resume conditions. Till now these functions were
> >>> present in a platform driver with a fixme notes.
> >>>
> >>> Similar functions modifying same set of registers will also be needed in
> >>> case of PCIe phy init/exit.
> >>>
> >>> So move all these SATA platform code to phy-miphy40lp driver.
> >>>
> >>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> >>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> >>> Cc: Viresh Kumar <viresh.linux@gmail.com>
> >>> Cc: Tejun Heo <tj@kernel.org>
> >>> Cc: Arnd Bergmann <arnd@arndb.de>
> >>> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> >>> Cc: spear-devel at list.st.com
> >>> Cc: linux-arm-kernel at lists.infradead.org
> >>> Cc: devicetree at vger.kernel.org
> >>> Cc: linux-ide at vger.kernel.org
> >>> Cc: linux-kernel at vger.kernel.org
> >>> ---
> >>>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
> >>>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
> >>>  arch/arm/boot/dts/spear1310.dtsi                   |  39 +++-
> >>>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
> >>>  arch/arm/boot/dts/spear1340.dtsi                   |  13 +-
> >>>  arch/arm/boot/dts/spear13xx.dtsi                   |   5 +
> >>>  arch/arm/mach-spear/Kconfig                        |   2 +
> >>>  arch/arm/mach-spear/spear1340.c                    | 127 +------------
> >>>  drivers/phy/phy-miphy40lp.c                        | 204 ++++++++++++++++++++-
> >>
> >> It would be better if you can split this patch. Keep arch/ in separate patch
> >> and drivers/ in separate patch.
> > 
> > Code is actually moving from arch to driver. Therefore I kept it in
> > same patch.
> > 
> >>>  9 files changed, 266 insertions(+), 136 deletions(-)
> >>>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >>>
> >> .
> >> .
> >> <snip>
> >> .
> >> .
> >>>  static const char * const spear1340_dt_board_compat[] = {
> >>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> >>> index d478c14..cc7f45d 100644
> >>> --- a/drivers/phy/phy-miphy40lp.c
> >>> +++ b/drivers/phy/phy-miphy40lp.c
> >>> @@ -8,6 +8,7 @@
> >>>   * it under the terms of the GNU General Public License version 2 as
> >>>   * published by the Free Software Foundation.
> >>>   *
> >>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >>>   */
> >>>  
> >>>  #include <linux/delay.h>
> >>> @@ -19,6 +20,60 @@
> >>>  #include <linux/phy/phy.h>
> >>>  #include <linux/regmap.h>
> >>>  
> >>> +/* SPEAr1340 Registers */
> >>> +/* Power Management Registers */
> >>> +#define SPEAR1340_PCM_CFG			0x100
> >>> +	#define SPEAR1340_PCM_CFG_SATA_POWER_EN	0x800
> >>> +#define SPEAR1340_PCM_WKUP_CFG			0x104
> >>> +#define SPEAR1340_SWITCH_CTR			0x108
> >>> +
> >>> +#define SPEAR1340_PERIP1_SW_RST			0x318
> >>> +	#define SPEAR1340_PERIP1_SW_RST_SATA	0x1000
> >>> +#define SPEAR1340_PERIP2_SW_RST			0x31C
> >>> +#define SPEAR1340_PERIP3_SW_RST			0x320
> >>> +
> >>> +/* PCIE - SATA configuration registers */
> >>> +#define SPEAR1340_PCIE_SATA_CFG			0x424
> >>> +	/* PCIE CFG MASks */
> >>> +	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> >>
> >> use BIT() wherever possible.
> > 
> > OK.
> > 
> >>> +	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> >>> +	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> >>> +	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> >>> +	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> >>> +	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> >>> +	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
> >>> +	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
> >>> +	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
> >>> +	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
> >>> +	#define SPEAR1340_PCIE_SATA_CFG_MASK		0xF1F
> >>> +	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
> >>> +			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> >>> +			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> >>> +			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> >>> +			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> >>> +	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
> >>> +			SPEAR1340_SATA_CFG_PM_CLK_EN | \
> >>> +			SPEAR1340_SATA_CFG_POWERUP_RESET | \
> >>> +			SPEAR1340_SATA_CFG_RX_CLK_EN | \
> >>> +			SPEAR1340_SATA_CFG_TX_CLK_EN)
> >>> +
> >>> +#define SPEAR1340_PCIE_MIPHY_CFG		0x428
> >>> +	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
> >>> +	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
> >>> +	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
> >>> +	#define SPEAR1340_PCIE_MIPHY_CFG_MASK		0xF80000FF
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> >>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> +			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> >>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> >>> +			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> >>> +	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> >>> +			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> +			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> >>> +
> >>>  enum phy_mode {
> >>>  	SATA,
> >>>  	PCIE,
> >>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >>>  	u32			id;
> >>>  };
> >>>  
> >>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> >>
> >> The function name format here differs from what you have already added. It will
> >> be good to have consistent name in the file.
> > 
> > You mean to pass "struct phy *phy" in all the internal functions too?
> 
> No. I meant let all the function names begin with miphy40lp_.

okkk.. miphy40lp_spear1340_sata_init looks better :)

Rgds
Pratyush

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  2014-02-06  4:44   ` Pratyush Anand
@ 2014-02-06 15:37     ` Arnd Bergmann
  -1 siblings, 0 replies; 49+ messages in thread
From: Arnd Bergmann @ 2014-02-06 15:37 UTC (permalink / raw)
  To: Pratyush Anand
  Cc: Kishon Vijay Abraham I, spear-devel, linux-arm-kernel, linux-kernel

On Thursday 06 February 2014, Pratyush Anand wrote:
> +static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +       u32 mask;
> +
> +       switch (phypriv->id) {
> +       case 0:
> +               mask = SPEAR1310_PCIE_CFG_MASK(0);
> +               break;
> +       case 1:
> +               mask = SPEAR1310_PCIE_CFG_MASK(1);
> +               break;
> +       case 2:
> +               mask = SPEAR1310_PCIE_CFG_MASK(2);
> +               break;
> +       default:
> +               return -EINVAL;
> +       }
> +
> +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
> +                       SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
> +
> +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> +                       SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
> +
> +       return 0;
> +}

hmm, you set the mask based on the id, but then use the macro below
and ignore the mask?

> +
> +static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +               return spear1340_pcie_miphy_init(phypriv);
> +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> +               return spear1310_pcie_miphy_init(phypriv);
> +       else
> +               return -EINVAL;
> +}
> +
> +static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +               return spear1340_pcie_miphy_exit(phypriv);
> +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> +               return spear1310_pcie_miphy_exit(phypriv);
> +       else
> +               return -EINVAL;
> +}

I think it's better to make this code table-driven. Rather than checking
'of_device_is_compatible()', it's much easier to add a .data field to
the of_device_id array that describes the PHY. You can use .data to
point to a structure containing per-device function pointers or
(better) values and offsets to be used.

	Arnd

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
@ 2014-02-06 15:37     ` Arnd Bergmann
  0 siblings, 0 replies; 49+ messages in thread
From: Arnd Bergmann @ 2014-02-06 15:37 UTC (permalink / raw)
  To: linux-arm-kernel

On Thursday 06 February 2014, Pratyush Anand wrote:
> +static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +       u32 mask;
> +
> +       switch (phypriv->id) {
> +       case 0:
> +               mask = SPEAR1310_PCIE_CFG_MASK(0);
> +               break;
> +       case 1:
> +               mask = SPEAR1310_PCIE_CFG_MASK(1);
> +               break;
> +       case 2:
> +               mask = SPEAR1310_PCIE_CFG_MASK(2);
> +               break;
> +       default:
> +               return -EINVAL;
> +       }
> +
> +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
> +                       SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
> +
> +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> +                       SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
> +
> +       return 0;
> +}

hmm, you set the mask based on the id, but then use the macro below
and ignore the mask?

> +
> +static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +               return spear1340_pcie_miphy_init(phypriv);
> +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> +               return spear1310_pcie_miphy_init(phypriv);
> +       else
> +               return -EINVAL;
> +}
> +
> +static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> +               return spear1340_pcie_miphy_exit(phypriv);
> +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> +               return spear1310_pcie_miphy_exit(phypriv);
> +       else
> +               return -EINVAL;
> +}

I think it's better to make this code table-driven. Rather than checking
'of_device_is_compatible()', it's much easier to add a .data field to
the of_device_id array that describes the PHY. You can use .data to
point to a structure containing per-device function pointers or
(better) values and offsets to be used.

	Arnd

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
  2014-02-06  4:44 ` Pratyush Anand
  (?)
@ 2014-02-06 17:30   ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06 17:30 UTC (permalink / raw)
  To: Pratyush Anand, Arnd Bergmann
  Cc: devicetree, linux-pci, spear-devel, linux-kernel, linux-ide,
	linux-arm-kernel

Hi Arnd,

Do you see any more improvement in this series.

Else we will send V5 (probably the final one) with modifications for
Kishon's comment.

Regards
Pratyush

On Thu, Feb 6, 2014 at 10:14 AM, Pratyush Anand <pratyush.anand@st.com> wrote:
> First three patches are improvement and fixes for SPEAr13xx support.
> Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
> wrapper. Patch 7 add support for SPEAr13xx PCIe.
>
> These pathes are tested with linux-3.14-rc1 with following patch on the top of
> it:
> Author: Balaji T K <balajitk@ti.com>
> Date:   Mon Jan 20 16:41:27 2014 +0200
>
>     ata: ahci_platform: Manage SATA PHY
>
> Tested with SPEAr1310 evaluation board:
>         - INTEL PRO 100/100 EP card
>         - USB xhci gen2 card
>         - Above cards connected through LeCROY PTC switch
>
> Modifications for SATA are tested with SPEAr1340-evb board
>
> Changes since v3:
> - Phy driver renamed to phy-miphy40lp
> - ahci phy hook patch used as suggested by Arnd
> - Incorporated other minor comments from v3
>
> Changes since v2:
> - Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
>   the phy framework
> - Modify ahci driver to include phy hooks
> - phy-core driver modifications for subsys_initcall()
>
> Changes since v1:
> - Few patches of the series are already accepted and applied to mainline e.g.
>  pcie designware driver improvements,fixes for IO translation bug, PCIe dw
>  driver maintainer. So dropped these from v2.
> - Incorporated comment to move the common/reset PCIe code to the seperate driver
> - PCIe and SATA share common PHY configuration registers, so move SATA
>  platform code to the system config driver
> Fourth patch is improves pcie designware driver and fixes the IO
> translation bug. IO translation bug fix leads to the working of PCIe EP devices
> connected to RC through switch.
>
> PCIe driver support for SPEAr1310/40 platform board is added.
>
> These patches are tested with SPEAr1310 evaluation board:
>         - INTEL PRO 100/100 EP card
>         - USB xhci gen2 card
>         - Above cards connected through LeCROY PTC switch
>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ide@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: spear-devel@list.st.com
> Cc: linux-kernel@vger.kernel.org
>
> Mohit Kumar (2):
>   SPEAr13xx: defconfig: Update
>   MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
>
> Pratyush Anand (6):
>   clk: SPEAr13xx: Fix pcie clock name
>   SPEAr13xx: Fix static mapping table
>   phy: st-miphy-40lp: Add skeleton driver
>   SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
>   phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
>   pcie: SPEAr13xx: Add designware pcie support
>
>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>  .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 +
>  MAINTAINERS                                        |   6 +
>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1310.dtsi                   |  96 +++-
>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1340.dtsi                   |  32 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |  10 +-
>  arch/arm/configs/spear13xx_defconfig               |  15 +
>  arch/arm/mach-spear/Kconfig                        |   3 +
>  arch/arm/mach-spear/include/mach/spear.h           |   4 +-
>  arch/arm/mach-spear/spear1340.c                    | 127 +----
>  arch/arm/mach-spear/spear13xx.c                    |   2 +-
>  drivers/clk/spear/spear1310_clock.c                |   6 +-
>  drivers/clk/spear/spear1340_clock.c                |   2 +-
>  drivers/pci/host/Kconfig                           |   5 +
>  drivers/pci/host/Makefile                          |   1 +
>  drivers/pci/host/pcie-spear13xx.c                  | 414 ++++++++++++++++
>  drivers/phy/Kconfig                                |   6 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-miphy40lp.c                        | 544 +++++++++++++++++++++
>  22 files changed, 1166 insertions(+), 139 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>  create mode 100644 drivers/pci/host/pcie-spear13xx.c
>  create mode 100644 drivers/phy/phy-miphy40lp.c
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
@ 2014-02-06 17:30   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06 17:30 UTC (permalink / raw)
  To: Pratyush Anand, Arnd Bergmann
  Cc: devicetree, linux-pci, spear-devel, linux-kernel, linux-ide,
	linux-arm-kernel

Hi Arnd,

Do you see any more improvement in this series.

Else we will send V5 (probably the final one) with modifications for
Kishon's comment.

Regards
Pratyush

On Thu, Feb 6, 2014 at 10:14 AM, Pratyush Anand <pratyush.anand@st.com> wrote:
> First three patches are improvement and fixes for SPEAr13xx support.
> Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
> wrapper. Patch 7 add support for SPEAr13xx PCIe.
>
> These pathes are tested with linux-3.14-rc1 with following patch on the top of
> it:
> Author: Balaji T K <balajitk@ti.com>
> Date:   Mon Jan 20 16:41:27 2014 +0200
>
>     ata: ahci_platform: Manage SATA PHY
>
> Tested with SPEAr1310 evaluation board:
>         - INTEL PRO 100/100 EP card
>         - USB xhci gen2 card
>         - Above cards connected through LeCROY PTC switch
>
> Modifications for SATA are tested with SPEAr1340-evb board
>
> Changes since v3:
> - Phy driver renamed to phy-miphy40lp
> - ahci phy hook patch used as suggested by Arnd
> - Incorporated other minor comments from v3
>
> Changes since v2:
> - Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
>   the phy framework
> - Modify ahci driver to include phy hooks
> - phy-core driver modifications for subsys_initcall()
>
> Changes since v1:
> - Few patches of the series are already accepted and applied to mainline e.g.
>  pcie designware driver improvements,fixes for IO translation bug, PCIe dw
>  driver maintainer. So dropped these from v2.
> - Incorporated comment to move the common/reset PCIe code to the seperate driver
> - PCIe and SATA share common PHY configuration registers, so move SATA
>  platform code to the system config driver
> Fourth patch is improves pcie designware driver and fixes the IO
> translation bug. IO translation bug fix leads to the working of PCIe EP devices
> connected to RC through switch.
>
> PCIe driver support for SPEAr1310/40 platform board is added.
>
> These patches are tested with SPEAr1310 evaluation board:
>         - INTEL PRO 100/100 EP card
>         - USB xhci gen2 card
>         - Above cards connected through LeCROY PTC switch
>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-ide@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: spear-devel@list.st.com
> Cc: linux-kernel@vger.kernel.org
>
> Mohit Kumar (2):
>   SPEAr13xx: defconfig: Update
>   MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
>
> Pratyush Anand (6):
>   clk: SPEAr13xx: Fix pcie clock name
>   SPEAr13xx: Fix static mapping table
>   phy: st-miphy-40lp: Add skeleton driver
>   SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
>   phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
>   pcie: SPEAr13xx: Add designware pcie support
>
>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>  .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 +
>  MAINTAINERS                                        |   6 +
>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1310.dtsi                   |  96 +++-
>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1340.dtsi                   |  32 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |  10 +-
>  arch/arm/configs/spear13xx_defconfig               |  15 +
>  arch/arm/mach-spear/Kconfig                        |   3 +
>  arch/arm/mach-spear/include/mach/spear.h           |   4 +-
>  arch/arm/mach-spear/spear1340.c                    | 127 +----
>  arch/arm/mach-spear/spear13xx.c                    |   2 +-
>  drivers/clk/spear/spear1310_clock.c                |   6 +-
>  drivers/clk/spear/spear1340_clock.c                |   2 +-
>  drivers/pci/host/Kconfig                           |   5 +
>  drivers/pci/host/Makefile                          |   1 +
>  drivers/pci/host/pcie-spear13xx.c                  | 414 ++++++++++++++++
>  drivers/phy/Kconfig                                |   6 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-miphy40lp.c                        | 544 +++++++++++++++++++++
>  22 files changed, 1166 insertions(+), 139 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>  create mode 100644 drivers/pci/host/pcie-spear13xx.c
>  create mode 100644 drivers/phy/phy-miphy40lp.c
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support
@ 2014-02-06 17:30   ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-06 17:30 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Arnd,

Do you see any more improvement in this series.

Else we will send V5 (probably the final one) with modifications for
Kishon's comment.

Regards
Pratyush

On Thu, Feb 6, 2014 at 10:14 AM, Pratyush Anand <pratyush.anand@st.com> wrote:
> First three patches are improvement and fixes for SPEAr13xx support.
> Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
> wrapper. Patch 7 add support for SPEAr13xx PCIe.
>
> These pathes are tested with linux-3.14-rc1 with following patch on the top of
> it:
> Author: Balaji T K <balajitk@ti.com>
> Date:   Mon Jan 20 16:41:27 2014 +0200
>
>     ata: ahci_platform: Manage SATA PHY
>
> Tested with SPEAr1310 evaluation board:
>         - INTEL PRO 100/100 EP card
>         - USB xhci gen2 card
>         - Above cards connected through LeCROY PTC switch
>
> Modifications for SATA are tested with SPEAr1340-evb board
>
> Changes since v3:
> - Phy driver renamed to phy-miphy40lp
> - ahci phy hook patch used as suggested by Arnd
> - Incorporated other minor comments from v3
>
> Changes since v2:
> - Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
>   the phy framework
> - Modify ahci driver to include phy hooks
> - phy-core driver modifications for subsys_initcall()
>
> Changes since v1:
> - Few patches of the series are already accepted and applied to mainline e.g.
>  pcie designware driver improvements,fixes for IO translation bug, PCIe dw
>  driver maintainer. So dropped these from v2.
> - Incorporated comment to move the common/reset PCIe code to the seperate driver
> - PCIe and SATA share common PHY configuration registers, so move SATA
>  platform code to the system config driver
> Fourth patch is improves pcie designware driver and fixes the IO
> translation bug. IO translation bug fix leads to the working of PCIe EP devices
> connected to RC through switch.
>
> PCIe driver support for SPEAr1310/40 platform board is added.
>
> These patches are tested with SPEAr1310 evaluation board:
>         - INTEL PRO 100/100 EP card
>         - USB xhci gen2 card
>         - Above cards connected through LeCROY PTC switch
>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> Cc: linux-ide at vger.kernel.org
> Cc: linux-pci at vger.kernel.org
> Cc: spear-devel at list.st.com
> Cc: linux-kernel at vger.kernel.org
>
> Mohit Kumar (2):
>   SPEAr13xx: defconfig: Update
>   MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
>
> Pratyush Anand (6):
>   clk: SPEAr13xx: Fix pcie clock name
>   SPEAr13xx: Fix static mapping table
>   phy: st-miphy-40lp: Add skeleton driver
>   SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
>   phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
>   pcie: SPEAr13xx: Add designware pcie support
>
>  .../devicetree/bindings/arm/spear-misc.txt         |   4 +
>  .../devicetree/bindings/pci/spear13xx-pcie.txt     |   7 +
>  .../devicetree/bindings/phy/st-miphy40lp.txt       |  12 +
>  MAINTAINERS                                        |   6 +
>  arch/arm/boot/dts/spear1310-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1310.dtsi                   |  96 +++-
>  arch/arm/boot/dts/spear1340-evb.dts                |   4 +
>  arch/arm/boot/dts/spear1340.dtsi                   |  32 +-
>  arch/arm/boot/dts/spear13xx.dtsi                   |  10 +-
>  arch/arm/configs/spear13xx_defconfig               |  15 +
>  arch/arm/mach-spear/Kconfig                        |   3 +
>  arch/arm/mach-spear/include/mach/spear.h           |   4 +-
>  arch/arm/mach-spear/spear1340.c                    | 127 +----
>  arch/arm/mach-spear/spear13xx.c                    |   2 +-
>  drivers/clk/spear/spear1310_clock.c                |   6 +-
>  drivers/clk/spear/spear1340_clock.c                |   2 +-
>  drivers/pci/host/Kconfig                           |   5 +
>  drivers/pci/host/Makefile                          |   1 +
>  drivers/pci/host/pcie-spear13xx.c                  | 414 ++++++++++++++++
>  drivers/phy/Kconfig                                |   6 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-miphy40lp.c                        | 544 +++++++++++++++++++++
>  22 files changed, 1166 insertions(+), 139 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
>  create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>  create mode 100644 drivers/pci/host/pcie-spear13xx.c
>  create mode 100644 drivers/phy/phy-miphy40lp.c
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  2014-02-06 15:37     ` Arnd Bergmann
@ 2014-02-07  3:54       ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-07  3:54 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Kishon Vijay Abraham I, spear-devel, linux-arm-kernel, linux-kernel

Hi Arnd,

On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> On Thursday 06 February 2014, Pratyush Anand wrote:
> > +static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +       u32 mask;
> > +
> > +       switch (phypriv->id) {
> > +       case 0:
> > +               mask = SPEAR1310_PCIE_CFG_MASK(0);
> > +               break;
> > +       case 1:
> > +               mask = SPEAR1310_PCIE_CFG_MASK(1);
> > +               break;
> > +       case 2:
> > +               mask = SPEAR1310_PCIE_CFG_MASK(2);
> > +               break;
> > +       default:
> > +               return -EINVAL;
> > +       }
> > +
> > +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
> > +                       SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
> > +
> > +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> > +                       SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
> > +
> > +       return 0;
> > +}
> 
> hmm, you set the mask based on the id, but then use the macro below
> and ignore the mask?

Blunder, no need of switch case here :(
Will correct.

> 
> > +
> > +static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +               return spear1340_pcie_miphy_init(phypriv);
> > +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> > +               return spear1310_pcie_miphy_init(phypriv);
> > +       else
> > +               return -EINVAL;
> > +}
> > +
> > +static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +               return spear1340_pcie_miphy_exit(phypriv);
> > +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> > +               return spear1310_pcie_miphy_exit(phypriv);
> > +       else
> > +               return -EINVAL;
> > +}
> 
> I think it's better to make this code table-driven. Rather than checking
> 'of_device_is_compatible()', it's much easier to add a .data field to
> the of_device_id array that describes the PHY. You can use .data to
> point to a structure containing per-device function pointers or
> (better) values and offsets to be used.

Sounds a better idea. will reduce code size a lot. Thanks.

Regards
Pratyush

> 
> 	Arnd

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
@ 2014-02-07  3:54       ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-07  3:54 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Arnd,

On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> On Thursday 06 February 2014, Pratyush Anand wrote:
> > +static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +       u32 mask;
> > +
> > +       switch (phypriv->id) {
> > +       case 0:
> > +               mask = SPEAR1310_PCIE_CFG_MASK(0);
> > +               break;
> > +       case 1:
> > +               mask = SPEAR1310_PCIE_CFG_MASK(1);
> > +               break;
> > +       case 2:
> > +               mask = SPEAR1310_PCIE_CFG_MASK(2);
> > +               break;
> > +       default:
> > +               return -EINVAL;
> > +       }
> > +
> > +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
> > +                       SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
> > +
> > +       regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> > +                       SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
> > +
> > +       return 0;
> > +}
> 
> hmm, you set the mask based on the id, but then use the macro below
> and ignore the mask?

Blunder, no need of switch case here :(
Will correct.

> 
> > +
> > +static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +               return spear1340_pcie_miphy_init(phypriv);
> > +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> > +               return spear1310_pcie_miphy_init(phypriv);
> > +       else
> > +               return -EINVAL;
> > +}
> > +
> > +static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > +       if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > +               return spear1340_pcie_miphy_exit(phypriv);
> > +       else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> > +               return spear1310_pcie_miphy_exit(phypriv);
> > +       else
> > +               return -EINVAL;
> > +}
> 
> I think it's better to make this code table-driven. Rather than checking
> 'of_device_is_compatible()', it's much easier to add a .data field to
> the of_device_id array that describes the PHY. You can use .data to
> point to a structure containing per-device function pointers or
> (better) values and offsets to be used.

Sounds a better idea. will reduce code size a lot. Thanks.

Regards
Pratyush

> 
> 	Arnd

^ permalink raw reply	[flat|nested] 49+ messages in thread

* Re: [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
  2014-02-07  3:54       ` Pratyush Anand
@ 2014-02-07  6:43         ` Pratyush Anand
  -1 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-07  6:43 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Kishon Vijay Abraham I, spear-devel, linux-arm-kernel, linux-kernel

Hi Arnd,

On Fri, Feb 07, 2014 at 11:54:30AM +0800, Pratyush ANAND wrote:
> Hi Arnd,
> 
> On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> > On Thursday 06 February 2014, Pratyush Anand wrote:
> > 

[...]

> > I think it's better to make this code table-driven. Rather than checking
> > 'of_device_is_compatible()', it's much easier to add a .data field to
> > the of_device_id array that describes the PHY. You can use .data to
> > point to a structure containing per-device function pointers or
> > (better) values and offsets to be used.

values and offset would be good as long as we do not need to write on
conditional read status. In our case its OK, as we do not need to
write conditionally. But, would it be a good idea to go that way?

Regards
Pratyush

> 
> Sounds a better idea. will reduce code size a lot. Thanks.
> 
> Regards
> Pratyush
> 
> > 
> > 	Arnd

^ permalink raw reply	[flat|nested] 49+ messages in thread

* [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
@ 2014-02-07  6:43         ` Pratyush Anand
  0 siblings, 0 replies; 49+ messages in thread
From: Pratyush Anand @ 2014-02-07  6:43 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Arnd,

On Fri, Feb 07, 2014 at 11:54:30AM +0800, Pratyush ANAND wrote:
> Hi Arnd,
> 
> On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> > On Thursday 06 February 2014, Pratyush Anand wrote:
> > 

[...]

> > I think it's better to make this code table-driven. Rather than checking
> > 'of_device_is_compatible()', it's much easier to add a .data field to
> > the of_device_id array that describes the PHY. You can use .data to
> > point to a structure containing per-device function pointers or
> > (better) values and offsets to be used.

values and offset would be good as long as we do not need to write on
conditional read status. In our case its OK, as we do not need to
write conditionally. But, would it be a good idea to go that way?

Regards
Pratyush

> 
> Sounds a better idea. will reduce code size a lot. Thanks.
> 
> Regards
> Pratyush
> 
> > 
> > 	Arnd

^ permalink raw reply	[flat|nested] 49+ messages in thread

end of thread, other threads:[~2014-02-07  6:44 UTC | newest]

Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-02-06  4:44 [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support Pratyush Anand
2014-02-06  4:44 ` Pratyush Anand
2014-02-06  4:44 ` Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 1/8] clk: SPEAr13xx: Fix pcie clock name Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 2/8] SPEAr13xx: Fix static mapping table Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 3/8] SPEAr13xx: defconfig: Update Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 4/8] phy: st-miphy-40lp: Add skeleton driver Pratyush Anand
2014-02-06  4:44   ` Pratyush Anand
2014-02-06  4:44   ` Pratyush Anand
2014-02-06  6:01   ` Kishon Vijay Abraham I
2014-02-06  6:01     ` Kishon Vijay Abraham I
2014-02-06  6:01     ` Kishon Vijay Abraham I
2014-02-06  6:14     ` Pratyush Anand
2014-02-06  6:14       ` Pratyush Anand
2014-02-06  6:14       ` Pratyush Anand
2014-02-06  6:23       ` Kishon Vijay Abraham I
2014-02-06  6:23         ` Kishon Vijay Abraham I
2014-02-06  6:23         ` Kishon Vijay Abraham I
2014-02-06  6:25         ` Pratyush Anand
2014-02-06  6:25           ` Pratyush Anand
2014-02-06  6:25           ` Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 5/8] SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver Pratyush Anand
2014-02-06  4:44   ` Pratyush Anand
2014-02-06  4:44   ` Pratyush Anand
2014-02-06  6:32   ` Kishon Vijay Abraham I
2014-02-06  6:32     ` Kishon Vijay Abraham I
2014-02-06  6:32     ` Kishon Vijay Abraham I
2014-02-06  7:00     ` Pratyush Anand
2014-02-06  7:00       ` Pratyush Anand
2014-02-06  7:00       ` Pratyush Anand
2014-02-06  8:01       ` Kishon Vijay Abraham I
2014-02-06  8:01         ` Kishon Vijay Abraham I
2014-02-06  8:01         ` Kishon Vijay Abraham I
     [not found]         ` <52F34155.8010900-l0cyMroinI0@public.gmane.org>
2014-02-06  8:07           ` Pratyush Anand
2014-02-06  8:07             ` Pratyush Anand
2014-02-06  8:07             ` Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 6/8] phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support Pratyush Anand
2014-02-06  4:44   ` Pratyush Anand
2014-02-06 15:37   ` Arnd Bergmann
2014-02-06 15:37     ` Arnd Bergmann
2014-02-07  3:54     ` Pratyush Anand
2014-02-07  3:54       ` Pratyush Anand
2014-02-07  6:43       ` Pratyush Anand
2014-02-07  6:43         ` Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 7/8] pcie: SPEAr13xx: Add designware pcie support Pratyush Anand
2014-02-06  4:44 ` [PATCH V4 8/8] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer Pratyush Anand
2014-02-06 17:30 ` [PATCH V4 0/8]PCI:Add SPEAr13xx PCie support Pratyush Anand
2014-02-06 17:30   ` Pratyush Anand
2014-02-06 17:30   ` Pratyush Anand

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