From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Francois Moine Subject: [PATCH 0/3] mmc: sunxi: Changes in the host driver Date: Thu, 21 Jul 2016 08:28:01 +0200 Message-ID: Reply-To: moinejf-GANU6spQydw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Ulf Hansson , Maxime Ripard , Chen-Yu Tsai Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: linux-mmc@vger.kernel.org While testing the eMMC access in a Banana Pi M3, I found and fixed some problems: - the driver was trying to set a strange rate when clk_round_rate() was returning an error - the 'new timing mode' could not work because a register was not set - with a parent clock at 1.2GHz, the output and sample phases were not correct for the A83T Jean-Francois Moine (3): mmc: sunxi: Check the value returned by clk_round_rate mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers mmc: sunxi: Add support to the Allwinner A83T drivers/mmc/host/sunxi-mmc.c | 45 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 7 deletions(-) -- 2.9.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: moinejf@free.fr (Jean-Francois Moine) Date: Thu, 21 Jul 2016 08:28:01 +0200 Subject: [PATCH 0/3] mmc: sunxi: Changes in the host driver Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org While testing the eMMC access in a Banana Pi M3, I found and fixed some problems: - the driver was trying to set a strange rate when clk_round_rate() was returning an error - the 'new timing mode' could not work because a register was not set - with a parent clock at 1.2GHz, the output and sample phases were not correct for the A83T Jean-Francois Moine (3): mmc: sunxi: Check the value returned by clk_round_rate mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers mmc: sunxi: Add support to the Allwinner A83T drivers/mmc/host/sunxi-mmc.c | 45 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 7 deletions(-) -- 2.9.2