* [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line
@ 2019-03-29 22:39 Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 1/6] linux-user/riscv: Add the CPU type as a comment Alistair Francis
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
This patch series adds a generic RISC-V CPU that can be generated at run
time based on the ISA string specified to QEMU via the -cpu argument. This
is supported on the virt and spike boards allowing users to specify the
RISC-V extensions as well as the ISA version.
As part of the conversion we have deprecated the version specifi Spike
machines.
v2:
- Keep the any CPU for linux-user
Alistair Francis (6):
linux-user/riscv: Add the CPU type as a comment
target/riscv: Fall back to generating a RISC-V CPU
target/riscv: Create settable CPU properties
riscv: virt: Allow specifying a CPU via commandline
target/riscv: Remove the generic no MMU CPUs
riscv: Add a generic spike machine
hw/riscv/spike.c | 106 ++++++++++++++++++++++++-
hw/riscv/virt.c | 3 +-
linux-user/riscv/target_elf.h | 1 +
target/riscv/cpu.c | 141 +++++++++++++++++++++++++++++++++-
target/riscv/cpu.h | 12 ++-
5 files changed, 256 insertions(+), 7 deletions(-)
--
2.21.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Qemu-riscv] [PATCH for 4.1 v2 1/6] linux-user/riscv: Add the CPU type as a comment
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
@ 2019-03-29 22:39 ` Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/riscv/target_elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/riscv/target_elf.h b/linux-user/riscv/target_elf.h
index a6716a6aac..9dd65652ee 100644
--- a/linux-user/riscv/target_elf.h
+++ b/linux-user/riscv/target_elf.h
@@ -9,6 +9,7 @@
#define RISCV_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
+ /* TYPE_RISCV_CPU_ANY */
return "any";
}
#endif
--
2.21.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-riscv] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 1/6] linux-user/riscv: Add the CPU type as a comment Alistair Francis
@ 2019-03-29 22:39 ` Alistair Francis
2019-04-04 12:35 ` [Qemu-riscv] " Ian Campbell
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 3/6] target/riscv: Create settable CPU properties Alistair Francis
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
If a user specifies a CPU that we don't understand then we want to fall
back to a CPU generated from the ISA string.
At the moment the generated CPU is assumed to be a privledge spec
version 1.10 CPU with an MMU. This can be changed in the future.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 95 +++++++++++++++++++++++++++++++++++++++++++++-
target/riscv/cpu.h | 2 +
2 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d61bce6d55..31561c719f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qemu/error-report.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
@@ -103,6 +104,93 @@ static void set_resetvec(CPURISCVState *env, int resetvec)
#endif
}
+static void riscv_generate_cpu_init(Object *obj)
+{
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ const char *riscv_cpu = mcc->isa_str;
+ target_ulong target_misa = 0;
+ target_ulong rvxlen = 0;
+ int i;
+ bool valid = false;
+
+ for (i = 0; i < strlen(riscv_cpu); i++) {
+ if (i == 0 && riscv_cpu[i] == 'r' &&
+ riscv_cpu[i + 1] == 'v') {
+ /* Starts with "rv" */
+ i += 2;
+ if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
+ i += 2;
+ valid = true;
+ rvxlen = RV32;
+ }
+ if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
+ i += 2;
+ valid = true;
+ rvxlen = RV64;
+ }
+ }
+
+ switch (riscv_cpu[i]) {
+ case 'i':
+ if (target_misa & RVE) {
+ error_report("I and E extensions are incompatible");
+ exit(1);
+ }
+ target_misa |= RVI;
+ continue;
+ case 'e':
+ if (target_misa & RVI) {
+ error_report("I and E extensions are incompatible");
+ exit(1);
+ }
+ target_misa |= RVE;
+ continue;
+ case 'g':
+ target_misa |= RVI | RVM | RVA | RVF | RVD;
+ continue;
+ case 'm':
+ target_misa |= RVM;
+ continue;
+ case 'a':
+ target_misa |= RVA;
+ continue;
+ case 'f':
+ target_misa |= RVF;
+ continue;
+ case 'd':
+ target_misa |= RVD;
+ continue;
+ case 'c':
+ target_misa |= RVC;
+ continue;
+ case 's':
+ target_misa |= RVS;
+ continue;
+ case 'u':
+ target_misa |= RVU;
+ continue;
+ default:
+ warn_report("QEMU does not support the %c extension",
+ riscv_cpu[i]);
+ continue;
+ }
+ }
+
+ if (!valid) {
+ error_report("'%s' does not appear to be a valid RISC-V CPU",
+ riscv_cpu);
+ exit(1);
+ }
+
+ set_misa(env, rvxlen | target_misa);
+ set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
+ set_resetvec(env, DEFAULT_RSTVEC);
+ set_feature(env, RISCV_FEATURE_MMU);
+ set_feature(env, RISCV_FEATURE_PMP);
+}
+
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -178,6 +266,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj)
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
+ RISCVCPUClass *mcc;
char *typename;
char **cpuname;
@@ -188,7 +277,10 @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
g_free(typename);
if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
object_class_is_abstract(oc)) {
- return NULL;
+ /* No CPU found, try the generic CPU and pass in the ISA string */
+ oc = object_class_by_name(TYPE_RISCV_CPU_GEN);
+ mcc = RISCV_CPU_CLASS(oc);
+ mcc->isa_str = g_strdup(cpu_model);
}
return oc;
}
@@ -440,6 +532,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_init = riscv_cpu_class_init,
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_GEN, riscv_generate_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 20bce8742e..453108a855 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -48,6 +48,7 @@
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
+#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
@@ -211,6 +212,7 @@ typedef struct RISCVCPUClass {
/*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+ const char *isa_str;
} RISCVCPUClass;
/**
--
2.21.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-riscv] [PATCH for 4.1 v2 3/6] target/riscv: Create settable CPU properties
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 1/6] linux-user/riscv: Add the CPU type as a comment Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
@ 2019-03-29 22:39 ` Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 4/6] riscv: virt: Allow specifying a CPU via commandline Alistair Francis
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:39 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 52 ++++++++++++++++++++++++++++++++++++++++++----
target/riscv/cpu.h | 8 +++++++
2 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 31561c719f..b6408e0a83 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -23,6 +23,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
+#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
/* RISC-V CPU definitions */
@@ -185,12 +186,9 @@ static void riscv_generate_cpu_init(Object *obj)
}
set_misa(env, rvxlen | target_misa);
- set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_MMU);
- set_feature(env, RISCV_FEATURE_PMP);
}
+
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -388,7 +386,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ RISCVCPU *cpu = RISCV_CPU(dev);
+ CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+ int priv_version = PRIV_VERSION_1_10_0;
+ int user_version = USER_VERSION_2_02_0;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -397,6 +399,39 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ if (cpu->cfg.priv_spec) {
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+ priv_version = PRIV_VERSION_1_10_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
+ priv_version = PRIV_VERSION_1_09_1;
+ } else {
+ error_report("Unsupported privilege spec version '%s'",
+ cpu->cfg.priv_spec);
+ exit(1);
+ }
+ }
+
+ if (cpu->cfg.user_spec) {
+ if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) {
+ user_version = USER_VERSION_2_02_0;
+ } else {
+ error_report("Unsupported user spec version '%s'",
+ cpu->cfg.user_spec);
+ exit(1);
+ }
+ }
+
+ set_versions(env, user_version, priv_version);
+ set_resetvec(env, DEFAULT_RSTVEC);
+
+ if (cpu->cfg.mmu) {
+ set_feature(env, RISCV_FEATURE_MMU);
+ }
+
+ if (cpu->cfg.pmp) {
+ set_feature(env, RISCV_FEATURE_PMP);
+ }
+
riscv_cpu_register_gdb_regs_for_features(cs);
qemu_init_vcpu(cs);
@@ -418,6 +453,14 @@ static const VMStateDescription vmstate_riscv_cpu = {
.unmigratable = 1,
};
+static Property riscv_cpu_properties[] = {
+ DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec),
+ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -458,6 +501,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ dc->props = riscv_cpu_properties;
}
char *riscv_isa_string(RISCVCPU *cpu)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 453108a855..bc877d8107 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -226,6 +226,14 @@ typedef struct RISCVCPU {
CPUState parent_obj;
/*< public >*/
CPURISCVState env;
+
+ /* Configuration Settings */
+ struct {
+ char *priv_spec;
+ char *user_spec;
+ bool mmu;
+ bool pmp;
+ } cfg;
} RISCVCPU;
static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
--
2.21.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-riscv] [PATCH for 4.1 v2 4/6] riscv: virt: Allow specifying a CPU via commandline
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
` (2 preceding siblings ...)
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 3/6] target/riscv: Create settable CPU properties Alistair Francis
@ 2019-03-29 22:40 ` Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 5/6] target/riscv: Remove the generic no MMU CPUs Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 6/6] riscv: Add a generic spike machine Alistair Francis
5 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index fc4c6b306e..5b25f028ad 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -400,7 +400,7 @@ static void riscv_virt_board_init(MachineState *machine)
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
@@ -526,6 +526,7 @@ static void riscv_virt_board_machine_init(MachineClass *mc)
mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
mc->init = riscv_virt_board_init;
mc->max_cpus = 8; /* hardcoded limit in BBL */
+ mc->default_cpu_type = VIRT_CPU;
}
DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
--
2.21.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-riscv] [PATCH for 4.1 v2 5/6] target/riscv: Remove the generic no MMU CPUs
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
` (3 preceding siblings ...)
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 4/6] riscv: virt: Allow specifying a CPU via commandline Alistair Francis
@ 2019-03-29 22:40 ` Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 6/6] riscv: Add a generic spike machine Alistair Francis
5 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
These can now be specified via the command line so we no longer need
these.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 --
target/riscv/cpu.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b6408e0a83..758201331c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,13 +580,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bc877d8107..6806f602b5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -51,10 +51,8 @@
#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
--
2.21.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Qemu-riscv] [PATCH for 4.1 v2 6/6] riscv: Add a generic spike machine
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
` (4 preceding siblings ...)
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 5/6] target/riscv: Remove the generic no MMU CPUs Alistair Francis
@ 2019-03-29 22:40 ` Alistair Francis
5 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-03-29 22:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair Francis, alistair23
Add a generic spike machine (not tied to a version) and deprecate the
spike mahines that are tied to a specific version. As we can now specify
the CPU via the command line we no londer need specific versions of the
spike machines.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/spike.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 105 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 2a000a5800..9d3f7cec4d 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -39,6 +39,7 @@
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
+#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
#include "elf.h"
@@ -160,7 +161,89 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
- }
+}
+
+static void spike_board_init(MachineState *machine)
+{
+ const struct MemmapEntry *memmap = spike_memmap;
+
+ SpikeState *s = g_new0(SpikeState, 1);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ int i;
+
+ /* Initialize SOC */
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+ &error_abort);
+ object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
+ &error_abort);
+
+ /* register system main memory (actual RAM) */
+ memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
+ machine->ram_size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
+ main_mem);
+
+ /* create device tree */
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+
+ /* boot rom */
+ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
+ memmap[SPIKE_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
+ mask_rom);
+
+ if (machine->kernel_filename) {
+ load_kernel(machine->kernel_filename);
+ }
+
+ /* reset vector */
+ uint32_t reset_vec[8] = {
+ 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
+ 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
+ 0xf1402573, /* csrr a0, mhartid */
+#if defined(TARGET_RISCV32)
+ 0x0182a283, /* lw t0, 24(t0) */
+#elif defined(TARGET_RISCV64)
+ 0x0182b283, /* ld t0, 24(t0) */
+#endif
+ 0x00028067, /* jr t0 */
+ 0x00000000,
+ memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
+ 0x00000000,
+ /* dtb: */
+ };
+
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+ memmap[SPIKE_MROM].base, &address_space_memory);
+
+ /* copy in the device tree */
+ if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
+ memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
+ error_report("not enough space to store device-tree");
+ exit(1);
+ }
+ qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
+ rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
+ memmap[SPIKE_MROM].base + sizeof(reset_vec),
+ &address_space_memory);
+
+ /* initialize HTIF using symbols found in load_kernel */
+ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
+
+ /* Core Local Interruptor (timer and IPI) */
+ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
+ smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
+}
static void spike_v1_10_0_board_init(MachineState *machine)
{
@@ -172,6 +255,12 @@ static void spike_v1_10_0_board_init(MachineState *machine)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ if (!qtest_enabled()) {
+ info_report("The Spike v1.10.0 machine has been depreceated. "
+ "Please use the deneric spike machine and specify the ISA "
+ "versions using -cpu.");
+ }
+
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
@@ -254,6 +343,12 @@ static void spike_v1_09_1_board_init(MachineState *machine)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ if (!qtest_enabled()) {
+ info_report("The Spike v1.09.1 machine has been depreceated. "
+ "Please use the deneric spike machine and specify the ISA "
+ "versions using -cpu.");
+ }
+
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
@@ -359,8 +454,17 @@ static void spike_v1_10_0_machine_init(MachineClass *mc)
mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
mc->init = spike_v1_10_0_board_init;
mc->max_cpus = 1;
+}
+
+static void spike_machine_init(MachineClass *mc)
+{
+ mc->desc = "RISC-V Spike Board";
+ mc->init = spike_board_init;
+ mc->max_cpus = 1;
mc->is_default = 1;
+ mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
+DEFINE_MACHINE("spike", spike_machine_init)
--
2.21.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
@ 2019-04-04 12:35 ` Ian Campbell
0 siblings, 0 replies; 12+ messages in thread
From: Ian Campbell @ 2019-04-04 12:35 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, palmer
On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> + for (i = 0; i < strlen(riscv_cpu); i++) {
> + if (i == 0 && riscv_cpu[i] == 'r' &&
> + riscv_cpu[i + 1] == 'v') {
Dpes something somewhere else enforce a minimum length or can
`riscv_cpu[i + 1]` be past the end of the string?
Similarly some more times below and also for the `i += 2` bits.
> + /* Starts with "rv" */
> + i += 2;
> + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> + i += 2;
> + valid = true;
> + rvxlen = RV32;
> + }
> + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> + i += 2;
> + valid = true;
> + rvxlen = RV64;
> + }
> + }
Ian.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
@ 2019-04-04 12:35 ` Ian Campbell
0 siblings, 0 replies; 12+ messages in thread
From: Ian Campbell @ 2019-04-04 12:35 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, palmer
On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> + for (i = 0; i < strlen(riscv_cpu); i++) {
> + if (i == 0 && riscv_cpu[i] == 'r' &&
> + riscv_cpu[i + 1] == 'v') {
Dpes something somewhere else enforce a minimum length or can
`riscv_cpu[i + 1]` be past the end of the string?
Similarly some more times below and also for the `i += 2` bits.
> + /* Starts with "rv" */
> + i += 2;
> + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> + i += 2;
> + valid = true;
> + rvxlen = RV32;
> + }
> + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> + i += 2;
> + valid = true;
> + rvxlen = RV64;
> + }
> + }
Ian.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
@ 2019-04-09 17:16 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-04-09 17:16 UTC (permalink / raw)
To: Ian Campbell; +Cc: Alistair Francis, qemu-devel, qemu-riscv, alistair23, palmer
On Thu, Apr 4, 2019 at 5:35 AM Ian Campbell <ijc@hellion.org.uk> wrote:
>
> On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> > + for (i = 0; i < strlen(riscv_cpu); i++) {
> > + if (i == 0 && riscv_cpu[i] == 'r' &&
> > + riscv_cpu[i + 1] == 'v') {
>
> Dpes something somewhere else enforce a minimum length or can
> `riscv_cpu[i + 1]` be past the end of the string?
>
> Similarly some more times below and also for the `i += 2` bits.
Good point, a valid string must be at least 5 characters so I have
added a check before we start the parsing.
Alistair
>
> > + /* Starts with "rv" */
> > + i += 2;
> > + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV32;
> > + }
> > + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV64;
> > + }
> > + }
>
> Ian.
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
@ 2019-04-09 17:16 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-04-09 17:16 UTC (permalink / raw)
To: Ian Campbell; +Cc: qemu-riscv, palmer, Alistair Francis, qemu-devel, alistair23
On Thu, Apr 4, 2019 at 5:35 AM Ian Campbell <ijc@hellion.org.uk> wrote:
>
> On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> > + for (i = 0; i < strlen(riscv_cpu); i++) {
> > + if (i == 0 && riscv_cpu[i] == 'r' &&
> > + riscv_cpu[i + 1] == 'v') {
>
> Dpes something somewhere else enforce a minimum length or can
> `riscv_cpu[i + 1]` be past the end of the string?
>
> Similarly some more times below and also for the `i += 2` bits.
Good point, a valid string must be at least 5 characters so I have
added a check before we start the parsing.
Alistair
>
> > + /* Starts with "rv" */
> > + i += 2;
> > + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV32;
> > + }
> > + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV64;
> > + }
> > + }
>
> Ian.
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU
@ 2019-04-09 17:16 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2019-04-09 17:16 UTC (permalink / raw)
To: Ian Campbell; +Cc: Alistair Francis, qemu-devel, qemu-riscv, alistair23, palmer
On Thu, Apr 4, 2019 at 5:35 AM Ian Campbell <ijc@hellion.org.uk> wrote:
>
> On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> > + for (i = 0; i < strlen(riscv_cpu); i++) {
> > + if (i == 0 && riscv_cpu[i] == 'r' &&
> > + riscv_cpu[i + 1] == 'v') {
>
> Dpes something somewhere else enforce a minimum length or can
> `riscv_cpu[i + 1]` be past the end of the string?
>
> Similarly some more times below and also for the `i += 2` bits.
Good point, a valid string must be at least 5 characters so I have
added a check before we start the parsing.
Alistair
>
> > + /* Starts with "rv" */
> > + i += 2;
> > + if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV32;
> > + }
> > + if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> > + i += 2;
> > + valid = true;
> > + rvxlen = RV64;
> > + }
> > + }
>
> Ian.
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-04-09 17:20 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-29 22:39 [Qemu-riscv] [PATCH for 4.1 v2 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 1/6] linux-user/riscv: Add the CPU type as a comment Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
2019-04-04 12:35 ` [Qemu-devel] " Ian Campbell
2019-04-04 12:35 ` [Qemu-riscv] " Ian Campbell
2019-04-09 17:16 ` Alistair Francis
2019-04-09 17:16 ` [Qemu-riscv] " Alistair Francis
2019-04-09 17:16 ` Alistair Francis
2019-03-29 22:39 ` [Qemu-riscv] [PATCH for 4.1 v2 3/6] target/riscv: Create settable CPU properties Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 4/6] riscv: virt: Allow specifying a CPU via commandline Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 5/6] target/riscv: Remove the generic no MMU CPUs Alistair Francis
2019-03-29 22:40 ` [Qemu-riscv] [PATCH for 4.1 v2 6/6] riscv: Add a generic spike machine Alistair Francis
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