From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 900FAC433F5 for ; Mon, 7 Feb 2022 14:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=/l0lnlWpTedaIs5I5ba41sQgggiuWzjj6CPur4AZ/M0=; b=dWzgbH2XnzsYDj T+dDq1Qb2Pv84sucDIdhOVfmzpQEi3qt0MyPCVZOLaZkkG7lKXanuZzIuj1XUrE6qVQcUfdx1sveG nEGM6pFIY3wJrBX6Xcd1I7E9r0U26ADoDKEm0RIuddqBLP9JtPwnuydpEyIlPwtT8+igzW7KL17GR laRjrpjRAxZSEV3s2JdcmsVabIZUj+TVdKsms76m+clJXvbwz+/sMOTGztplvIzRuEPtBrbi7SegT AJrUvagmGwGx6voB3ymBZPz15DSXAxw77HFlFaUfrFRK/CLgNnPCFfmh8QgxYaVFwhcLHFRIonmc0 UUpmU1zXceNEyAMExgXg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nH5Qu-00AZBf-2u; Mon, 07 Feb 2022 14:56:02 +0000 Received: from guitar.tcltek.co.il ([84.110.109.230] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nH5N1-00AY7N-Ry for linux-arm-kernel@lists.infradead.org; Mon, 07 Feb 2022 14:52:03 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 109E2440F5F; Mon, 7 Feb 2022 16:51:33 +0200 (IST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1644245493; bh=7aNgLkH2AUxOLsKPef7Ni1LA2rtSGekKuigyuyViuyM=; h=From:To:Cc:Subject:Date:From; b=phl7B+KswJvMTbObMss9Cr38/Rv2yuwI3qlHHebcV/DS1pszFdGbMI7/7nxGZymiC jQx18rL8gZefPL7KiLw+JV/BK4ySQRPqgJVxIxx3BIdl4w4KKs+LdJCNrSJjsmXrvD cW5vKdeVJTKEpbn26VKLRCeKs3OHFAUGbWezCSKFj1NNlcJ1Lnn6lX2nyBxqzfA50A yi52Em5Z3nVshHockJep7Ta7lNt5QF1kw1Oh3Ynlf+2DQi5jbAkKQiqqwTw5C75X8b cbDQxxr5IKuRVMJjHoC0Cgvkd3v0mjLiCCRRB23cf+kzTwFqhq1Wn3LWvunWBQji6H d+NgVT6RIlvRA== From: Baruch Siach To: Andy Gross , Bjorn Andersson Cc: Baruch Siach , Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 0/3] PCI: IPQ6018 platform support Date: Mon, 7 Feb 2022 16:51:23 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220207_065200_311140_BC5A7997 X-CRM114-Status: GOOD ( 13.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v6: * Drop DT patch applied to the qcom tree * Normalize driver changes subject line * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros * Drop a vague comment about ASPM configuration * Add a comment about the source of delay periods Changes in v5: * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) Changes in v4: * Drop applied DT bits * Add max-link-speed that was missing from the applied v2 patch * Rebase the driver on v5.16-rc3 Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (2): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Selvam Sathappan Periakaruppan (1): PCI: qcom: Add IPQ60xx support drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 3 files changed, 160 insertions(+), 8 deletions(-) -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F705C4332F for ; Mon, 7 Feb 2022 15:21:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233133AbiBGPVA (ORCPT ); Mon, 7 Feb 2022 10:21:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442929AbiBGPKN (ORCPT ); Mon, 7 Feb 2022 10:10:13 -0500 Received: from mx.tkos.co.il (guitar.tcltek.co.il [84.110.109.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5DEFC0401C4; Mon, 7 Feb 2022 07:08:44 -0800 (PST) Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 109E2440F5F; Mon, 7 Feb 2022 16:51:33 +0200 (IST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1644245493; bh=7aNgLkH2AUxOLsKPef7Ni1LA2rtSGekKuigyuyViuyM=; h=From:To:Cc:Subject:Date:From; b=phl7B+KswJvMTbObMss9Cr38/Rv2yuwI3qlHHebcV/DS1pszFdGbMI7/7nxGZymiC jQx18rL8gZefPL7KiLw+JV/BK4ySQRPqgJVxIxx3BIdl4w4KKs+LdJCNrSJjsmXrvD cW5vKdeVJTKEpbn26VKLRCeKs3OHFAUGbWezCSKFj1NNlcJ1Lnn6lX2nyBxqzfA50A yi52Em5Z3nVshHockJep7Ta7lNt5QF1kw1Oh3Ynlf+2DQi5jbAkKQiqqwTw5C75X8b cbDQxxr5IKuRVMJjHoC0Cgvkd3v0mjLiCCRRB23cf+kzTwFqhq1Wn3LWvunWBQji6H d+NgVT6RIlvRA== From: Baruch Siach To: Andy Gross , Bjorn Andersson Cc: Baruch Siach , Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 0/3] PCI: IPQ6018 platform support Date: Mon, 7 Feb 2022 16:51:23 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v6: * Drop DT patch applied to the qcom tree * Normalize driver changes subject line * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros * Drop a vague comment about ASPM configuration * Add a comment about the source of delay periods Changes in v5: * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) Changes in v4: * Drop applied DT bits * Add max-link-speed that was missing from the applied v2 patch * Rebase the driver on v5.16-rc3 Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (2): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Selvam Sathappan Periakaruppan (1): PCI: qcom: Add IPQ60xx support drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 155 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 3 files changed, 160 insertions(+), 8 deletions(-) -- 2.34.1