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spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed10:d0b:c833:41f6:da0e]) by baptiste.telenet-ops.be with bizsmtp id lslE2800229fmst01slEPe; Fri, 18 Nov 2022 17:45:14 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1ow4UK-000pAE-OJ; Fri, 18 Nov 2022 17:45:12 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1ow4UK-00Frgr-0M; Fri, 18 Nov 2022 17:45:12 +0100 From: Geert Uytterhoeven List-Id: To: arm-soc , soc Cc: Magnus Damm , linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [GIT PULL 6/7] Renesas RISC-V DT updates for v6.2 Date: Fri, 18 Nov 2022 17:45:03 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The following changes since commit b9a0be2054964026aa58966ce9724b672f210835: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts (2022-10-28 14:23:00 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-riscv-dt-for-v6.2-tag1 for you to fetch changes up to 40005cb6093e92d24a1bdbc444311c25e4b28878: riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C (2022-11-17 20:27:02 +0100) ---------------------------------------------------------------- Renesas RISC-V DT updates for v6.2 - Add initial support for the Renesas RZ/Five SoC and the Renesas RZ/Five SMARC EVK development board. ---------------------------------------------------------------- Lad Prabhakar (5): riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK MAINTAINERS: Add entry for Renesas RISC-V riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C MAINTAINERS | 3 +- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 59 ++++++++++++++++++++ arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 47 ++++++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 64 ++++++++++++++++++++++ 7 files changed, 202 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D74BDC4332F for ; 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Fri, 18 Nov 2022 16:46:32 +0000 Received: from baptiste.telenet-ops.be ([2a02:1800:120:4::f00:13]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ow4US-005SHQ-GR for linux-arm-kernel@lists.infradead.org; Fri, 18 Nov 2022 16:45:24 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed10:d0b:c833:41f6:da0e]) by baptiste.telenet-ops.be with bizsmtp id lslE2800229fmst01slEPe; Fri, 18 Nov 2022 17:45:14 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1ow4UK-000pAE-OJ; Fri, 18 Nov 2022 17:45:12 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1ow4UK-00Frgr-0M; Fri, 18 Nov 2022 17:45:12 +0100 From: Geert Uytterhoeven To: arm-soc , soc Cc: Magnus Damm , linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [GIT PULL 6/7] Renesas RISC-V DT updates for v6.2 Date: Fri, 18 Nov 2022 17:45:03 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221118_084520_787075_412B6EB4 X-CRM114-Status: UNSURE ( 9.47 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The following changes since commit b9a0be2054964026aa58966ce9724b672f210835: arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts (2022-10-28 14:23:00 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-riscv-dt-for-v6.2-tag1 for you to fetch changes up to 40005cb6093e92d24a1bdbc444311c25e4b28878: riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C (2022-11-17 20:27:02 +0100) ---------------------------------------------------------------- Renesas RISC-V DT updates for v6.2 - Add initial support for the Renesas RZ/Five SoC and the Renesas RZ/Five SMARC EVK development board. ---------------------------------------------------------------- Lad Prabhakar (5): riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK MAINTAINERS: Add entry for Renesas RISC-V riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C MAINTAINERS | 3 +- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 59 ++++++++++++++++++++ arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 47 ++++++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 64 ++++++++++++++++++++++ 7 files changed, 202 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel