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[90.112.199.53]) by smtp.gmail.com with ESMTPSA id d3-20020adfe2c3000000b002bc7fcf08ddsm3971131wrj.103.2023.01.27.05.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 05:59:43 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: da0b65de-9e4a-11ed-a5d9-ddcf98b90cbd DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=jAx0Mn8J44WfqcJprMgRa+KRzCfpCYZQMBUBNPmWHMc=; b=Dh8kanroU5lGejeoxm13ZdObW+mHxL4ASiLXDKXz83rGCndbXmma3cMH6iP/BCNp4U 7moNydA++TOZ2SeXtZasQbz7SnOGOKupJMT4kAl1V8u1U2xM6AElMdU/EV+l1AJlM4m0 X3obuKErQPJV8Dy1joozmRIJp8niaIJrCrTdXvM3CrlU21w88R5SRxDUTqYBKtNfgjKk Ss0032Vr/l7fc0fslRi3HL0GBfaNnrBbNTwQLSs5PP/ZmgJw07uGOas/7KCdqO2dqrVI 8tL7gUHaKcfkJs/E20sb5A1mlgqVvDnCPcKZfhiAwJzFCYcc66diRmICBCCmd4UBbhEG GEnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jAx0Mn8J44WfqcJprMgRa+KRzCfpCYZQMBUBNPmWHMc=; b=CZkPYm8Fq1NLL9dkpFwsHMWueI19LQ37PA0qajURHB6r/DJfX5Bw11Csub0iW89vIR Ari7iHEnO1/hzlByjU9j9WD7aIU1G/6SvClkqgpuevJY7YQxoo6/e1U81vhKrISfNs9S A8ISm7+FQ6RgeisOyupz8boxjZEPzz048NZawebk0+ZdzLxUPyTdf3Ocr2dZwfa4VYjk qF/eEYm3ecp5aA/8FpIe98XcaQAwHFqHkLj14E2OcvbUM+WdB4cblarGLZQQ91NfC1hy 8cHEkTxkxPkH4LwsuMKzRFr8/CIgJr+W1U5WMuJw6RV8Y5zf2BMB9kC1ysu4RN/oLZlW tmPg== X-Gm-Message-State: AO0yUKUr31Aw/Wx+YKD1xe3hCBbU85rH81NGZHUOq9eUQ8rWvUdSH3rb xsk+q9WQPDQ4BQA1JHeUHDWflIcM2PE= X-Google-Smtp-Source: AK7set9PC/KvhFFh9eyiGgoGgyU6s5oxi2Ehj2TQe37co4M0b1Rza/+MtECDMsjNvKBCD+Xhs2307A== X-Received: by 2002:a5d:664f:0:b0:2bf:be0f:b016 with SMTP id f15-20020a5d664f000000b002bfbe0fb016mr8450627wrw.23.1674827983434; Fri, 27 Jan 2023 05:59:43 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Jan Beulich , Julien Grall , Andrew Cooper , Stefano Stabellini , Gianluca Guida , Oleksii Kurochko , Bob Eshleman , Alistair Francis , Connor Davis , Doug Goldstein Subject: [PATCH v2 00/14] RISCV basic exception handling implementation Date: Fri, 27 Jan 2023 15:59:05 +0200 Message-Id: X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The patch series is based on another one [Basic early_printk and smoke test implementation] which hasn't been commited yet. The patch series provides a basic implementation of exception handling. It can do only basic things such as decode a cause of an exception, save/restore registers and execute "wfi" instruction if an exception can not be handled. To verify that exception handling works well it was implemented macros from such as BUG/WARN/run_in_exception/assert_failed. The implementation of macros is used "ebreak" instruction and set up bug frame tables for each type of macros. Also it was implemented register save/restore to return and continue work after WARN/run_in_exception. Not all functionality of the macros was implemented as some of them require hard-panic the system which is not available now. Instead of hard-panic 'wfi' instruction is used but it should be definitely changed in the neareset future. It wasn't implemented show_execution_state() and stack trace discovering as it's not necessary now. --- Changes in V2: - take the latest riscv_encoding.h from OpenSBI, update it with Xen related changes, and update the commit message with "Origin:" tag and the commit message itself. - add "Origin:" tag to the commit messag of the patch [xen/riscv: add header]. - Remove the patch [xen/riscv: add early_printk_hnum() function] as the functionality provided by the patch isn't used now. - Refactor prcoess.h: move structure offset defines to asm-offsets.c, change register_t to unsigned long. - Refactor entry.S to use offsets defined in asm-offsets.C - Rename {__,}handle_exception to handle_trap() and do_trap() to be more consistent with RISC-V spec. - Merge the pathc which introduces do_unexpected_trap() with the patch [xen/riscv: introduce exception handlers implementation]. - Rename setup_trap_handler() to trap_init() and update correspondingly the patches in the patch series. - Refactor bug.h, remove bug_instr_t type from it. - Refactor decode_trap_cause() function to be more optimization-friendly. - Add two new empty headers: and as they are needed to include which provides ARRAY_SIZE and other macros. - Code style fixes. --- Oleksii Kurochko (14): xen/riscv: add _zicsr to CFLAGS xen/riscv: add header xen/riscv: add header xen/riscv: introduce empty xen/riscv: introduce empty xen/riscv: introduce exception context xen/riscv: introduce exception handlers implementation xen/riscv: introduce decode_cause() stuff xen/riscv: mask all interrupts xen/riscv: introduce trap_init() xen/riscv: introduce an implementation of macros from xen/riscv: test basic handling stuff automation: add smoke test to verify macros from bug.h automation/scripts/qemu-smoke-riscv64.sh | 2 +- xen/arch/riscv/Makefile | 2 + xen/arch/riscv/arch.mk | 2 +- xen/arch/riscv/entry.S | 94 ++ xen/arch/riscv/include/asm/asm.h | 54 ++ xen/arch/riscv/include/asm/bug.h | 118 +++ xen/arch/riscv/include/asm/cache.h | 6 + xen/arch/riscv/include/asm/csr.h | 84 ++ xen/arch/riscv/include/asm/processor.h | 82 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 927 ++++++++++++++++++++ xen/arch/riscv/include/asm/string.h | 6 + xen/arch/riscv/include/asm/traps.h | 14 + xen/arch/riscv/riscv64/asm-offsets.c | 53 ++ xen/arch/riscv/riscv64/head.S | 5 + xen/arch/riscv/setup.c | 21 + xen/arch/riscv/traps.c | 231 +++++ xen/arch/riscv/xen.lds.S | 10 + 17 files changed, 1709 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/entry.S create mode 100644 xen/arch/riscv/include/asm/asm.h create mode 100644 xen/arch/riscv/include/asm/bug.h create mode 100644 xen/arch/riscv/include/asm/cache.h create mode 100644 xen/arch/riscv/include/asm/csr.h create mode 100644 xen/arch/riscv/include/asm/processor.h create mode 100644 xen/arch/riscv/include/asm/riscv_encoding.h create mode 100644 xen/arch/riscv/include/asm/string.h create mode 100644 xen/arch/riscv/include/asm/traps.h create mode 100644 xen/arch/riscv/traps.c -- 2.39.0