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From: James Hogan <james.hogan@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: "James Hogan" <james.hogan@imgtec.com>,
	"Matt Redfearn" <matt.redfearn@imgtec.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>,
	"Leonid Yegoshin" <leonid.yegoshin@imgtec.com>,
	linux-mips@linux-mips.org, kvm@vger.kernel.org
Subject: [PATCH 0/9] MIPS: General EVA fixes & cleanups
Date: Thu, 1 Sep 2016 17:30:06 +0100	[thread overview]
Message-ID: <cover.d93e43428f3c573bdd18d7c874830705b39c3a8a.1472747205.git-series.james.hogan@imgtec.com> (raw)

These patches fix some general MIPS Enhanced Virtual Addressing (EVA)
issues, with the aim of allowing KVM to be fixed to work on EVA host
kernels.

Patches 1-3 improve the CP0_EBase handling, particularly in relation to
the Write Gate (WG) bit which allows the upper bits (63:30 on MIPS64,
31:30 on MIPS32) to be modified. This allows CP0_EBase to be set
correctly with EVA, even when the boot time allocated exception vector
is not in KSeg0. They will also help with Matt's upcoming rproc patches.

Patch 4 then drops the EVA specific L2 cache flushing from
flush_icache_range(), which appeared to work around the partial
CP0_EBase assignment fixed by patch 3.

Patches 5-9 fix the semantics of flush_icache_range(), which only works
on user pointers with EVA. We add a new __flush_icache_user_range() API
in patch 5, fix users of flush_icache_range() with user pointers in
patches 6-8, and finally separate the implementations so that
flush_icache_range() works with kernel addresses in patch 9.

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org

James Hogan (8):
  MIPS: traps: 64bit kernels should read CP0_EBase 64bit
  MIPS: traps: Convert ebase to KSeg0
  MIPS: c-r4k: Drop bc_wback_inv() from icache flush
  MIPS: c-r4k: Split user/kernel flush_icache_range()
  MIPS: cacheflush: Use __flush_icache_user_range()
  MIPS: uprobes: Flush icache via kernel address
  MIPS: KVM: Use __local_flush_icache_user_range()
  MIPS: c-r4k: Fix flush_icache_range() for EVA

Matt Redfearn (1):
  MIPS: traps: Ensure full EBase is written

 arch/mips/include/asm/cacheflush.h |  5 +++-
 arch/mips/kernel/traps.c           | 49 +++++++++++++++++++++++++++--
 arch/mips/kernel/uprobes.c         | 13 ++------
 arch/mips/kvm/dyntrans.c           |  4 +-
 arch/mips/mm/c-octeon.c            |  2 +-
 arch/mips/mm/c-r3k.c               |  2 +-
 arch/mips/mm/c-r4k.c               | 52 ++++++++++++++++++++-----------
 arch/mips/mm/c-tx39.c              |  3 ++-
 arch/mips/mm/cache.c               |  6 +++-
 9 files changed, 104 insertions(+), 32 deletions(-)

-- 
git-series 0.8.10

             reply	other threads:[~2016-09-01 16:30 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-01 16:30 James Hogan [this message]
2016-09-01 16:30 ` [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase 64bit James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-21 13:08   ` Ralf Baechle
2016-09-21 15:01     ` Matt Redfearn
2016-09-21 15:01       ` Matt Redfearn
2016-10-02 10:30       ` Maciej W. Rozycki
2016-10-05 15:56         ` James Hogan
2016-10-05 15:56           ` James Hogan
2016-10-06 16:18           ` Maciej W. Rozycki
2016-10-06 18:05             ` James Hogan
2016-10-06 18:05               ` James Hogan
2016-10-06 19:56               ` Maciej W. Rozycki
2016-10-06 20:19                 ` James Hogan
2016-10-06 20:19                   ` James Hogan
2016-10-06 22:41                   ` Maciej W. Rozycki
2016-10-06 22:50                     ` James Hogan
2016-10-06 22:50                       ` James Hogan
2016-10-06 23:07                       ` Maciej W. Rozycki
2016-10-07 15:35             ` David Daney
2016-10-07 15:41               ` David Daney
2016-10-07 17:39                 ` Maciej W. Rozycki
2016-09-01 16:30 ` [PATCH 2/9] MIPS: traps: Convert ebase to KSeg0 James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-01 16:30 ` [PATCH 3/9] MIPS: traps: Ensure full EBase is written James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-21 13:19   ` Ralf Baechle
2016-09-01 16:30 ` [PATCH 4/9] MIPS: c-r4k: Drop bc_wback_inv() from icache flush James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-01 16:30 ` [PATCH 5/9] MIPS: c-r4k: Split user/kernel flush_icache_range() James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-01 16:30 ` [PATCH 6/9] MIPS: cacheflush: Use __flush_icache_user_range() James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-01 16:30 ` [PATCH 7/9] MIPS: uprobes: Flush icache via kernel address James Hogan
2016-09-01 16:30   ` James Hogan
2016-09-21 13:26   ` Ralf Baechle
2016-09-21 18:15     ` Leonid Yegoshin
2016-09-21 18:15       ` Leonid Yegoshin
2016-09-22 21:15       ` James Hogan
2016-09-22 21:15         ` James Hogan
2016-09-22 21:38         ` Leonid Yegoshin
2016-09-22 21:38           ` Leonid Yegoshin
2016-09-22 21:42           ` Leonid Yegoshin
2016-09-22 21:42             ` Leonid Yegoshin
2016-09-22 22:13           ` James Hogan
2016-09-22 22:27             ` Leonid Yegoshin
2016-09-22 22:27               ` Leonid Yegoshin
2016-09-23  7:10               ` James Hogan
2016-09-01 16:30 ` [PATCH 8/9] MIPS: KVM: Use __local_flush_icache_user_range() James Hogan
2016-09-01 16:30 ` [PATCH 9/9] MIPS: c-r4k: Fix flush_icache_range() for EVA James Hogan
2016-09-01 16:30   ` James Hogan

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