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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1559961859; bh=oKWJ7IKb+QbAvUpADFLHB7hOUGVmIRjnWSUgva6nGvc=; h=Subject:To:References:From:Date:In-Reply-To:From; b=am4cnrVIkLTW3BjoL2rTfOEK+yBpuSa1p396Q/acd5RAwWAOW57vc/ndv9KH39zwv hlJhtxcw733TPFb6sx8APFWX0UtRPuWgiwCpV33PA5fGQZHpictSF270BfkUpWvMCh Y2CdwX8/i5UPWVeVdm+13dwQpr45hCrqIDQdVM0E= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B499660240 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org Subject: Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support To: Marc Zyngier , robh+dt@kernel.org, sboyd@codeaurora.org, linus.walleij@linaro.org, agross@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1559754961-26783-1-git-send-email-sricharan@codeaurora.org> <1559754961-26783-6-git-send-email-sricharan@codeaurora.org> From: Sricharan R Message-ID: Date: Sat, 8 Jun 2019 08:14:11 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Marc, On 6/5/2019 10:56 PM, Marc Zyngier wrote: > On 05/06/2019 18:16, Sricharan R wrote: >> Add initial device tree support for the Qualcomm IPQ6018 SoC and >> CP01 evaluation board. >> >> Signed-off-by: Sricharan R >> Signed-off-by: Abhishek Sahu >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++ >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++ >> 3 files changed, 267 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index 21d548f..ac22dbb 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -2,6 +2,7 @@ >> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb >> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> new file mode 100644 >> index 0000000..ac7cb22 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> @@ -0,0 +1,35 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * IPQ6018 CP01 board device tree source >> + * >> + * Copyright (c) 2019, The Linux Foundation. All rights reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include "ipq6018.dtsi" >> + >> +/ { >> + #address-cells = <0x2>; >> + #size-cells = <0x2>; >> + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; >> + compatible = "qcom,ipq6018-cp01", "qcom,ipq6018"; >> + interrupt-parent = <&intc>; >> +}; >> + >> +&tlmm { >> + uart_pins: uart_pins { >> + mux { >> + pins = "gpio44", "gpio45"; >> + function = "blsp2_uart"; >> + drive-strength = <8>; >> + bias-pull-down; >> + }; >> + }; >> +}; >> + >> +&blsp1_uart3 { >> + pinctrl-0 = <&uart_pins>; >> + pinctrl-names = "default"; >> + status = "ok"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> new file mode 100644 >> index 0000000..79cccdd >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> @@ -0,0 +1,231 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * IPQ6018 SoC device tree source >> + * >> + * Copyright (c) 2019, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include >> +#include >> + >> +/ { >> + model = "Qualcomm Technologies, Inc. IPQ6018"; >> + compatible = "qcom,ipq6018"; >> + >> + chosen { >> + bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; >> + bootargs-append = " swiotlb=1 clk_ignore_unused"; >> + }; >> + >> + reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + tz:tz@48500000 { >> + no-map; >> + reg = <0x0 0x48500000 0x0 0x00200000>; >> + }; >> + }; >> + >> + soc: soc { >> + #address-cells = <0x1>; >> + #size-cells = <0x1>; >> + ranges = <0 0 0 0xffffffff>; >> + dma-ranges; >> + compatible = "simple-bus"; >> + >> + intc: interrupt-controller@b000000 { >> + compatible = "qcom,msm-qgic2"; >> + interrupt-controller; >> + #interrupt-cells = <0x3>; >> + reg = <0xb000000 0x1000>, <0xb002000 0x1000>; > > Where are the rest of the GICv2 MMIO regions, such as GICV and GICH? And > the maintenance interrupt? > GICH - 0xB001000 -- 0xB002000 GICV - 0xB004000 -- 0xB005000 Will add this and the PPI as well. Regards, Sricharan >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = , >> + , >> + , >> + ; > > The fact that you expose the EL2 timer interrupt would tend to confirm > the idea that this system supports virtualization... Hence my questions > above. > > Thanks, > > M. > -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84683C2BCA1 for ; Sat, 8 Jun 2019 02:44:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5CD9F208C0 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org Subject: Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support To: Marc Zyngier , robh+dt@kernel.org, sboyd@codeaurora.org, linus.walleij@linaro.org, agross@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1559754961-26783-1-git-send-email-sricharan@codeaurora.org> <1559754961-26783-6-git-send-email-sricharan@codeaurora.org> From: Sricharan R Message-ID: Date: Sat, 8 Jun 2019 08:14:11 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190607_194422_988738_E69C074C X-CRM114-Status: GOOD ( 19.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 6/5/2019 10:56 PM, Marc Zyngier wrote: > On 05/06/2019 18:16, Sricharan R wrote: >> Add initial device tree support for the Qualcomm IPQ6018 SoC and >> CP01 evaluation board. >> >> Signed-off-by: Sricharan R >> Signed-off-by: Abhishek Sahu >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++ >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++ >> 3 files changed, 267 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index 21d548f..ac22dbb 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -2,6 +2,7 @@ >> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb >> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb >> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> new file mode 100644 >> index 0000000..ac7cb22 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> @@ -0,0 +1,35 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * IPQ6018 CP01 board device tree source >> + * >> + * Copyright (c) 2019, The Linux Foundation. All rights reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include "ipq6018.dtsi" >> + >> +/ { >> + #address-cells = <0x2>; >> + #size-cells = <0x2>; >> + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; >> + compatible = "qcom,ipq6018-cp01", "qcom,ipq6018"; >> + interrupt-parent = <&intc>; >> +}; >> + >> +&tlmm { >> + uart_pins: uart_pins { >> + mux { >> + pins = "gpio44", "gpio45"; >> + function = "blsp2_uart"; >> + drive-strength = <8>; >> + bias-pull-down; >> + }; >> + }; >> +}; >> + >> +&blsp1_uart3 { >> + pinctrl-0 = <&uart_pins>; >> + pinctrl-names = "default"; >> + status = "ok"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> new file mode 100644 >> index 0000000..79cccdd >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi >> @@ -0,0 +1,231 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * IPQ6018 SoC device tree source >> + * >> + * Copyright (c) 2019, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include >> +#include >> + >> +/ { >> + model = "Qualcomm Technologies, Inc. IPQ6018"; >> + compatible = "qcom,ipq6018"; >> + >> + chosen { >> + bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; >> + bootargs-append = " swiotlb=1 clk_ignore_unused"; >> + }; >> + >> + reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + tz:tz@48500000 { >> + no-map; >> + reg = <0x0 0x48500000 0x0 0x00200000>; >> + }; >> + }; >> + >> + soc: soc { >> + #address-cells = <0x1>; >> + #size-cells = <0x1>; >> + ranges = <0 0 0 0xffffffff>; >> + dma-ranges; >> + compatible = "simple-bus"; >> + >> + intc: interrupt-controller@b000000 { >> + compatible = "qcom,msm-qgic2"; >> + interrupt-controller; >> + #interrupt-cells = <0x3>; >> + reg = <0xb000000 0x1000>, <0xb002000 0x1000>; > > Where are the rest of the GICv2 MMIO regions, such as GICV and GICH? And > the maintenance interrupt? > GICH - 0xB001000 -- 0xB002000 GICV - 0xB004000 -- 0xB005000 Will add this and the PPI as well. Regards, Sricharan >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = , >> + , >> + , >> + ; > > The fact that you expose the EL2 timer interrupt would tend to confirm > the idea that this system supports virtualization... Hence my questions > above. > > Thanks, > > M. > -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel