From mboxrd@z Thu Jan  1 00:00:00 1970
From: Akhil Goyal <akhil.goyal@nxp.com>
Subject: Re: [PATCH v2 07/33] common/cpt: add hardware register
 defines
Date: Mon, 17 Sep 2018 16:48:32 +0530
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Cc: Anoob Joseph <anoob.joseph@caviumnetworks.com>,
 Jerin Jacob <jerin.jacob@caviumnetworks.com>,
 Narayana Prasad <narayanaprasad.athreya@caviumnetworks.com>, dev@dpdk.org,
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To: Anoob Joseph <ajoseph@caviumnetworks.com>,
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> +typedef union cpt_res_s {
> +	uint64_t u[2];
> +	struct cpt_res_s_8s {
> +#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
> +		uint64_t reserved_17_63        : 47;
> +		uint64_t doneint               : 1;
> +		/**< [ 16: 16] Done interrupt. This bit is copied from the
> +		 * corresponding instruction's CPT_INST_S[DONEINT].
> +		 **/
> +		uint64_t reserved_8_15         : 8;
> +		uint64_t compcode              : 8;
> +		/**< [  7:  0] Indicates completion/error status of the CPT
> +		 * coprocessor for the associated instruction, as enumerated by
> +		 * CPT_COMP_E. Core software may write the memory location
> +		 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
> +		 * then poll for completion by checking for a nonzero value.
> +
> +		 Once the core observes a nonzero [COMPCODE] value in this case,
> +		 the CPT coprocessor will have also completed L2/DRAM write
> +		 operations.
> +		  */
commenting style shall be uniform in the file.
Half of the comments have * and half don't have. Please be consistent.

-Akhil