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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Wei Liu <wl@xen.org>, Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH v10 2/9] x86emul: rework CMP and TEST emulation
Date: Fri, 29 May 2020 16:07:19 +0100	[thread overview]
Message-ID: <d1d304ee-613e-c013-2000-39c5707c3af0@citrix.com> (raw)
In-Reply-To: <629b042b-1226-6d2d-6509-569bb3c64abe@suse.com>

On 29/05/2020 14:41, Jan Beulich wrote:
> On 29.05.2020 14:24, Andrew Cooper wrote:
>> On 25/05/2020 15:26, Jan Beulich wrote:
>>> Unlike similarly encoded insns these don't write their memory operands,
>> "write to their".
>>
>>> and hence x86_is_mem_write() should return false for them. However,
>>> rather than adding special logic there, rework how their emulation gets
>>> done, by making decoding attributes properly describe the r/o nature of
>>> their memory operands.
>> Describe how?  I see you've change the order of operands encoding, but
>> then override it back?
> There's no overriding back, I don't think: I change the table entries
> for opcodes 0x38 and 0x39, with no other adjustments the the attributes
> later on. For the other opcodes I leave the table entries as they are,
> and override the attributes for the specific sub-cases (identified by
> ModRM.reg).
>
> For opcodes 0x38 and 0x39 the change of the table entries implies
> changing the order of operands as passed to emulate_2op_SrcV(), hence
> the splitting of the cases in the main switch().
> I didn't think this was necessary to spell out in the commit message,
> but of course I can re-use most of the text above and add it into
> there, if you think that would help.

Yes please.  With something suitable, Acked-by: Andrew Cooper
<andrew.cooper3@citrix.com>

~Andrew


  reply	other threads:[~2020-05-29 15:07 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-25 14:23 [PATCH v10 0/9] x86emul: further work Jan Beulich
2020-05-25 14:26 ` [PATCH v10 1/9] x86emul: address x86_insn_is_mem_{access,write}() omissions Jan Beulich
2020-05-29 12:18   ` [PATCH v10 1/9] x86emul: address x86_insn_is_mem_{access, write}() omissions Andrew Cooper
2020-05-29 13:29     ` Jan Beulich
2020-05-29 15:03       ` Andrew Cooper
2020-05-29 15:19         ` Jan Beulich
2020-05-25 14:26 ` [PATCH v10 2/9] x86emul: rework CMP and TEST emulation Jan Beulich
2020-05-29 12:24   ` Andrew Cooper
2020-05-29 13:41     ` Jan Beulich
2020-05-29 15:07       ` Andrew Cooper [this message]
2020-05-25 14:27 ` [PATCH v10 3/9] x86emul: also test decoding and mem access / write logic Jan Beulich
2020-05-29 12:27   ` Andrew Cooper
2020-05-25 14:27 ` [PATCH v10 4/9] x86emul: disable FPU/MMX/SIMD insn emulation when !HVM Jan Beulich
2020-05-29 12:33   ` Andrew Cooper
2020-05-25 14:28 ` [PATCH v10 5/9] x86emul: support MOVDIR{I,64B} insns Jan Beulich
2020-05-29 13:55   ` Andrew Cooper
2020-05-29 14:00     ` Jan Beulich
2020-05-25 14:28 ` [PATCH v10 6/9] x86emul: support ENQCMD insns Jan Beulich
2020-05-25 14:29 ` [PATCH v10 7/9] x86emul: support FNSTENV and FNSAVE Jan Beulich
2020-05-29 14:08   ` Andrew Cooper
2020-05-29 14:12     ` Jan Beulich
2020-05-25 14:29 ` [PATCH v10 8/9] x86emul: support FLDENV and FRSTOR Jan Beulich
2020-05-29 14:09   ` Andrew Cooper
2020-05-25 14:30 ` [PATCH v10 9/9] x86emul: support FXSAVE/FXRSTOR Jan Beulich
2020-05-29 14:25   ` Andrew Cooper

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