From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrloN-0004yY-HK for qemu-devel@nongnu.org; Wed, 26 Jun 2013 05:14:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UrloL-0002Zi-Sw for qemu-devel@nongnu.org; Wed, 26 Jun 2013 05:14:47 -0400 Received: from [222.73.24.84] (port=6647 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrloL-0002Xi-HD for qemu-devel@nongnu.org; Wed, 26 Jun 2013 05:14:45 -0400 From: Hu Tao Date: Wed, 26 Jun 2013 17:13:34 +0800 Message-Id: In-Reply-To: References: Subject: [Qemu-devel] [PATCH v5 11/14] Introduce paravirt interface QEMU_CFG_PCI_WINDOW List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Vasilis Liaskovitis From: Vasilis Liaskovitis Qemu calculates the 32-bit and 64-bit PCI starting offsets based on initial memory and hotplug-able dimms. This info needs to be passed to Seabios for PCI initialization. Signed-off-by: Vasilis Liaskovitis Signed-off-by: Hu Tao --- hw/i386/pc_q35.c | 10 ++++++++++ hw/pci-host/piix.c | 13 +++++++++++++ include/hw/nvram/fw_cfg.h | 1 + 3 files changed, 24 insertions(+) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 2c14977..f956c62 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -42,6 +42,7 @@ #include "hw/ide/ahci.h" #include "hw/usb.h" #include "hw/cpu/icc_bus.h" +#include "hw/nvram/fw_cfg.h" /* ICH9 AHCI has 6 ports */ #define MAX_SATA_PORTS 6 @@ -75,6 +76,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) PCIDevice *ahci; DeviceState *icc_bridge; void *fw_cfg = NULL; + uint64_t *pci_window_fw_cfg; icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE); object_property_add_child(qdev_get_machine(), "icc-bridge", @@ -119,6 +121,14 @@ static void pc_q35_init(QEMUMachineInitArgs *args) /* pci */ qdev_init_nofail(DEVICE(q35_host)); bochs_meminfo_bios_init(fw_cfg); + + pci_window_fw_cfg = g_new0(uint64_t, 2); + pci_window_fw_cfg[0] = cpu_to_le64(MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); + pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL + + q35_host->mch.dev.above_4g_mem_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW, + (uint8_t *)pci_window_fw_cfg, 2 * 8); + host_bus = q35_host->host.pci.bus; /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 71a9b8b..ace8f2b 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -32,6 +32,7 @@ #include "hw/xen/xen.h" #include "hw/pci-host/pam.h" #include "sysemu/sysemu.h" +#include "hw/nvram/fw_cfg.h" /* * I440FX chipset data sheet. @@ -229,6 +230,8 @@ static PCIBus *i440fx_common_init(const char *device_name, PIIX3State *piix3; I440FXPMCState *f; I440FXState *i440fx; + uint64_t *pci_window_fw_cfg; + void *fw_cfg; i440fx = I440FX_DEVICE(object_new(TYPE_I440FX_DEVICE)); s = PCI_HOST_BRIDGE(i440fx); @@ -266,6 +269,16 @@ static PCIBus *i440fx_common_init(const char *device_name, *piix3_devfn = piix3->dev.devfn; *pci_address_space = &i440fx->pci_address_space; + fw_cfg = fw_cfg_find(); + if (fw_cfg) { + pci_window_fw_cfg = g_new0(uint64_t, 2); + pci_window_fw_cfg[0] = cpu_to_le64(f->dev.below_4g_mem_size); + pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL + + f->dev.above_4g_mem_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW, + (uint8_t *)pci_window_fw_cfg, 2 * 8); + } + return s->bus; } diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index f60dd67..41cfa32 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -35,6 +35,7 @@ #define FW_CFG_SETUP_SIZE 0x17 #define FW_CFG_SETUP_DATA 0x18 #define FW_CFG_FILE_DIR 0x19 +#define FW_CFG_PCI_WINDOW 0x1a #define FW_CFG_FILE_FIRST 0x20 #define FW_CFG_FILE_SLOTS 0x10 -- 1.8.3.1