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From: Richard Henderson <richard.henderson@linaro.org>
To: Stephen Long <steplong@quicinc.com>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, apazos@quicinc.com
Subject: Re: [PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT
Date: Fri, 17 Apr 2020 16:58:33 -0700	[thread overview]
Message-ID: <d2c568ef-c87a-3300-17dc-cccf83c8f12f@linaro.org> (raw)
In-Reply-To: <7593864c-828f-5c03-c3d5-8ba8eab8cd6a@linaro.org>

On 4/17/20 2:24 PM, Richard Henderson wrote:
> On 4/17/20 9:22 AM, Stephen Long wrote:
>> +#define DO_RADDHN(N, M, SH) ((N + M + (1 << (SH - 1))) >> SH)
> 
> This formula will overflow.  See DO_RSHR -- with some added parenthesis, we
> could actually reuse that macro.

My bad.  While it does overflow, all of these operations are truncating not
saturating, and moreover truncate to halfesize bits.  Therefore overflow
doesn't matter.


r~


  reply	other threads:[~2020-04-17 23:59 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-17 16:22 [PATCH 0/4] target/arm: Implement last SVE2 narrowing section Stephen Long
2020-04-17 16:22 ` [PATCH 1/4] target/arm: Implement SVE2 ADDHNB, ADDHNT Stephen Long
2020-04-17 16:22 ` [PATCH 2/4] target/arm: Implement SVE2 RADDHNB, RADDHNT Stephen Long
2020-04-17 21:24   ` Richard Henderson
2020-04-17 23:58     ` Richard Henderson [this message]
2020-04-17 16:22 ` [PATCH 3/4] target/arm: Implement SVE2 SUBHNB, SUBHNT Stephen Long
2020-04-17 16:22 ` [PATCH 4/4] target/arm: Implement SVE2 RSUBHNB, RSUBHNT Stephen Long
2020-04-19 18:28 ` [PATCH 0/4] target/arm: Implement last SVE2 narrowing section Richard Henderson

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