* [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-02-26 10:59 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-02-26 10:59 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream, Mason Zhang
this patch add spi master dts node for mt6779 SOC.
Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309d32de..ca72eb09cff9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -219,6 +219,102 @@
status = "disabled";
};
+ spi0: spi0@1100a000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi1: spi1@11010000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi2: spi2@11012000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi3: spi3@11013000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi4: spi4@11018000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi5: spi5@11019000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi6: spi6@1101d000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI6>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi7: spi7@1101e000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI7>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-02-26 10:59 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-02-26 10:59 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: devicetree, Mason Zhang, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, linux-arm-kernel
this patch add spi master dts node for mt6779 SOC.
Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309d32de..ca72eb09cff9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -219,6 +219,102 @@
status = "disabled";
};
+ spi0: spi0@1100a000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi1: spi1@11010000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi2: spi2@11012000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi3: spi3@11013000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi4: spi4@11018000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi5: spi5@11019000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi6: spi6@1101d000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI6>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi7: spi7@1101e000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI7>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-02-26 10:59 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-02-26 10:59 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: devicetree, Mason Zhang, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, linux-arm-kernel
this patch add spi master dts node for mt6779 SOC.
Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 370f309d32de..ca72eb09cff9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -219,6 +219,102 @@
status = "disabled";
};
+ spi0: spi0@1100a000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi1: spi1@11010000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi2: spi2@11012000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi3: spi3@11013000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi4: spi4@11018000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi5: spi5@11019000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi6: spi6@1101d000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI6>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
+ spi7: spi7@1101e000 {
+ compatible = "mediatek,mt6779-spi",
+ "mediatek,mt6765-spi";
+ mediatek,pad-select = <0>;
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_SPI7>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ };
+
audio: clock-controller@11210000 {
compatible = "mediatek,mt6779-audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
2021-02-26 10:59 ` Mason Zhang
(?)
@ 2021-03-01 2:01 ` Mason Zhang
-1 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-03-01 2:01 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: Matthias Brugger, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-03-01 2:01 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-03-01 2:01 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: devicetree, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, Matthias Brugger, linux-arm-kernel
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-03-01 2:01 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-03-01 2:01 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: devicetree, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, Matthias Brugger, linux-arm-kernel
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
2021-02-26 10:59 ` Mason Zhang
(?)
@ 2021-03-22 11:28 ` Mason Zhang
-1 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-03-22 11:28 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: devicetree, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi Mark Brown and Rob Herring:
Gentle ping on this patch.
Thanks
Mason
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-03-22 11:28 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-03-22 11:28 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: devicetree, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi Mark Brown and Rob Herring:
Gentle ping on this patch.
Thanks
Mason
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-03-22 11:28 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-03-22 11:28 UTC (permalink / raw)
To: Mark Brown, Rob Herring
Cc: devicetree, wsd_upstream, hanks.chen, linux-kernel,
linux-mediatek, Matthias Brugger, linux-arm-kernel
Hi Mark Brown and Rob Herring:
Gentle ping on this patch.
Thanks
Mason
On Fri, 2021-02-26 at 18:59 +0800, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
2021-02-26 10:59 ` Mason Zhang
(?)
@ 2021-03-29 15:50 ` Matthias Brugger
-1 siblings, 0 replies; 21+ messages in thread
From: Matthias Brugger @ 2021-03-29 15:50 UTC (permalink / raw)
To: Mason Zhang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
Please also update binding description accordingling and add as another patch. I
wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
the same as this patch.
Regards,
Matthias
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-03-29 15:50 ` Matthias Brugger
0 siblings, 0 replies; 21+ messages in thread
From: Matthias Brugger @ 2021-03-29 15:50 UTC (permalink / raw)
To: Mason Zhang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
Please also update binding description accordingling and add as another patch. I
wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
the same as this patch.
Regards,
Matthias
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
>
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Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-03-29 15:50 ` Matthias Brugger
0 siblings, 0 replies; 21+ messages in thread
From: Matthias Brugger @ 2021-03-29 15:50 UTC (permalink / raw)
To: Mason Zhang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
Please also update binding description accordingling and add as another patch. I
wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
the same as this patch.
Regards,
Matthias
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
2021-03-29 15:50 ` Matthias Brugger
(?)
@ 2021-04-07 8:49 ` Mason Zhang
-1 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-04-07 8:49 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Mon, 2021-03-29 at 17:50 +0200, Matthias Brugger wrote:
> Please also update binding description accordingling and add as another patch. I
> wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
> the same as this patch.
Dear Matthias:
patch 2/2 in this link and this patch has been merged:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210226110109.30500-1-Mason.Zhang@mediatek.com/
so, Please gentle ping on patch 1/2. Thank you~
Thanks
Mason
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-04-07 8:49 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-04-07 8:49 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Mon, 2021-03-29 at 17:50 +0200, Matthias Brugger wrote:
> Please also update binding description accordingling and add as another patch. I
> wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
> the same as this patch.
Dear Matthias:
patch 2/2 in this link and this patch has been merged:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210226110109.30500-1-Mason.Zhang@mediatek.com/
so, Please gentle ping on patch 1/2. Thank you~
Thanks
Mason
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-04-07 8:49 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-04-07 8:49 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Mon, 2021-03-29 at 17:50 +0200, Matthias Brugger wrote:
> Please also update binding description accordingling and add as another patch. I
> wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
> the same as this patch.
Dear Matthias:
patch 2/2 in this link and this patch has been merged:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210226110109.30500-1-Mason.Zhang@mediatek.com/
so, Please gentle ping on patch 1/2. Thank you~
Thanks
Mason
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
2021-02-26 10:59 ` Mason Zhang
(?)
@ 2021-04-07 11:17 ` Matthias Brugger
-1 siblings, 0 replies; 21+ messages in thread
From: Matthias Brugger @ 2021-04-07 11:17 UTC (permalink / raw)
To: Mason Zhang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream, Leilk Liu
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
From the binding description:
- #address-cells: should be 1.
- #size-cells: should be 0.
We are missing both here. Please fix that.
Apart the binding description is naming PLL, clock mux and clock gate IDs which
do not correspond to the ones used here. It seems that this binding was tailored
for a specific SoC family but never made generic. If you want, please do so and
convert it to yaml.
Regards,
Matthias
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-04-07 11:17 ` Matthias Brugger
0 siblings, 0 replies; 21+ messages in thread
From: Matthias Brugger @ 2021-04-07 11:17 UTC (permalink / raw)
To: Mason Zhang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream, Leilk Liu
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
From the binding description:
- #address-cells: should be 1.
- #size-cells: should be 0.
We are missing both here. Please fix that.
Apart the binding description is naming PLL, clock mux and clock gate IDs which
do not correspond to the ones used here. It seems that this binding was tailored
for a specific SoC family but never made generic. If you want, please do so and
convert it to yaml.
Regards,
Matthias
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-04-07 11:17 ` Matthias Brugger
0 siblings, 0 replies; 21+ messages in thread
From: Matthias Brugger @ 2021-04-07 11:17 UTC (permalink / raw)
To: Mason Zhang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
hanks.chen, wsd_upstream, Leilk Liu
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
From the binding description:
- #address-cells: should be 1.
- #size-cells: should be 0.
We are missing both here. Please fix that.
Apart the binding description is naming PLL, clock mux and clock gate IDs which
do not correspond to the ones used here. It seems that this binding was tailored
for a specific SoC family but never made generic. If you want, please do so and
convert it to yaml.
Regards,
Matthias
> + };
> +
> + spi1: spi1@11010000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11010000 0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
> + <&topckgen CLK_TOP_SPI>,
> + <&infracfg_ao CLK_INFRA_SPI7>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> audio: clock-controller@11210000 {
> compatible = "mediatek,mt6779-audio", "syscon";
> reg = <0 0x11210000 0 0x1000>;
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
2021-04-07 11:17 ` Matthias Brugger
(?)
@ 2021-04-09 2:27 ` Mason Zhang
-1 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-04-09 2:27 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Wed, 2021-04-07 at 13:17 +0200, Matthias Brugger wrote:
>
> From the binding description:
> - #address-cells: should be 1.
>
> - #size-cells: should be 0.
>
> We are missing both here. Please fix that.
>
> Apart the binding description is naming PLL, clock mux and clock gate IDs which
> do not correspond to the ones used here. It seems that this binding was tailored
> for a specific SoC family but never made generic. If you want, please do so and
> convert it to yaml.
Dear Matthias:
I have update patch v2:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210409015651.11474-1-Mason.Zhang@mediatek.com/
Please gentle ping on this patch. Thanks~
Thanks
Mason
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-04-09 2:27 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-04-09 2:27 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Wed, 2021-04-07 at 13:17 +0200, Matthias Brugger wrote:
>
> From the binding description:
> - #address-cells: should be 1.
>
> - #size-cells: should be 0.
>
> We are missing both here. Please fix that.
>
> Apart the binding description is naming PLL, clock mux and clock gate IDs which
> do not correspond to the ones used here. It seems that this binding was tailored
> for a specific SoC family but never made generic. If you want, please do so and
> convert it to yaml.
Dear Matthias:
I have update patch v2:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210409015651.11474-1-Mason.Zhang@mediatek.com/
Please gentle ping on this patch. Thanks~
Thanks
Mason
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
@ 2021-04-09 2:27 ` Mason Zhang
0 siblings, 0 replies; 21+ messages in thread
From: Mason Zhang @ 2021-04-09 2:27 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, hanks.chen, wsd_upstream
On Wed, 2021-04-07 at 13:17 +0200, Matthias Brugger wrote:
>
> From the binding description:
> - #address-cells: should be 1.
>
> - #size-cells: should be 0.
>
> We are missing both here. Please fix that.
>
> Apart the binding description is naming PLL, clock mux and clock gate IDs which
> do not correspond to the ones used here. It seems that this binding was tailored
> for a specific SoC family but never made generic. If you want, please do so and
> convert it to yaml.
Dear Matthias:
I have update patch v2:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210409015651.11474-1-Mason.Zhang@mediatek.com/
Please gentle ping on this patch. Thanks~
Thanks
Mason
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-04-09 2:47 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-26 10:59 [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node Mason Zhang
2021-02-26 10:59 ` Mason Zhang
2021-02-26 10:59 ` Mason Zhang
2021-03-01 2:01 ` Mason Zhang
2021-03-01 2:01 ` Mason Zhang
2021-03-01 2:01 ` Mason Zhang
2021-03-22 11:28 ` Mason Zhang
2021-03-22 11:28 ` Mason Zhang
2021-03-22 11:28 ` Mason Zhang
2021-03-29 15:50 ` Matthias Brugger
2021-03-29 15:50 ` Matthias Brugger
2021-03-29 15:50 ` Matthias Brugger
2021-04-07 8:49 ` Mason Zhang
2021-04-07 8:49 ` Mason Zhang
2021-04-07 8:49 ` Mason Zhang
2021-04-07 11:17 ` Matthias Brugger
2021-04-07 11:17 ` Matthias Brugger
2021-04-07 11:17 ` Matthias Brugger
2021-04-09 2:27 ` Mason Zhang
2021-04-09 2:27 ` Mason Zhang
2021-04-09 2:27 ` Mason Zhang
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