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Subject: Re: [PATCH 3/5] ns8250: Add base support for MMIO UARTs
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Sven Anderson <sven@anderson.de>
Cc: Matthias Lange <matthias.lange@kernkonzept.com>, The development of
 GNU GRUB <grub-devel@gnu.org>
Date: Wed, 31 Aug 2022 15:56:05 +1000
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On Mon, 2022-05-23 at 19:11 +0200, Sven Anderson wrote:
>=20
> I had a couple of sleepless nights trying to find out why this didn't
> work for my MMIO UART (Intel Cannon Lake PCH=C2=A0Intel=C2=A0C246), so I
> thought I would share my findings with others in a similar=C2=A0situation=
.
> (See below.)
> =C2=A0
 .../...
>=20
> This code assumes that the registers are only 8 bit wide. Apparently
> for my chipset they are 32 bits wide, so it only (finally) worked
> when I rewrote this code to address=C2=A0and write full grub_uint32_t
> values, like this:=C2=A0
>=20
> ------
> =C2=A0 volatile grub_uint32_t* p =3D (void*)(port->mmio_base);
> =C2=A0 *(p + reg) =3D (grub_uint32_t)(value);
> ------

Sorry, I dopped the ball on this for a while. Getting back to it and
will re-submit the patches.

Can you send me a dump of your SPCR table ? I'd like to see if it
properly says "32-bit" there to auto-detect this.

Cheers,
Ben.