From: Jan Beulich <jbeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: [PATCH v6 05/10] x86/HVM: scale MPERF values reported to guests (on AMD)
Date: Tue, 14 Apr 2020 13:46:46 +0200 [thread overview]
Message-ID: <d37edec9-5a87-e095-18d8-6b4d3fa8dced@suse.com> (raw)
In-Reply-To: <d9a53b50-472d-477a-6275-ada0cb6e87e6@suse.com>
AMD's PM specifies that MPERF (and its r/o counterpart) reads are
affected by the TSC ratio. Hence when processing such reads in software
we too should scale the values. While we don't currently (yet) expose
the underlying feature flags, besides us allowing the MSRs to be read
nevertheless, RDPRU is going to expose the values even to user space.
Furthermore, due to the not exposed feature flags, this change has the
effect of making properly inaccessible (for reads) the two MSRs.
Note that writes to MPERF (and APERF) continue to be unsupported.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v3: New.
---
I did consider whether to put the code in guest_rdmsr() instead, but
decided that it's better to have it next to TSC handling.
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3454,6 +3454,22 @@ int hvm_msr_read_intercept(unsigned int
*msr_content = v->arch.hvm.msr_tsc_adjust;
break;
+ case MSR_MPERF_RD_ONLY:
+ if ( !d->arch.cpuid->extd.efro )
+ {
+ goto gp_fault;
+
+ case MSR_IA32_MPERF:
+ if ( !(d->arch.cpuid->basic.raw[6].c &
+ CPUID6_ECX_APERFMPERF_CAPABILITY) )
+ goto gp_fault;
+ }
+ if ( rdmsr_safe(msr, *msr_content) )
+ goto gp_fault;
+ if ( d->arch.cpuid->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
+ *msr_content = hvm_get_guest_tsc_fixed(v, *msr_content);
+ break;
+
case MSR_APIC_BASE:
*msr_content = vcpu_vlapic(v)->hw.apic_base_msr;
break;
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -397,6 +397,9 @@
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
+#define MSR_MPERF_RD_ONLY 0xc00000e7
+#define MSR_APERF_RD_ONLY 0xc00000e8
+
#define MSR_IA32_THERM_CONTROL 0x0000019a
#define MSR_IA32_THERM_INTERRUPT 0x0000019b
#define MSR_IA32_THERM_STATUS 0x0000019c
next prev parent reply other threads:[~2020-04-14 11:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 11:39 [PATCH v6 00/10] x86emul: further work Jan Beulich
2020-04-14 11:43 ` [PATCH v6 01/10] x86: determine HAVE_AS_* just once Jan Beulich
2020-04-14 11:44 ` [PATCH v6 02/10] x86: move back clang no integrated assembler tests Jan Beulich
2020-04-14 11:44 ` [PATCH v6 03/10] x86emul: support MOVDIR{I,64B} insns Jan Beulich
2020-04-16 12:25 ` Paul Durrant
2020-04-14 11:45 ` [PATCH v6 04/10] x86emul: support ENQCMD insn Jan Beulich
2020-04-14 11:46 ` Jan Beulich [this message]
2020-04-14 11:48 ` [PATCH v6 06/10] x86emul: support RDPRU Jan Beulich
2020-04-14 11:48 ` [PATCH v6 07/10] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2020-04-14 11:49 ` [PATCH v6 08/10] x86emul: support SERIALIZE Jan Beulich
2020-04-14 11:49 ` [PATCH v6 09/10] x86emul: support X{SUS,RES}LDTRK Jan Beulich
2020-04-14 11:49 ` [PATCH v6 10/10] x86emul: support MCOMMIT Jan Beulich
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