From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751500AbdJEQm6 (ORCPT ); Thu, 5 Oct 2017 12:42:58 -0400 Received: from mail-ve1eur01on0069.outbound.protection.outlook.com ([104.47.1.69]:44448 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751319AbdJEQm4 (ORCPT ); Thu, 5 Oct 2017 12:42:56 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=ed.blake@sondrel.com; Subject: Re: [PATCH 4/4] irqchip: imgpdc: Pass on peripheral mask/unmasks to the parent From: Ed Blake To: James Hogan Cc: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linux-kernel@vger.kernel.org References: <1506938159-466-1-git-send-email-ed.blake@sondrel.com> <1506938159-466-5-git-send-email-ed.blake@sondrel.com> <20171004140302.GG25320@jhogan-linux.le.imgtec.org> <20171005152647.GL25320@jhogan-linux.le.imgtec.org> Message-ID: Date: Thu, 5 Oct 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05 Oct 2017 16:42:52.9185 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4faa3872-698e-4896-80ec-148b916cb1ba X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4P191MB0002 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/10/17 16:43, Ed Blake wrote: > On 05/10/17 16:26, James Hogan wrote: >> On Thu, Oct 05, 2017 at 03:48:53PM +0100, Ed Blake wrote: >>> I'm not sure how this is supposed to work, but the issue seems to be >>> that without this patch the parent irq isn't being masked.  This is >>> causing the parent handler (MIPS GIC in this case) to be called >>> continuously.  This leads to the PDC irq being masked each time, but not >>> the parent irq.  This is the callstack: >>> >>>     "irq-imgpdc.c"::perip_irq_mask >>>     mask_ack_irq >>>     handle_level_irq >>>     generic_handle_irq_desc >>>     generic_handle_irq >>>     generic_handle_irq_desc >>>     generic_handle_irq >>>     gic_handle_shared_int >>>     gic_handle_local_int >>>     "irq-mips-gic.c"::gic_irq_dispatch >>>     generic_handle_irq_desc >>>     generic_handle_irq >>>     do_IRQ >>>     plat_irq_dispatch() >> Right, yeh it shouldn't technically be masked by the parent (contrary to >> what I said above) because its a chained handler, i.e. as far as the >> kernel knows there could be other IRQs coming through that GIC pin that >> would also get masked. >> >> (though IIRC the perip IRQs can wake, but then they go straight out to >> separate dedicated IRQ pins into the main IRQ chip, i.e. the GIC in this >> case). > That's right, each of the PDC peripherals (RTC, WD, IR) has a dedicated > IRQ to the parent, and the sys wakes are muxed onto a single IRQ. >> I think its worth understanding the root cause here though. Disabling >> routing of an IRQ fundamentally should deassert it. Is it an actual >> hardware bug that has reached silicon? > So you think the PDC->parent IRQ must not be being de-asserted when > IRQ_ROUTE is cleared?  I hadn't considered this and thought it was some > persistence in the GIC due to not being masked / ack'd there.  Is that > possible?  I'll discuss the possible IRQ_ROUTE issue with the hardware team. OK, I've looked at the RTL and discussed it with the hardware team, and yes it's a bug.  Clearing IRQ_ROUTE will not clear a PDC->GIC IRQ once asserted, the only way is to clear the RTC->PDC IRQ, which we can't do at this point as interrupts are disabled.  So I think this method of propagating the mask to the parent is a reasonable workaround.  Is it ok if I just modify the commit message and add comments to make it clear it's a workaround for a h/w bug? Ed.