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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id kr16sm352606pjb.23.2021.02.15.13.01.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Feb 2021 13:01:55 -0800 (PST) Subject: Re: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20210214175912.732946-1-f4bug@amsat.org> <20210214175912.732946-29-f4bug@amsat.org> From: Richard Henderson Message-ID: Date: Mon, 15 Feb 2021 13:01:52 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210214175912.732946-29-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Aleksandar Rikalo , Fredrik Noring , Laurent Vivier , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote: > Now than SQ is properly implemented, we can move the RDHWR > kludge required to have usermode working with recent glibc. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/translate.c | 56 ------------------------------------ > target/mips/tx79_translate.c | 34 +++++++++++++++++++++- > 2 files changed, 33 insertions(+), 57 deletions(-) > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index c1d07a4591d..0fa2b3bcc15 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -1780,7 +1780,6 @@ enum { > > enum { > MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ > - MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ > }; > > /* > @@ -27330,53 +27329,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) > } > } > > -static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) > -{ > - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ > -} > - > -/* > - * The TX79-specific instruction Store Quadword > - * > - * +--------+-------+-------+------------------------+ > - * | 011111 | base | rt | offset | SQ > - * +--------+-------+-------+------------------------+ > - * 6 5 5 16 > - * > - * has the same opcode as the Read Hardware Register instruction > - * > - * +--------+-------+-------+-------+-------+--------+ > - * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR > - * +--------+-------+-------+-------+-------+--------+ > - * 6 5 5 5 5 6 > - * > - * that is required, trapped and emulated by the Linux kernel. However, all > - * RDHWR encodings yield address error exceptions on the TX79 since the SQ > - * offset is odd. Therefore all valid SQ instructions can execute normally. > - * In user mode, QEMU must verify the upper and lower 11 bits to distinguish > - * between SQ and RDHWR, as the Linux kernel does. > - */ > -static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) > -{ > - int base = extract32(ctx->opcode, 21, 5); > - int rt = extract32(ctx->opcode, 16, 5); > - int offset = extract32(ctx->opcode, 0, 16); > - > -#ifdef CONFIG_USER_ONLY > - uint32_t op1 = MASK_SPECIAL3(ctx->opcode); > - uint32_t op2 = extract32(ctx->opcode, 6, 5); > - > - if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) { > - int rd = extract32(ctx->opcode, 11, 5); > - > - gen_rdhwr(ctx, rt, rd, 0); > - return; > - } > -#endif > - > - gen_mmi_sq(ctx, base, rt, offset); > -} > - > #endif > > static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) > @@ -27561,15 +27513,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) > } > break; > case OPC_SPECIAL3: > -#if defined(TARGET_MIPS64) > - if (ctx->insn_flags & INSN_R5900) { > - decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ > - } else { > - decode_opc_special3(env, ctx); > - } > -#else > decode_opc_special3(env, ctx); > -#endif > break; > case OPC_REGIMM: > op1 = MASK_REGIMM(ctx->opcode); > diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c > index 386bae7808b..2aa3182d21d 100644 > --- a/target/mips/tx79_translate.c > +++ b/target/mips/tx79_translate.c > @@ -411,7 +411,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) > return true; > } > > -static bool trans_SQ(DisasContext *ctx, arg_itype *a) > +static bool trans_SQ_real(DisasContext *ctx, arg_itype *a) > { > TCGv_i64 t0 = tcg_temp_new_i64(); > TCGv addr = tcg_temp_new(); > @@ -438,6 +438,38 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) > return true; > } > > +static bool trans_SQ(DisasContext *ctx, arg_itype *a) > +{ > + /* > + * The TX79-specific instruction Store Quadword > + * > + * +--------+-------+-------+------------------------+ > + * | 011111 | base | rt | offset | SQ > + * +--------+-------+-------+------------------------+ > + * 6 5 5 16 > + * > + * has the same opcode as the Read Hardware Register instruction > + * > + * +--------+-------+-------+-------+-------+--------+ > + * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR > + * +--------+-------+-------+-------+-------+--------+ > + * 6 5 5 5 5 6 > + * > + * that is required, trapped and emulated by the Linux kernel. However, all > + * RDHWR encodings yield address error exceptions on the TX79 since the SQ > + * offset is odd. Not that it's odd (the final address is masked, remember), but that it a store to an address in the zero page. > Therefore all valid SQ instructions can execute normally. > + * In user mode, QEMU must verify the upper and lower 13 bits to distinguish 11 bits. > + * between SQ and RDHWR, as the Linux kernel does. > + */ > +#if defined(CONFIG_USER_ONLY) > + if (!a->base && extract32(a->offset, 0, 11) == 0b00000111011) { > + gen_rdhwr(ctx, a->rt, extract32(ctx->opcode, 11, 5), 0); > + return true; > + } > +#endif I would do this as { RDHWR_user 011111 00000 ..... ..... 00000 111011 @rd_rt SQ 011111 ..... ..... ................ @ldst } static bool trans_RDHWR_user(DisasContext *ctx, arg_rtype *a) { #ifdef CONFIG_USER_ONLY gen_rdhwr(ctx, a->rt, a->rd, 0); return true; #else return false; #endif } r~