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Thu, 20 Oct 2022 05:02:10 -0700 (PDT) Received: from [192.168.1.107] ([149.135.10.35]) by smtp.gmail.com with ESMTPSA id k33-20020a635621000000b00460a5c6304dsm3250334pgb.67.2022.10.20.05.02.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Oct 2022 05:02:09 -0700 (PDT) Message-ID: Date: Thu, 20 Oct 2022 22:01:56 +1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st Content-Language: en-US To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, lzw194868@alibaba-inc.com References: <20221020104154.4276-1-zhiwei_liu@linux.alibaba.com> <20221020104154.4276-2-zhiwei_liu@linux.alibaba.com> <4373f964-3336-d076-5284-d5a2983ddd88@linaro.org> <6c468fb2-c41e-a7dc-8fef-10185dffeca9@linux.alibaba.com> From: Richard Henderson In-Reply-To: <6c468fb2-c41e-a7dc-8fef-10185dffeca9@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Oct 2022 12:02:23 -0000 On 10/20/22 21:42, LIU Zhiwei wrote: > > On 2022/10/20 19:18, Richard Henderson wrote: >> On 10/20/22 20:41, LIU Zhiwei wrote: >>> When guest base is zero, we should use addr_regl as base regiser instead of >>> the initial register TCG_REG_TMP0. >>> >>> Signed-off-by: LIU Zhiwei >>> --- >>>   tcg/riscv/tcg-target.c.inc | 4 ++++ >>>   1 file changed, 4 insertions(+) >>> >>> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc >>> index 81a83e45b1..32f4bc7bfc 100644 >>> --- a/tcg/riscv/tcg-target.c.inc >>> +++ b/tcg/riscv/tcg-target.c.inc >>> @@ -1185,6 +1185,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, >>> bool is_64) >>>       } >>>       if (guest_base != 0) { >>>           tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); >>> +    } else { >>> +        base = addr_regl; >>>       } >> >> You're right that there's a bug here, where TMP0 remains uninitialized.  I think it >> would be better to reorg the other direction: begin with initializeing base = addr_regl, > > Do you mean only in user mode? I see TCG_REG_TMP0 has been used in tcg_out_tlb_load when > system mode. Well, yes, since that's what you're patching here... r~