From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94732C352A1 for ; Wed, 30 Nov 2022 07:21:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233880AbiK3HVi (ORCPT ); Wed, 30 Nov 2022 02:21:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229648AbiK3HVf (ORCPT ); Wed, 30 Nov 2022 02:21:35 -0500 Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 038211F9D9; Tue, 29 Nov 2022 23:21:34 -0800 (PST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 3E9AF32008C3; Wed, 30 Nov 2022 02:21:31 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 30 Nov 2022 02:21:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1669792890; x= 1669879290; bh=q72EpL3uhOPRJqv9dDJjBbzAkGOsjTb1XnOeKej+X6Y=; b=T 1oA3hm0bUR7Xv8EVN7JD1+jqOy3CWDrA2nAw/zq8z9ewbU3FQ8BBdMxfxP9FTE8y tuYufw1idtHR12TPdU7wDWUgwHVtiBc1Jvh0c3hG5sAzi5QWafOHf8snUNIHxkQp pQ4nEFhDJVqX0ybKKMvv1o6wxfnvHMjnBzDR/tzfpPQLh6F1qOy+Alme3W13OYnG 6rIYtNTmTCKr7k8+jfO5fF8TvKST6t6PxkcRN02IqKPTRZsbcp5p57iZ9PyRTWwt yU/yICNdQPw68xFDEIZXTxEe6ze9lR/RSsAnGxUCoj7kplifqz9R4yJpWd3f4X/D 9Irdun8sZQShg21/RCCWg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1669792890; x= 1669879290; bh=q72EpL3uhOPRJqv9dDJjBbzAkGOsjTb1XnOeKej+X6Y=; b=R pYOmhN+h3E3LxnGoY1ByqBMUkdZ/f5rHya6YV4HXgIah0Xz+uVR7bGS/m0AR/hao 6wRFPXOwo1V5Hf7puqFqe29XGyX0QtVwGrKVAZs+2jIg8zAdBPGGIZ84wmQojVCC lVVvLw6DkItgG4OEVCE2cl28nLNZUATNjbqKHuKy8fb5HmYRrerLfG5N63DywkVP Siu8xcTVvs0aqhvmg9ASVSkAgfjHvaq6tdA+BYdNZLnvJ4UHjq7P3a5Rv8yOP9E1 ++L6vEv4rJj15oFj1ZJZZ9fcxK2Rz32m3sO79fXN6lRulgx+JBMng08MU1Nnqt3x Tk6bOHpiu15BfyrwDsAng== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrtddvgddutdeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepkfffgggfvfevfhfhufgjtgfgsehtjeertddtfeejnecuhfhrohhmpefurghm uhgvlhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenuc ggtffrrghtthgvrhhnpeejgfffhfdujeeftdeuudeguedttefgieetffffheejuefguedv heejteeftdfftdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 30 Nov 2022 02:21:28 -0500 (EST) Message-ID: Date: Wed, 30 Nov 2022 01:21:27 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux ppc64le; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Content-Language: en-US To: Jisheng Zhang Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Greg Kroah-Hartman , Jiri Slaby , =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= References: <20221127132448.4034-1-jszhang@kernel.org> <20221127132448.4034-7-jszhang@kernel.org> From: Samuel Holland Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree In-Reply-To: <20221127132448.4034-7-jszhang@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/27/22 07:24, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..f4b170ccc32e > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang > + */ > + > +#include > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { It's unfortunate that the SDK/documentation calls this peripheral both UART0 and UART3. I don't know if we can/should put the "M0" and "D0" bus peripherals in the same DT; it seems like most of the "M0" peripherals are not accessible from the C906. But if we did, this would conflict with the other UART0. > + compatible = "bouffalolab,bl808-uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; There's a clock controller with a mux and a gate between the crystal and the UART. I'm not sure what the policy is about adding "fake" suppliers before the real supplier has a binding defined. Unfortunately, Bouffalolab threw everything and the kitchen sink into the GLB register space, so that complicates defining the binding for the clock/reset controller part. > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, The C906 PLIC has an M-mode context, so 0xffffffff is not correct. This should reference the M-mode external interrupt. > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so this value should be at least that. Regards, Samuel > + }; > + }; > +}; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49BD6C433FE for ; Wed, 30 Nov 2022 07:21:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Subject:From:References:Cc: To:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uRUZmAuzUWTMtBc/wUFuhoi18xA71pIi43mevL0lXHc=; b=zxmPUFgerCqFUY P7nXBtYuqE1MrIXAAy9xdHMrve1WZrVcpNw5uno17ssGKehZBYKSf1XyOAGX9EMy31CdNjkE9x0qA ewBl8nozOgBfoDlpfVoQUrX/tT+yB1axBe1U0pNzxbQ/w+5QnwvNbNJYRE8b+yA6jrgrTu1xsgZhz pcqxDPnfmrG+zwG6ZAAzUfilrRfAyZNqyhCysXOcKffCBEUMPwnKM+8g1LLBFyBD9VtJcLCrB4Q+/ PmgkVppvRvpOa245x5efDRZjgTEKgVsRj6cr3JWCv0iSGzLGtK55aEb/apJ5vEuQKuZ1c2AWn9y11 4FYLCoEHKao7TWDnljfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0HPV-00E5Ue-WB; Wed, 30 Nov 2022 07:21:38 +0000 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0HPS-00E5SX-OT for linux-riscv@lists.infradead.org; Wed, 30 Nov 2022 07:21:36 +0000 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 3E9AF32008C3; Wed, 30 Nov 2022 02:21:31 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Wed, 30 Nov 2022 02:21:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1669792890; x= 1669879290; bh=q72EpL3uhOPRJqv9dDJjBbzAkGOsjTb1XnOeKej+X6Y=; b=T 1oA3hm0bUR7Xv8EVN7JD1+jqOy3CWDrA2nAw/zq8z9ewbU3FQ8BBdMxfxP9FTE8y tuYufw1idtHR12TPdU7wDWUgwHVtiBc1Jvh0c3hG5sAzi5QWafOHf8snUNIHxkQp pQ4nEFhDJVqX0ybKKMvv1o6wxfnvHMjnBzDR/tzfpPQLh6F1qOy+Alme3W13OYnG 6rIYtNTmTCKr7k8+jfO5fF8TvKST6t6PxkcRN02IqKPTRZsbcp5p57iZ9PyRTWwt yU/yICNdQPw68xFDEIZXTxEe6ze9lR/RSsAnGxUCoj7kplifqz9R4yJpWd3f4X/D 9Irdun8sZQShg21/RCCWg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1669792890; x= 1669879290; bh=q72EpL3uhOPRJqv9dDJjBbzAkGOsjTb1XnOeKej+X6Y=; b=R pYOmhN+h3E3LxnGoY1ByqBMUkdZ/f5rHya6YV4HXgIah0Xz+uVR7bGS/m0AR/hao 6wRFPXOwo1V5Hf7puqFqe29XGyX0QtVwGrKVAZs+2jIg8zAdBPGGIZ84wmQojVCC lVVvLw6DkItgG4OEVCE2cl28nLNZUATNjbqKHuKy8fb5HmYRrerLfG5N63DywkVP Siu8xcTVvs0aqhvmg9ASVSkAgfjHvaq6tdA+BYdNZLnvJ4UHjq7P3a5Rv8yOP9E1 ++L6vEv4rJj15oFj1ZJZZ9fcxK2Rz32m3sO79fXN6lRulgx+JBMng08MU1Nnqt3x Tk6bOHpiu15BfyrwDsAng== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrtddvgddutdeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepkfffgggfvfevfhfhufgjtgfgsehtjeertddtfeejnecuhfhrohhmpefurghm uhgvlhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenuc ggtffrrghtthgvrhhnpeejgfffhfdujeeftdeuudeguedttefgieetffffheejuefguedv heejteeftdfftdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 30 Nov 2022 02:21:28 -0500 (EST) Message-ID: Date: Wed, 30 Nov 2022 01:21:27 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux ppc64le; rv:102.0) Gecko/20100101 Thunderbird/102.3.3 Content-Language: en-US To: Jisheng Zhang Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Rob Herring , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Greg Kroah-Hartman , Jiri Slaby , =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= References: <20221127132448.4034-1-jszhang@kernel.org> <20221127132448.4034-7-jszhang@kernel.org> From: Samuel Holland Subject: Re: [PATCH v2 6/9] riscv: dts: bouffalolab: add the bl808 SoC base device tree In-Reply-To: <20221127132448.4034-7-jszhang@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_232134_873316_6ACA2D96 X-CRM114-Status: GOOD ( 20.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 11/27/22 07:24, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..f4b170ccc32e > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang > + */ > + > +#include > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { It's unfortunate that the SDK/documentation calls this peripheral both UART0 and UART3. I don't know if we can/should put the "M0" and "D0" bus peripherals in the same DT; it seems like most of the "M0" peripherals are not accessible from the C906. But if we did, this would conflict with the other UART0. > + compatible = "bouffalolab,bl808-uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; There's a clock controller with a mux and a gate between the crystal and the UART. I'm not sure what the policy is about adding "fake" suppliers before the real supplier has a binding defined. Unfortunately, Bouffalolab threw everything and the kitchen sink into the GLB register space, so that complicates defining the binding for the clock/reset controller part. > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, The C906 PLIC has an M-mode context, so 0xffffffff is not correct. This should reference the M-mode external interrupt. > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; The SDK/documentation lists IRQ numbers up to BL808_IRQ_PDS == 82, so this value should be at least that. Regards, Samuel > + }; > + }; > +}; _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv