From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Philippe Brucker Subject: Re: [PATCH 35/37] iommu/arm-smmu-v3: Add support for PRI Date: Mon, 5 Mar 2018 13:09:19 +0000 Message-ID: References: <20180212183352.22730-1-jean-philippe.brucker@arm.com> <20180212183352.22730-36-jean-philippe.brucker@arm.com> <6f55afcf-04b0-0dc4-6c75-064b70e6851c@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <6f55afcf-04b0-0dc4-6c75-064b70e6851c-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Dongdong Liu , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" Cc: Mark Rutland , "ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" , Catalin Marinas , "xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org" , Will Deacon , "okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" , "ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org" , "bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org" , "rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org" , "lenb-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org" , "dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org" , "rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org" , Sudeep Holla , "christian.koenig-5C7GfCeVMHo@public.gmane.org" List-Id: linux-acpi@vger.kernel.org On 05/03/18 12:29, Dongdong Liu wrote: >> >> +static int arm_smmu_enable_pri(struct arm_smmu_master_data *master) >> +{ >> + int ret, pos; >> + struct pci_dev *pdev; >> + /* >> + * TODO: find a good inflight PPR number. We should divide the PRI queue >> + * by the number of PRI-capable devices, but it's impossible to know >> + * about current and future (hotplugged) devices. So we're at risk of >> + * dropping PPRs (and leaking pending requests in the FQ). >> + */ >> + size_t max_inflight_pprs = 16; >> + struct arm_smmu_device *smmu = master->smmu; >> + >> + if (!(smmu->features & ARM_SMMU_FEAT_PRI) || !dev_is_pci(master->dev)) >> + return -ENOSYS; >> + >> + pdev = to_pci_dev(master->dev); >> + > From here >> + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); >> + if (!pos) >> + return -ENOSYS; > to here, seems this code is not needed as it is already done in > pci_reset_pri(). Indeed, thanks. It would allow to differentiate a device that doesn't support PRI from a reset error, but since we ignore the return value at the moment I'll remove it. Thanks, Jean From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Subject: Re: [PATCH 35/37] iommu/arm-smmu-v3: Add support for PRI To: Dongdong Liu , "linux-arm-kernel@lists.infradead.org" , "linux-pci@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "devicetree@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" References: <20180212183352.22730-1-jean-philippe.brucker@arm.com> <20180212183352.22730-36-jean-philippe.brucker@arm.com> <6f55afcf-04b0-0dc4-6c75-064b70e6851c@huawei.com> From: Jean-Philippe Brucker Message-ID: Date: Mon, 5 Mar 2018 13:09:19 +0000 MIME-Version: 1.0 In-Reply-To: <6f55afcf-04b0-0dc4-6c75-064b70e6851c@huawei.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "xieyisheng1@huawei.com" , "ilias.apalodimas@linaro.org" , Catalin Marinas , "xuzaibo@huawei.com" , "jonathan.cameron@huawei.com" , Will Deacon , "okaya@codeaurora.org" , "yi.l.liu@intel.com" , Lorenzo Pieralisi , "ashok.raj@intel.com" , "tn@semihalf.com" , "joro@8bytes.org" , "bharatku@xilinx.com" , "rfranz@cavium.com" , "lenb@kernel.org" , "jacob.jun.pan@linux.intel.com" , "alex.williamson@redhat.com" , "robh+dt@kernel.org" , "thunder.leizhen@huawei.com" , "bhelgaas@google.com" , "shunyong.yang@hxt-semitech.com" , "dwmw2@infradead.org" , "liubo95@huawei.com" , "rjw@rjwysocki.net" , "jcrouse@codeaurora.org" , "robdclark@gmail.com" , "hanjun.guo@linaro.org" , Sudeep Holla , Robin Murphy , "christian.koenig@amd.com" , "nwatters@codeaurora.org" Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: On 05/03/18 12:29, Dongdong Liu wrote: >> >> +static int arm_smmu_enable_pri(struct arm_smmu_master_data *master) >> +{ >> + int ret, pos; >> + struct pci_dev *pdev; >> + /* >> + * TODO: find a good inflight PPR number. We should divide the PRI queue >> + * by the number of PRI-capable devices, but it's impossible to know >> + * about current and future (hotplugged) devices. So we're at risk of >> + * dropping PPRs (and leaking pending requests in the FQ). >> + */ >> + size_t max_inflight_pprs = 16; >> + struct arm_smmu_device *smmu = master->smmu; >> + >> + if (!(smmu->features & ARM_SMMU_FEAT_PRI) || !dev_is_pci(master->dev)) >> + return -ENOSYS; >> + >> + pdev = to_pci_dev(master->dev); >> + > From here >> + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); >> + if (!pos) >> + return -ENOSYS; > to here, seems this code is not needed as it is already done in > pci_reset_pri(). Indeed, thanks. It would allow to differentiate a device that doesn't support PRI from a reset error, but since we ignore the return value at the moment I'll remove it. Thanks, Jean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: jean-philippe.brucker@arm.com (Jean-Philippe Brucker) Date: Mon, 5 Mar 2018 13:09:19 +0000 Subject: [PATCH 35/37] iommu/arm-smmu-v3: Add support for PRI In-Reply-To: <6f55afcf-04b0-0dc4-6c75-064b70e6851c@huawei.com> References: <20180212183352.22730-1-jean-philippe.brucker@arm.com> <20180212183352.22730-36-jean-philippe.brucker@arm.com> <6f55afcf-04b0-0dc4-6c75-064b70e6851c@huawei.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 05/03/18 12:29, Dongdong Liu wrote: >> >> +static int arm_smmu_enable_pri(struct arm_smmu_master_data *master) >> +{ >> + int ret, pos; >> + struct pci_dev *pdev; >> + /* >> + * TODO: find a good inflight PPR number. We should divide the PRI queue >> + * by the number of PRI-capable devices, but it's impossible to know >> + * about current and future (hotplugged) devices. So we're at risk of >> + * dropping PPRs (and leaking pending requests in the FQ). >> + */ >> + size_t max_inflight_pprs = 16; >> + struct arm_smmu_device *smmu = master->smmu; >> + >> + if (!(smmu->features & ARM_SMMU_FEAT_PRI) || !dev_is_pci(master->dev)) >> + return -ENOSYS; >> + >> + pdev = to_pci_dev(master->dev); >> + > From here >> + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); >> + if (!pos) >> + return -ENOSYS; > to here, seems this code is not needed as it is already done in > pci_reset_pri(). Indeed, thanks. It would allow to differentiate a device that doesn't support PRI from a reset error, but since we ignore the return value at the moment I'll remove it. Thanks, Jean