From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrice CHOTARD Date: Wed, 18 Mar 2020 09:46:39 +0000 Subject: [PATCH 8/9] ram: stm32mp1: reduce delay after BIST reset for tuning In-Reply-To: <20200306111355.8.I2ed443e2c15db6b007f836254b3753da9b06e76d@changeid> References: <20200306101412.15376-1-patrick.delaunay@st.com> <20200306111355.8.I2ed443e2c15db6b007f836254b3753da9b06e76d@changeid> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 3/6/20 11:14 AM, Patrick Delaunay wrote: > Reduce the delay after BIST delay, from 1ms to 10us > which is enough accoriding datasheet. > > Signed-off-by: Patrick Delaunay > --- > > drivers/ram/stm32mp1/stm32mp1_tuning.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c > index 07d57d496c..3013b7b667 100644 > --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c > +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c > @@ -402,7 +402,7 @@ run: > writel(rand(), &phy->bistlsr); > > /* some delay to reset BIST */ > - mdelay(1); > + udelay(10); > > /*Perform BIST Run*/ > clrsetbits_le32(&phy->bistrr, Acked-by: Patrice Chotard Thanks Patrice