From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Subject: Re: [PATCH 00/92] ram: rk3399: Add LPDDR4 support Date: Thu, 13 Jun 2019 09:44:16 +0800 Message-ID: References: <20190611145135.21399-1-jagan@amarulasolutions.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To: Jagan Teki , Simon Glass , Philipp Tomsich , YouMin Chen , u-boot@lists.denx.de Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, gajjar04akash@gmail.com List-Id: linux-rockchip.vger.kernel.org SGkgSmFnYW4sCgrCoMKgwqAgVmVyeSBncmF0ZWZ1bCBmb3IgeW91IHRvIHNlbmQgdGhpcyBwYXRj aCBzZXQgZm9yIExQRERSNCBzdXBwb3J0LgoKwqDCoMKgIEJ1dCwgOTIgcGF0Y2hlcywgYSBsaXR0 bGUgYml0IHRvbyBtdWNoIGZvciBtZXJnZSB0aGVtIG9uZSBieSBvbmUsCgppcyBpdCBwb3NzaWJs ZSBmb3IgVS1Cb290IHRvIG1lcmdlIHRoaXMgZnJvbSBzb21ld2hlcmUgYWZ0ZXIgd2UgcmV2aWV3 CgphbGwgdGhlc2UgcGF0Y2hlcz8KCgpUaGFua3MsCi0gS2V2ZXIKT24gMDYvMTEvMjAxOSAxMDo1 MCBQTSwgSmFnYW4gVGVraSB3cm90ZToKPiBZZXMsIGl0IGNhbiBiZSBwb3NzaWJsZSB0byBicmVh ayB0aGlzIHNlcmllcyBpbnRvIG11bHRpcGxlIHN1YiBzZXJpZXMKPiBidXQgaWRlYSBoZXJlIGlz IHRvIG1hcmsgYWxsIHRoZSByZXF1aXJlZCBjaGFuZ2VzIHRvIHN1cHBvcnQgTFBERFI0IAo+IGlu IHJrMzM5OSBpbiBvbmUgc2V0LiBpZiByZXF1aXJlZCB3ZSBjYW4gYnJlYWsgaXQgZnJvbSBuZXh0 IHZlcnNpb25zLgo+Cj4gVGhpcyBpcyB0aGUgaW5pdGlhbCBzZXQgZm9yIHN1cHBvcnRpbmcgTFBE RFI0IHdpdGggYXNzb2NpYXRlZAo+IGZlYXR1cmVzLgo+Cj4gVGhhbmtzIHRvCj4gLSBZb3VNaW4g Q2hlbgo+IC0gQWthc2ggR2FqamFyCj4gLSBLZXZlciBZYW5nCj4gZm9yIHN1cHBvcnRpbmcgYWxs IHRoZSBoZWxwIG9uIHRoaXMgd29yay4KPgo+IE9uIHN1bW1hcnkgdGhpcyBzZXJpZXMgc3VwcG9y dAo+IC0gQ29kZSB3YXJuaW5nIGFuZCBmaXhlcwo+IC0gcmFuayBkZXRlY3Rpb24sIHRoaXMgd291 bGQgcmVxdWlyZWQgdG8gcHJvYmUgc2luZ2xlIGNoYW5uZWwgCj4gICBzZHJhbSBjb25maWd1cmVk IGluIE5hbm9QSS1ORU80Cj4gLSBMUEREUjQgc3VwcG9ydCwgdGVzdGVkIGluIFJvY2twcm82NCBh bmQgUm9jay1QSS00Cj4KPiBwYXRjaCAwMDAxIC0gMDAzMzogZml4IGNvZGUgd2FybmluZ3MsIHBy aW50cywgbmV3IG1hY3Jvcwo+Cj4gcGF0Y2ggMDAzNCAtIDAwNTE6IHJhbmsgZGV0ZWN0aW9uLCBz ZHJhbSBkZWJ1ZyBjb2RlCj4KPiBwYXRjaCAwMDUyOiBVc2UgRERSMy0xODAwIG9uIE5hbm9QSS1O RU80Cj4KPiBwYXRjaCAwMDUzIC0gMDA4OTogbHBkZHI0IHN1cHBvcnQKPgo+IHBhdGNoIDAwOTA6 IExQRERSNC0xMDAgdGltaW5ncwo+Cj4gcGF0Y2ggMDA5MTogVXNlIExQRERSNC0xMDAgb24gUm9j a3BybzY0Cj4KPiBwYXRjaCAwMDkyOiBVc2UgTFBERFI0LTEwMCBvbiBSb2NrLVBJIDQKPgo+IE5v dGU6IFB1bWEgcmszMzk5IGhhcyBTUEwgc2l6ZSBvdmVyZmxvdywgYmV0dGVyIHRvIGVuYWJsZSBU UEwKPiBmb3IgdGhpcyBib2FyZC4KPgo+IEFueSBpbnB1dHM/Cj4gSmFnYW4uCj4KPiBKYWdhbiBU ZWtpICg5Mik6Cj4gICByYW06IHJrMzM5OTogRml4IGNvZGUgd2FybmluZ3MKPiAgIHJhbTogcmsz Mzk5OiBBZGQgc3BhY2UgYmV0d2VlbiBzdHJpbmcgd2l0aCBmb3JtYXQgc3BlY2lmaWVyCj4gICBy YW06IHJrMzM5OTogQWRkIHByb3BlciBzcGFjZXMgaW4gZGF0YSB0cmFpbmluZwo+ICAgcmFtOiBy azMzOTk6IEhhbmRsZSBkYXRhIHRyYWluaW5nIHJldHVybiB0eXBlcwo+ICAgcmFtOiByazMzOTk6 IE9yZGVyIGluY2x1ZGUgZmlsZXMKPiAgIHJhbTogcmszMzk5OiBNb3ZlIG1hY3JvIGFmdGVyIGlu Y2x1ZGUgZmlsZXMKPiAgIHJhbTogcmszMzk5OiBDbGVhciBQSV8xNzUgaW50ZXJydXB0cyBpbiBk YXRhIHRyYWluaW5nCj4gICByYW06IHJrMzM5OTogVXNlIHJhbmsgbWFzayBpbiBjYSBkYXRhIHRy YWluaW5nCj4gICByYW06IHJrMzM5OTogVXNlIHJhbmsgbWFzayBpbiB3ZHFsIGRhdGEgdHJhaW5p bmcKPiAgIHJhbTogcmszMzk5OiBBZGQgZGRydHlwZSBlbmMgbWFjcm8KPiAgIHJhbTogcmszMzk5 OiBBZGQgY2hhbm5lbCBudW1iZXIgZW5jb2RlciBtYWNybwo+ICAgcmFtOiByazMzOTk6IEFkZCBy b3dfM180IGVuYyBtYWNybwo+ICAgcmFtOiByazMzOTk6IEFkZCBjaGlwaW5mbyBtYWNybwo+ICAg cmFtOiByazMzOTk6IEFkZCByYW5rIGVuYyBtYWNybwo+ICAgcmFtOiByazMzOTk6IEFkZCBjb2x1 bW4gZW5jIG1hY3JvCj4gICByYW06IHJrMzM5OTogQWRkIGJrIGVuYyBtYWNybwo+ICAgcmFtOiBy azMzOTk6IEFkZCBkYncgZW5jIG1hY3JvCj4gICByYW06IHJrMzM5OTogQWRkIGNzMF9ydyBtYWNy bwo+ICAgcmFtOiByazMzOTk6IEFkZCBjczFfcncgbWFjcm8KPiAgIHJhbTogcmszMzk5OiBBZGQg YncgZW5jIG1hY3JvCj4gICByYW06IHJrMzM5OTogUmVuYW1lIHN5c19yZWcgd2l0aCBzeXNfcmVn Mgo+ICAgcmFtOiByazMzOTk6IFVwZGF0ZSBjczBfcm93IHRvIHVzZSBzeXNfcmVnMwo+ICAgcmFt OiByazMzOTk6IFVwZGF0ZSBjczFfcm93IHRvIHVzZSBzeXNfcmVnMwo+ICAgcmFtOiByazMzOTk6 IEFkZCBjczFfY29sIGVuYyBtYWNybwo+ICAgcmFtOiByazMzOTk6IEFkZCBkZHIgdmVyc2lvbiBl bmMgbWFjcm8KPiAgIHJhbTogcmszMzk5OiBBZGQgZGRydGltaW5nQzAKPiAgIHJhbTogcmszMzk5 OiBBZGQgRGRyTW9kZQo+ICAgcmFtOiByazMzOTk6IEhhbmRsZSBwY3RsX2NmZyByZXR1cm4gdHlw ZQo+ICAgcmFtOiByazMzOTk6IHMvdHNlbF93cl9zZWxlY3Rfbi90c2VsX3dyX3NlbGVjdF9kcV9u Cj4gICByYW06IHJrMzM5OTogcy90c2VsX3dyX3NlbGVjdF9wL3RzZWxfd3Jfc2VsZWN0X2RxX3AK PiAgIHJhbTogcmszMzk5OiBzL2NhX3RzZWxfd3Jfc2VsZWN0X24vdHNlbF93cl9zZWxlY3RfY2Ff bgo+ICAgcmFtOiByazMzOTk6IHMvY2FfdHNlbF93cl9zZWxlY3RfcC90c2VsX3dyX3NlbGVjdF9j YV9wCj4gICByYW06IHJrMzM5OTogT3JkZXIgdHNlbCB2YXJpYWJsZXMKPiAgIHJhbTogcmszMzk5 OiBBZGQgcGh5IHBjdHJsIHJlc2V0IHN1cHBvcnQKPiAgIHJhbTogcmszMzk5OiBNb3ZlIHB3cnVw X3NyZWZyZXNoX2V4aXQgdG8gZHJhbV9pbmZvCj4gICByYW06IHJrMzM5OTogQWRkIHBjdGwgc3Rh cnQgc3VwcG9ydAo+ICAgcmFtOiByb2NrY2hpcDogcmszMzk5OiBBZGQgY2FwX2luZm8gc3RydWN0 dXJlCj4gICByYW06IHJrMzM5OTogcy9yazMzOTlfYmFzZV9wYXJhbXMvc2RyYW1fYmFzZV9wYXJh bXMKPiAgIHJhbTogcmszMzk5OiBNb3ZlIGNvbW1vbiBzZHJhbSBzdHJ1Y3R1cmVzIGluIGNvbW1v biBoZWFkZXIKPiAgIGFybTogaW5jbHVkZTogcm9ja2NoaXA6IE1vdmUgZHJhbXR5cGVzIHRvIGNv bW1vbiBoZWFkZXIKPiAgIGFybTogaW5jbHVkZTogcm9ja2NoaXA6IEFkZCBERFI0IGVudW0KPiAg IHJhbTogcm9ja2NoaXA6IEFkZCBpbml0aWFsIEtjb25maWcKPiAgIGRlYnVnX3VhcnQ6IEFkZCBw cmludGRlYwo+ICAgcmFtOiByb2NrY2hpcDogQWRkIGRlYnVnIHNkcmFtIGRyaXZlcgo+ICAgcmFt OiByb2NrY2hpcDogZGVidWc6IEFkZCBzZHJhbV9wcmludF9kZHJfaW5mbwo+ICAgcmFtOiByb2Nr Y2hpcDogZGVidWc6IEdldCB0aGUgY3MgY2FwYWNpdHkKPiAgIHJhbTogcmszMzk5OiBkZWJ1Zzog QWRkIHNkcmFtX3ByaW50X3N0cmlkZQo+ICAgcmFtOiByazMzOTk6IENvbXB1dGUgc3RyaWRlIGZv ciAyIGNoYW5uZWxzCj4gICByYW06IHJrMzM5OTogQ29tcHV0ZSBzdHJpZGUgZm9yIDEgY2hhbm5l bCBhCj4gICByYW06IHJrMzM5OTogQWRkIHJhbmsgZGV0ZWN0aW9uIHN1cHBvcnQKPiAgIHJhbTog cmszMzk5OiBFbmFibGUgc2RyYW0gZGVidWcgZnVuY3Rpb25zCj4gICByb2NrY2hpcDogZHRzOiBy azMzOTk6IG5hbm9waS1uZW80OiBVc2UgRERSMy0xODY2IGR0c2kKPiAgIGNsazogcm9ja2NoaXA6 IHJrMzM5OTogRml4IGNoZWNrIHBhdGNoIHdhcm5pbmdzIGFuZCBjaGVja3MKPiAgIGNsazogcm9j a2NoaXA6IHJrMzM5OTogU2V0IDUwTUh6IGRkciBjbG9jawo+ICAgY2xrOiByb2NrY2hpcDogcmsz Mzk5OiBTZXQgNDAwTUh6IGRkciBjbG9jawo+ICAgcmFtOiByazMzOTk6IEFkZCBzcGFjZXMgaW4g cGN0bF9jZmcKPiAgIHJhbTogcmszMzk5OiBDb25maWd1cmUgcGh5IElPIGluIGRzIG9kdAo+ICAg cmFtOiByazMzOTk6IEFkZCBscGRkcjQgcmFuayBtYXNrIGZvciBjcyB0cmFpbmluZwo+ICAgcmFt OiByazMzOTk6IEFkZCBscGRkcjQgcmFuayBtYXNrIGZvciB3ZHFsIHRyYWluaW5nCj4gICByYW06 IHJrMzM5OTogTW92ZSBtb2RlX3NlbCBhc3NpZ25tZW50Cj4gICByYW06IHJrMzM5OTogRG9uJ3Qg d2FpdCBmb3IgUExMIGxvY2sgaW4gbHBkZHI0Cj4gICByYW06IHJrMzM5OTogQXZvaWQgdHdvIGNo YW5uZWwgWlEgQ2FsIFN0YXJ0IGF0IHRoZSBzYW1lIHRpbWUKPiAgIHJhbTogcmszMzk5OiBDb25m aWd1cmUgUEhZXzg5OCwgUEhZXzkxOSBmb3IgbHBkZHI0Cj4gICByYW06IHJrMzM5OTogQ29uZmln dXJlIEJPT1NUUF9FTiwgQk9PU1ROX0VOIGZvciBscGRkcjQKPiAgIHJhbTogcmszMzk5OiBDb25m aWd1cmUgU0xFV1BfRU4sIFNMRVdOX0VOIGZvciBscGRkcjQKPiAgIHJhbTogcmszMzk5OiBDb25m aWd1cmUgUEhZIFJYX0NNX0lOUFVUIGZvciBscGRkcjQKPiAgIHJhbTogcmszMzk5OiBNYXAgY2hp cHNlbGVjdCBmb3IgbHBkZHI0Cj4gICByYW06IHJrMzM5OTogQ29uZmlndXJlIHRzZWwgd3JpdGUg Y2EgZm9yIGxwZGRyNAo+ICAgcmFtOiByazMzOTk6IERvbid0IGRpc2FibGUgZGZpIGRyYW0gY2xr IGZvciBscGRkcjQsIHJhbmsgMQo+ICAgcmFtOiByazMzOTk6IEFkZCBJTyBzZXR0aW5ncwo+ICAg cmFtOiBzZHJhbTogQ29uZmlndXJlIGxwZGRyNCB0c2VsIHJkLCB3ciBiYXNlZCBvbiBJTyBzZXR0 aW5ncwo+ICAgcmFtOiByazMzOTk6IEFkZCB0c2VsIGNvbnRyb2wgY2xvY2sgZHJpdmUKPiAgIHJh bTogcmszMzk5OiBDb25maWd1cmUgc29jIG9kdCBzdXBwb3J0Cj4gICByYW06IHJrMzM5OTogR2V0 IGxwZGRyNCB0c2VsX3JkX2VuIGZyb20gaW8gc2V0dGluZ3MKPiAgIHJhbTogcmszMzk5OiBVcGRh dGUgbHBkZHI0IHZyZWYgYmFzZWQgb24gaW8gc2V0dGluZ3MKPiAgIHJhbTogcmszMzk5OiBVcGRh dGUgbHBkZHI0IG1vZGVfc2VsIGJhc2VkIG9uIGlvIHNldHRpbmdzCj4gICByYW06IHJrMzM5OTog VXBkYXRlIGxwZGRyNCB2cmVmX21vZGVfYWMKPiAgIHJhbTogcmszMzk5OiBBZGQgTFBQRFI0IG1y IGRldGVjdGlvbgo+ICAgYXJtOiBpbmNsdWRlOiByb2NrY2hpcDogQWRkIHJrMzM5OSBwbXUgZmls ZQo+ICAgcm9ja2NoaXA6IHJrMzM5OTogc3lzY29uOiBBZGQgcG11IHN1cHBvcnQKPiAgIHJvY2tj aGlwOiBkdHM6IHJrMzM5OTogQWRkIHUtYm9vdCxkbS1wcmUtcmVsb2MgZm9yIHBtdQo+ICAgcmFt OiByazMzOTk6IEFkZCBMUFBERFI0LTQwMCB0aW1pbmdzIGluYwo+ICAgcmFtOiByazMzOTk6IEFk ZCBMUFBERFI0LTgwMCB0aW1pbmdzIGluYwo+ICAgcmFtOiByazMzOTk6IEFkZCBscGRkcjQgc2V0 IHJhdGUgc3VwcG9ydAo+ICAgcmFtOiByazMzOTk6IFNldCBscGRkcjQgZHEgb2R0Cj4gICByYW06 IHJrMzM5OTogU2V0IGxwZGRyNCBjYSBvZHQKPiAgIHJhbTogcmszMzk5OiBTZXQgbHBkZHI0IE1S Mwo+ICAgcmFtOiByazMzOTk6IFNldCBscGRkcjQgTVIxMgo+ICAgcmFtOiByazMzOTk6IFNldCBs cGRkcjQgTVIxNAo+ICAgcm9ja2NoaXA6IGR0czogcmszMzk5OiBBZGQgTFBERFI0LTEwMCB0aW1p bmdzCj4gICByb2NrY2hpcDogZHRzOiByazMzOTk6IHJvY2twcm82NDogVXNlIExQRERSNC0xMDAg ZHRzaQo+ICAgcm9ja2NoaXA6IGR0czogcmszMzk5OiByb2NrLXBpLTQ6IFVzZSBMUEREUjQtMTAw IGR0c2kKPgo+ICBhcmNoL2FybS9kdHMvcmszMzk5LW5hbm9waS1uZW80LXUtYm9vdC5kdHNpICAg fCAgICAxICsKPiAgYXJjaC9hcm0vZHRzL3JrMzM5OS1yb2NrLXBpLTQtdS1ib290LmR0c2kgICAg IHwgICAgMSArCj4gIGFyY2gvYXJtL2R0cy9yazMzOTktcm9ja3BybzY0LXUtYm9vdC5kdHNpICAg ICB8ICAgIDEgKwo+ICBhcmNoL2FybS9kdHMvcmszMzk5LXNkcmFtLWxwZGRyNC0xMDAuZHRzaSAg ICAgfCAxNTM3ICsrKysrKysrKysrKwo+ICBhcmNoL2FybS9kdHMvcmszMzk5LXUtYm9vdC5kdHNp ICAgICAgICAgICAgICAgfCAgICA0ICsKPiAgLi4uL2luY2x1ZGUvYXNtL2FyY2gtcm9ja2NoaXAv cG11X3JrMzM5OS5oICAgIHwgICA3MiArCj4gIGFyY2gvYXJtL2luY2x1ZGUvYXNtL2FyY2gtcm9j a2NoaXAvc2RyYW0uaCAgICB8ICAgIDYgLQo+ICAuLi4vaW5jbHVkZS9hc20vYXJjaC1yb2NrY2hp cC9zZHJhbV9jb21tb24uaCAgfCAgIDg5ICsKPiAgLi4uL2luY2x1ZGUvYXNtL2FyY2gtcm9ja2No aXAvc2RyYW1fcmszMjJ4LmggIHwgICAgNyAtCj4gIC4uLi9pbmNsdWRlL2FzbS9hcmNoLXJvY2tj aGlwL3NkcmFtX3JrMzM5OS5oICB8ICAgNjUgKy0KPiAgYXJjaC9hcm0vbWFjaC1yb2NrY2hpcC9y azMzOTkvc3lzY29uX3JrMzM5OS5jIHwgICAgOCArCj4gIGRyaXZlcnMvY2xrL3JvY2tjaGlwL2Ns a19yazMzOTkuYyAgICAgICAgICAgICB8ICAgNzYgKy0KPiAgZHJpdmVycy9yYW0vS2NvbmZpZyAg ICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAgMSArCj4gIGRyaXZlcnMvcmFtL3JvY2tjaGlw L0tjb25maWcgICAgICAgICAgICAgICAgICB8ICAgMjYgKwo+ICBkcml2ZXJzL3JhbS9yb2NrY2hp cC9NYWtlZmlsZSAgICAgICAgICAgICAgICAgfCAgICAzICstCj4gIC4uLi9yYW0vcm9ja2NoaXAv c2RyYW0tcmszMzk5LWxwZGRyNC00MDAuaW5jICB8IDE1NzAgKysrKysrKysrKysrCj4gIC4uLi9y YW0vcm9ja2NoaXAvc2RyYW0tcmszMzk5LWxwZGRyNC04MDAuaW5jICB8IDE1NzAgKysrKysrKysr KysrCj4gIGRyaXZlcnMvcmFtL3JvY2tjaGlwL3NkcmFtX2RlYnVnLmMgICAgICAgICAgICB8ICAx NDcgKysKPiAgZHJpdmVycy9yYW0vcm9ja2NoaXAvc2RyYW1fcmszMzk5LmMgICAgICAgICAgIHwg MjE3NiArKysrKysrKysrKysrKy0tLQo+ICBpbmNsdWRlL2RlYnVnX3VhcnQuaCAgICAgICAgICAg ICAgICAgICAgICAgICAgfCAgIDE5ICsKPiAgMjAgZmlsZXMgY2hhbmdlZCwgNjk2NCBpbnNlcnRp b25zKCspLCA0MTUgZGVsZXRpb25zKC0pCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybS9k dHMvcmszMzk5LXNkcmFtLWxwZGRyNC0xMDAuZHRzaQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgYXJj aC9hcm0vaW5jbHVkZS9hc20vYXJjaC1yb2NrY2hpcC9wbXVfcmszMzk5LmgKPiAgY3JlYXRlIG1v ZGUgMTAwNjQ0IGRyaXZlcnMvcmFtL3JvY2tjaGlwL0tjb25maWcKPiAgY3JlYXRlIG1vZGUgMTAw NjQ0IGRyaXZlcnMvcmFtL3JvY2tjaGlwL3NkcmFtLXJrMzM5OS1scGRkcjQtNDAwLmluYwo+ICBj cmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9yYW0vcm9ja2NoaXAvc2RyYW0tcmszMzk5LWxwZGRy NC04MDAuaW5jCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3JhbS9yb2NrY2hpcC9zZHJh bV9kZWJ1Zy5jCj4KCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KVS1Cb290IG1haWxpbmcgbGlzdApVLUJvb3RAbGlzdHMuZGVueC5kZQpodHRwczovL2xp c3RzLmRlbnguZGUvbGlzdGluZm8vdS1ib290Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Thu, 13 Jun 2019 09:44:16 +0800 Subject: [U-Boot] [PATCH 00/92] ram: rk3399: Add LPDDR4 support In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de Hi Jagan,     Very grateful for you to send this patch set for LPDDR4 support.     But, 92 patches, a little bit too much for merge them one by one, is it possible for U-Boot to merge this from somewhere after we review all these patches? Thanks, - Kever On 06/11/2019 10:50 PM, Jagan Teki wrote: > Yes, it can be possible to break this series into multiple sub series > but idea here is to mark all the required changes to support LPDDR4 > in rk3399 in one set. if required we can break it from next versions. > > This is the initial set for supporting LPDDR4 with associated > features. > > Thanks to > - YouMin Chen > - Akash Gajjar > - Kever Yang > for supporting all the help on this work. > > On summary this series support > - Code warning and fixes > - rank detection, this would required to probe single channel > sdram configured in NanoPI-NEO4 > - LPDDR4 support, tested in Rockpro64 and Rock-PI-4 > > patch 0001 - 0033: fix code warnings, prints, new macros > > patch 0034 - 0051: rank detection, sdram debug code > > patch 0052: Use DDR3-1800 on NanoPI-NEO4 > > patch 0053 - 0089: lpddr4 support > > patch 0090: LPDDR4-100 timings > > patch 0091: Use LPDDR4-100 on Rockpro64 > > patch 0092: Use LPDDR4-100 on Rock-PI 4 > > Note: Puma rk3399 has SPL size overflow, better to enable TPL > for this board. > > Any inputs? > Jagan. > > Jagan Teki (92): > ram: rk3399: Fix code warnings > ram: rk3399: Add space between string with format specifier > ram: rk3399: Add proper spaces in data training > ram: rk3399: Handle data training return types > ram: rk3399: Order include files > ram: rk3399: Move macro after include files > ram: rk3399: Clear PI_175 interrupts in data training > ram: rk3399: Use rank mask in ca data training > ram: rk3399: Use rank mask in wdql data training > ram: rk3399: Add ddrtype enc macro > ram: rk3399: Add channel number encoder macro > ram: rk3399: Add row_3_4 enc macro > ram: rk3399: Add chipinfo macro > ram: rk3399: Add rank enc macro > ram: rk3399: Add column enc macro > ram: rk3399: Add bk enc macro > ram: rk3399: Add dbw enc macro > ram: rk3399: Add cs0_rw macro > ram: rk3399: Add cs1_rw macro > ram: rk3399: Add bw enc macro > ram: rk3399: Rename sys_reg with sys_reg2 > ram: rk3399: Update cs0_row to use sys_reg3 > ram: rk3399: Update cs1_row to use sys_reg3 > ram: rk3399: Add cs1_col enc macro > ram: rk3399: Add ddr version enc macro > ram: rk3399: Add ddrtimingC0 > ram: rk3399: Add DdrMode > ram: rk3399: Handle pctl_cfg return type > ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n > ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p > ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n > ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p > ram: rk3399: Order tsel variables > ram: rk3399: Add phy pctrl reset support > ram: rk3399: Move pwrup_srefresh_exit to dram_info > ram: rk3399: Add pctl start support > ram: rockchip: rk3399: Add cap_info structure > ram: rk3399: s/rk3399_base_params/sdram_base_params > ram: rk3399: Move common sdram structures in common header > arm: include: rockchip: Move dramtypes to common header > arm: include: rockchip: Add DDR4 enum > ram: rockchip: Add initial Kconfig > debug_uart: Add printdec > ram: rockchip: Add debug sdram driver > ram: rockchip: debug: Add sdram_print_ddr_info > ram: rockchip: debug: Get the cs capacity > ram: rk3399: debug: Add sdram_print_stride > ram: rk3399: Compute stride for 2 channels > ram: rk3399: Compute stride for 1 channel a > ram: rk3399: Add rank detection support > ram: rk3399: Enable sdram debug functions > rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi > clk: rockchip: rk3399: Fix check patch warnings and checks > clk: rockchip: rk3399: Set 50MHz ddr clock > clk: rockchip: rk3399: Set 400MHz ddr clock > ram: rk3399: Add spaces in pctl_cfg > ram: rk3399: Configure phy IO in ds odt > ram: rk3399: Add lpddr4 rank mask for cs training > ram: rk3399: Add lpddr4 rank mask for wdql training > ram: rk3399: Move mode_sel assignment > ram: rk3399: Don't wait for PLL lock in lpddr4 > ram: rk3399: Avoid two channel ZQ Cal Start at the same time > ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 > ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4 > ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4 > ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4 > ram: rk3399: Map chipselect for lpddr4 > ram: rk3399: Configure tsel write ca for lpddr4 > ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 > ram: rk3399: Add IO settings > ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings > ram: rk3399: Add tsel control clock drive > ram: rk3399: Configure soc odt support > ram: rk3399: Get lpddr4 tsel_rd_en from io settings > ram: rk3399: Update lpddr4 vref based on io settings > ram: rk3399: Update lpddr4 mode_sel based on io settings > ram: rk3399: Update lpddr4 vref_mode_ac > ram: rk3399: Add LPPDR4 mr detection > arm: include: rockchip: Add rk3399 pmu file > rockchip: rk3399: syscon: Add pmu support > rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu > ram: rk3399: Add LPPDDR4-400 timings inc > ram: rk3399: Add LPPDDR4-800 timings inc > ram: rk3399: Add lpddr4 set rate support > ram: rk3399: Set lpddr4 dq odt > ram: rk3399: Set lpddr4 ca odt > ram: rk3399: Set lpddr4 MR3 > ram: rk3399: Set lpddr4 MR12 > ram: rk3399: Set lpddr4 MR14 > rockchip: dts: rk3399: Add LPDDR4-100 timings > rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi > rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi > > arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 + > arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 + > arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 + > arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++ > arch/arm/dts/rk3399-u-boot.dtsi | 4 + > .../include/asm/arch-rockchip/pmu_rk3399.h | 72 + > arch/arm/include/asm/arch-rockchip/sdram.h | 6 - > .../include/asm/arch-rockchip/sdram_common.h | 89 + > .../include/asm/arch-rockchip/sdram_rk322x.h | 7 - > .../include/asm/arch-rockchip/sdram_rk3399.h | 65 +- > arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 + > drivers/clk/rockchip/clk_rk3399.c | 76 +- > drivers/ram/Kconfig | 1 + > drivers/ram/rockchip/Kconfig | 26 + > drivers/ram/rockchip/Makefile | 3 +- > .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++ > .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++ > drivers/ram/rockchip/sdram_debug.c | 147 ++ > drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++--- > include/debug_uart.h | 19 + > 20 files changed, 6964 insertions(+), 415 deletions(-) > create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi > create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h > create mode 100644 drivers/ram/rockchip/Kconfig > create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc > create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc > create mode 100644 drivers/ram/rockchip/sdram_debug.c >