Re: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs

[Aditya Swarup <aditya.swarup@intel.com>]

On 1/11/21 12:57 PM, Matt Roper wrote:
> On Mon, Jan 11, 2021 at 10:18:45PM +0200, Jani Nikula wrote:
>> On Mon, 11 Jan 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>> On Fri, 08 Jan 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
>>>> On Fri, Jan 08, 2021 at 03:18:52PM -0800, Aditya Swarup wrote:
>>>>> TGL adds another level of indirection for applying WA based on stepping
>>>>> information rather than PCI REVID. So change TGL_REVID enum into
>>>>> stepping enum and use PCI REVID as index into revid to stepping table to
>>>>> fetch correct display and GT stepping for application of WAs as
>>>>> suggested by Matt Roper.
>>>>
>>>> So to clarify the goal is to rename "revid" -> "stepping" because the
>>>> values like "A1," "C0," etc. are't the actual PCI revision ID, but
>>>> rather descriptions of the stepping of a given IP block; the enum values
>>>> we use to represent those are arbitrary and don't matter as long as
>>>> they're monotonically increasing for comparisons.  The PCI revision ID
>>>> is just the input we use today to deduce what the IP steppings are, and
>>>> there's talk that we could determine the IP steppings in a different way
>>>> at some point in the future.
>>>>
>>>> Furthermore, since the same scheme will be used at least for ADL-S, we
>>>> should drop the "TGL" prefix since there's no need to name these general
>>>> enum values in a platform-specific manner.
>>>>
>>>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>>>
>>>> We should probably make the same kind of change to KBL (and use the same
>>>> stepping enum) too since it has the same kind of extra indirection as
>>>> TGL/ADL-S, but we can do that as a followup patch.
>>>
>>> FWIW I have a wip series changing the whole thing to abstract steppings
>>> enums that are shared between platforms, but it's in a bit of limbo
>>> because the previous revid changes were applied to drm-intel-gt-next,
>>> and it's fallen pretty far out of sync with drm-intel-next. All of this
>>> really belongs to drm-intel-next, but can't do that until the branches
>>> sync up again.
>>
>> Btw this series doesn't apply to drm-intel-next either, for the same
>> reason, and the ADL-S platform definition and PCI IDs must *not* be
>> applied to drm-intel-gt-next.

The reason behind this patch not cleanly applying on drm-intel-next is because
drm/i915/tgl: Add bound checks and simplify TGL REVID macros
isn't present on that branch but present on gt-next. 

The patch doesn't apply on gt-next because of a conflict in the following hunk:
        /* Wa_1409825376:tgl (pre-prod)*/
-       if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
+       if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))

which can be easily fixed during backmerge process as I was able apply the patch
cleanly on gt-next. 
I don't understand the "must *not*" reasoning behind not applying this patch on gt-next.

It was common consesus during initial review that separating stepping/revid parsing in a 
separate .c file will be pushed in after ADLS changes and adding this patch won't add any extra
churn, just a minor rebase for your approach.

Regards,
aswarup

> 
> So to clarify, it looks like we have a bunch of revid changes to the
> display code that got merged to the gt-next tree but not to the
> intel-next tree?  Should we be going back and also merging /
> cherry-picking those over to intel-next since that's where the display
> changes are supposed to go, or is it too late to do that cleanly at this
> point?
> 
> Going forward, what should the general strategy be for stuff like
> platform definitions and such?  Merge such enablement patches to both
> intel-next and gt-next at the same time so that the basic definitions
> are available to both trees?  It seems like the whole split into two
> trees really isn't working well and is just leading to more mistakes and
> bottlenecks.  What benefit are we supposed to be getting from this
> split?> 
> 
> Matt
> 
> 
>>
>> BR,
>> Jani.
>>
>>>
>>> My series also completely hides the arrays into a separate .c file,
>>> because the externs with direct array access are turning into
>>> nightmare. The ARRAY_SIZE() checks rely on the extern declaration and
>>> the actual array definition to have the sizes in sync, but the compiler
>>> does not check that. Really.
>>>
>>> IDK, feels like this merging this series is going to be extra churn.
>>>
>>>
>>> BR,
>>> Jani.
>>>
>>>
>>>>
>>>>
>>>> Matt
>>>>
>>>>>
>>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>>>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>>>>> ---
>>>>>  .../drm/i915/display/intel_display_power.c    |  2 +-
>>>>>  drivers/gpu/drm/i915/display/intel_psr.c      |  4 +-
>>>>>  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
>>>>>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 26 +++++-----
>>>>>  drivers/gpu/drm/i915/i915_drv.h               | 50 +++++++++----------
>>>>>  drivers/gpu/drm/i915/intel_pm.c               |  2 +-
>>>>>  6 files changed, 43 insertions(+), 43 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>>> index d52374f01316..bb04b502a442 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>>> @@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>>>>>  	int config, i;
>>>>>  
>>>>>  	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>>>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
>>>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
>>>>>  		/* Wa_1409767108:tgl,dg1 */
>>>>>  		table = wa_1409767108_buddy_page_masks;
>>>>>  	else
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> index c24ae69426cf..a93717178957 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>>>>  
>>>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
>>>>>  		/* WA 1408330847 */
>>>>> -		if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>>>> +		if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>>>  		    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
>>>>>  			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>>>  				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>>>>> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>>>>  
>>>>>  	/* WA 1408330847 */
>>>>>  	if (dev_priv->psr.psr2_sel_fetch_enabled &&
>>>>> -	    (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
>>>>> +	    (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
>>>>>  	     IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
>>>>>  		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>>>>>  			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>>>>> index cf3589fd0ddb..4ce32df3855f 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>>>> @@ -3033,7 +3033,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
>>>>>  {
>>>>>  	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
>>>>>  	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
>>>>> -	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
>>>>> +	    IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
>>>>>  		return false;
>>>>>  
>>>>>  	return plane_id < PLANE_SPRITE4;
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> index c21a9726326a..111d01e2f81e 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> @@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
>>>>>  	[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
>>>>>  };
>>>>>  
>>>>> -const struct i915_rev_steppings tgl_uy_revids[] = {
>>>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
>>>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
>>>>> -	[2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
>>>>> -	[3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
>>>>> +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
>>>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
>>>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
>>>>> +	[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
>>>>> +	[3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
>>>>>  };
>>>>>  
>>>>>  /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
>>>>> -const struct i915_rev_steppings tgl_revids[] = {
>>>>> -	[0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
>>>>> -	[1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
>>>>> +const struct i915_rev_steppings tgl_revid_step_tbl[] = {
>>>>> +	[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
>>>>> +	[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
>>>>>  };
>>>>>  
>>>>>  static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
>>>>> @@ -1211,19 +1211,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>>>>  	gen12_gt_workarounds_init(i915, wal);
>>>>>  
>>>>>  	/* Wa_1409420604:tgl */
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>>>  		wa_write_or(wal,
>>>>>  			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
>>>>>  			    CPSSUNIT_CLKGATE_DIS);
>>>>>  
>>>>>  	/* Wa_1607087056:tgl also know as BUG:1409180338 */
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>>>  		wa_write_or(wal,
>>>>>  			    SLICE_UNIT_LEVEL_CLKGATE,
>>>>>  			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>>>>>  
>>>>>  	/* Wa_1408615072:tgl[a0] */
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
>>>>>  		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
>>>>>  			    VSUNIT_CLKGATE_DIS_TGL);
>>>>>  }
>>>>> @@ -1700,7 +1700,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>>>  	struct drm_i915_private *i915 = engine->i915;
>>>>>  
>>>>>  	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
>>>>> -	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>>>> +	    IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>>>  		/*
>>>>>  		 * Wa_1607138336:tgl[a0],dg1[a0]
>>>>>  		 * Wa_1607063988:tgl[a0],dg1[a0]
>>>>> @@ -1710,7 +1710,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>>>  			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
>>>>>  	}
>>>>>  
>>>>> -	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
>>>>> +	if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
>>>>>  		/*
>>>>>  		 * Wa_1606679103:tgl
>>>>>  		 * (see also Wa_1606682166:icl)
>>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>>> index 5e5bcef20e33..11d6e8abde46 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>>> @@ -1559,54 +1559,54 @@ extern const struct i915_rev_steppings kbl_revids[];
>>>>>  	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
>>>>>  
>>>>>  enum {
>>>>> -	TGL_REVID_A0,
>>>>> -	TGL_REVID_B0,
>>>>> -	TGL_REVID_B1,
>>>>> -	TGL_REVID_C0,
>>>>> -	TGL_REVID_D0,
>>>>> +	STEP_A0,
>>>>> +	STEP_B0,
>>>>> +	STEP_B1,
>>>>> +	STEP_C0,
>>>>> +	STEP_D0,
>>>>>  };
>>>>>  
>>>>> -#define TGL_UY_REVIDS_SIZE	4
>>>>> -#define TGL_REVIDS_SIZE		2
>>>>> +#define TGL_UY_REVID_STEP_TBL_SIZE	4
>>>>> +#define TGL_REVID_STEP_TBL_SIZE		2
>>>>>  
>>>>> -extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
>>>>> -extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
>>>>> +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
>>>>> +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
>>>>>  
>>>>>  static inline const struct i915_rev_steppings *
>>>>> -tgl_revids_get(struct drm_i915_private *dev_priv)
>>>>> +tgl_stepping_get(struct drm_i915_private *dev_priv)
>>>>>  {
>>>>>  	u8 revid = INTEL_REVID(dev_priv);
>>>>>  	u8 size;
>>>>> -	const struct i915_rev_steppings *tgl_revid_tbl;
>>>>> +	const struct i915_rev_steppings *revid_step_tbl;
>>>>>  
>>>>>  	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
>>>>> -		tgl_revid_tbl = tgl_uy_revids;
>>>>> -		size = ARRAY_SIZE(tgl_uy_revids);
>>>>> +		revid_step_tbl = tgl_uy_revid_step_tbl;
>>>>> +		size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
>>>>>  	} else {
>>>>> -		tgl_revid_tbl = tgl_revids;
>>>>> -		size = ARRAY_SIZE(tgl_revids);
>>>>> +		revid_step_tbl = tgl_revid_step_tbl;
>>>>> +		size = ARRAY_SIZE(tgl_revid_step_tbl);
>>>>>  	}
>>>>>  
>>>>>  	revid = min_t(u8, revid, size - 1);
>>>>>  
>>>>> -	return &tgl_revid_tbl[revid];
>>>>> +	return &revid_step_tbl[revid];
>>>>>  }
>>>>>  
>>>>> -#define IS_TGL_DISP_REVID(p, since, until) \
>>>>> +#define IS_TGL_DISP_STEPPING(p, since, until) \
>>>>>  	(IS_TIGERLAKE(p) && \
>>>>> -	 tgl_revids_get(p)->disp_stepping >= (since) && \
>>>>> -	 tgl_revids_get(p)->disp_stepping <= (until))
>>>>> +	 tgl_stepping_get(p)->disp_stepping >= (since) && \
>>>>> +	 tgl_stepping_get(p)->disp_stepping <= (until))
>>>>>  
>>>>> -#define IS_TGL_UY_GT_REVID(p, since, until) \
>>>>> +#define IS_TGL_UY_GT_STEPPING(p, since, until) \
>>>>>  	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>>>  
>>>>> -#define IS_TGL_GT_REVID(p, since, until) \
>>>>> +#define IS_TGL_GT_STEPPING(p, since, until) \
>>>>>  	(IS_TIGERLAKE(p) && \
>>>>>  	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping >= (since) && \
>>>>> -	 tgl_revids_get(p)->gt_stepping <= (until))
>>>>> +	 tgl_stepping_get(p)->gt_stepping >= (since) && \
>>>>> +	 tgl_stepping_get(p)->gt_stepping <= (until))
>>>>>  
>>>>>  #define RKL_REVID_A0		0x0
>>>>>  #define RKL_REVID_B0		0x1
>>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>>> index bbc73df7f753..319acca2630b 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>>> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
>>>>>  		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>>>>>  
>>>>>  	/* Wa_1409825376:tgl (pre-prod)*/
>>>>> -	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
>>>>> +	if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1))
>>>>>  		intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
>>>>>  			   TGL_VRH_GATING_DIS);
>>>>>  
>>>>> -- 
>>>>> 2.27.0
>>>>>
>>
>> -- 
>> Jani Nikula, Intel Open Source Graphics Center
> 

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