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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id w2sm9157149pfc.126.2021.06.07.16.33.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 16:33:02 -0700 (PDT) Subject: Re: [PATCH 04/55] target/arm: Add handling for PSR.ECI/ICI To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210607165821.9892-1-peter.maydell@linaro.org> <20210607165821.9892-5-peter.maydell@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 7 Jun 2021 16:33:00 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210607165821.9892-5-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/7/21 9:57 AM, Peter Maydell wrote: > +void clear_eci_state(DisasContext *s) > +{ > + /* > + * Clear any ECI/ICI state: used when a load multiple/store > + * multiple insn executes. > + */ > + if (s->eci) { > + TCGv_i32 tmp = tcg_temp_new_i32(); > + tcg_gen_movi_i32(tmp, 0); tcg_const_i32 or preferably tcg_constant_i32. > + /* > + * the CONDEXEC TB flags are CPSR bits [15:10][26:25]. On A-profile this > + * is always the IT bits. On M-profile, some of the reserved encodings > + * of IT are used instead to indicate either ICI or ECI, which > + * indicate partial progress of a restartable insn that was interrupted > + * partway through by an exception: > + * * if CONDEXEC[3:0] != 0b0000 : CONDEXEC is IT bits > + * * if CONDEXEC[3:0] == 0b0000 : CONDEXEC is ICI or ECI bits > + * In all cases CONDEXEC == 0 means "not in IT block or restartable > + * insn, behave normally". > + */ > + if (condexec & 0xf) { > + dc->condexec_mask = (condexec & 0xf) << 1; > + dc->condexec_cond = condexec >> 4; > + dc->eci = 0; > + } else { > + dc->condexec_mask = 0; > + dc->condexec_cond = 0; > + if (arm_feature(env, ARM_FEATURE_M)) { > + dc->eci = condexec >> 4; > + } This else leaves eci uninitialized. > dc->insn = insn; > > + if (dc->eci) { > + /* > + * For M-profile continuable instructions, ECI/ICI handling > + * falls into these cases: > + * - interrupt-continuable instructions > + * These are the various load/store multiple insns (both > + * integer and fp). The ICI bits indicate the register > + * where the load/store can resume. We make the IMPDEF > + * choice to always do "instruction restart", ie ignore > + * the ICI value and always execute the ldm/stm from the > + * start. So all we need to do is zero PSR.ICI if the > + * insn executes. > + * - MVE instructions subject to beat-wise execution > + * Here the ECI bits indicate which beats have already been > + * executed, and we must honour this. Each insn of this > + * type will handle it correctly. We will update PSR.ECI > + * in the helper function for the insn (some ECI values > + * mean that the following insn also has been partially > + * executed). > + * - Special cases which don't advance ECI > + * The insns LE, LETP and BKPT leave the ECI/ICI state > + * bits untouched. > + * - all other insns (the common case) > + * Non-zero ECI/ICI means an INVSTATE UsageFault. > + * We place a rewind-marker here. Insns in the previous > + * three categories will set a flag in the DisasContext. > + * If the flag isn't set after we call disas_thumb_insn() > + * or disas_thumb2_insn() then we know we have a "some other > + * insn" case. We will rewind to the marker (ie throwing away > + * all the generated code) and instead emit "take exception". > + */ > + dc->eci_handled = false; This should be done in arm_tr_init_disas_context, I think, unconditionally, next to eci. > + dc->insn_eci_rewind = tcg_last_op(); I believe that this is identical to dc->insn_start. Certainly there does not seem to be any possibility of any opcodes emitted in between. If you think we should use a different field, then initialize it to null next to eci/eci_handled. r~