From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752999AbdDKNzT (ORCPT ); Tue, 11 Apr 2017 09:55:19 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:32665 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751799AbdDKNzQ (ORCPT ); Tue, 11 Apr 2017 09:55:16 -0400 X-IronPort-AV: E=Sophos;i="5.37,185,1488870000"; d="scan'208";a="1325519" Subject: Re: [PATCH v3 06/32] avr32: include default ioremap_nopost() implementation To: Lorenzo Pieralisi , References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> <20170411122923.6285-7-lorenzo.pieralisi@arm.com> CC: , , Bjorn Helgaas , Haavard Skinnemoen , , Hans-Christian Egtvedt From: Nicolas Ferre Organization: atmel Message-ID: Date: Tue, 11 Apr 2017 15:55:15 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20170411122923.6285-7-lorenzo.pieralisi@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: =?Windows-1252?Q?H4sIAAAAAAAAC+NgFnrGKsWRWlGSWpSXmKPExsXCxeXDomv+4E2Ewddr?= =?Windows-1252?Q?x8wsljRlWHSve8Ru8eNrM4tFx66vLBabHl9jtbi8aw6bxdl5x9ks3vx+?= =?Windows-1252?Q?we7A4bFm3hpGj52z7rJ7LNhU6rF5Sb3HolOf2T0+b5ILYItizcxLyq9I?= =?Windows-1252?Q?YM04Pvklc8E6/ooTN5cwNTB+4eli5OIQEljBKHF26n+2LkZODmGBMIlt?= =?Windows-1252?Q?c7sYQWwRAR+J9uaHYHEhgUKJ25862UEamAVeMUqc7t7ICpJgE9CVODvh?= =?Windows-1252?Q?CVARBwe/gLDEmanxIGFeARuJiff2s4CEWQRUJWY/0AEJiwpESDzs3MUO?= =?Windows-1252?Q?USIocXLmExYQm1PATuLFvT1gE5kFDCSOLJoDZctLNG+dzQxxgopE3/t+?= =?Windows-1252?Q?dpCREgKBEj8exYKEJQScJHYun8oCYdtJHJ5+kR3CdpBY+nsOO0xN+9I3?= =?Windows-1252?Q?rBC2tsT2V/ugbB2JbQf7oXptJfbMmMgEYbtLPHi0HMr2lZj1sAGqJkri?= =?Windows-1252?Q?7bxTLBMYpWYh+WAWkqtnIbl6ASPzKkZpZw8/3eAwXdcIZw8DU73c5IwC?= =?Windows-1252?Q?3dzEzDy95PzcTYyQGM/awfi7M+IQoyQHk5Iob8DM1xFCfEn5KZUZicUZ?= =?Windows-1252?Q?8UWlOanFhxhlODiUJHib7r6JEBIsSk1PrUjLzAEmG5g0EwfnIUYJDh4l?= =?Windows-1252?Q?Ed5SkBre4oLE3OLMdIj8KUZJKXFejXtACQGQREZpHlzvJUZRKWFeyStA?= =?Windows-1252?Q?OZ6C1KLczBKI+C1GMY6HTByPmYRY8vLzUqWATmUAAgPGV4ziHIxKQC0g?= =?Windows-1252?Q?43gy80rg1gDTBdAHIrxndr0EuaAkESEl1cDYcnfl5aiibvN21xu3M8Ra?= =?Windows-1252?Q?JiZd2a/1q+aN/ddd07cbH9e992x+0TWBZQtPG7Nn7CkK4+evvd3WtXOJ?= =?Windows-1252?Q?9D6xznvv+3nCpx2avXSD5ORTCwQ4TzUftQu9cybk4o3N+4JOLtqvXvQn?= =?Windows-1252?Q?+6LYEf8nByLbrq2R+yvKVcG60o29+NlxMQOXn+sbFk5Na/q6QomlOCPR?= =?Windows-1252?Q?UIu5qDgRAHTj2/B5AwAA?= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 11/04/2017 à 14:28, Lorenzo Pieralisi a écrit : > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > > Signed-off-by: Lorenzo Pieralisi > Cc: Bjorn Helgaas > Cc: Hans-Christian Egtvedt > Cc: Haavard Skinnemoen > --- > arch/avr32/include/asm/io.h | 1 + > 1 file changed, 1 insertion(+) You probably need to remove this one as the avr32 architecture will be removed in kernel 4.12: https://lkml.org/lkml/2017/3/27/422 Best regards, > diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h > index f855646..b2ff522 100644 > --- a/arch/avr32/include/asm/io.h > +++ b/arch/avr32/include/asm/io.h > @@ -298,6 +298,7 @@ extern void __iounmap(void __iomem *addr); > #define ioremap_wc ioremap_nocache > #define ioremap_wt ioremap_nocache > #define ioremap_uc ioremap_nocache > +#include > > #define cached(addr) P1SEGADDR(addr) > #define uncached(addr) P2SEGADDR(addr) > -- Nicolas Ferre From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Subject: Re: [PATCH v3 06/32] avr32: include default ioremap_nopost() implementation To: Lorenzo Pieralisi , References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> <20170411122923.6285-7-lorenzo.pieralisi@arm.com> From: Nicolas Ferre Message-ID: Date: Tue, 11 Apr 2017 15:55:15 +0200 MIME-Version: 1.0 In-Reply-To: <20170411122923.6285-7-lorenzo.pieralisi@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , Haavard Skinnemoen , linux-arm-kernel@lists.infradead.org, Hans-Christian Egtvedt Content-Type: text/plain; charset="windows-1252" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: Le 11/04/2017 =E0 14:28, Lorenzo Pieralisi a =E9crit : > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > = > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > = > Signed-off-by: Lorenzo Pieralisi > Cc: Bjorn Helgaas > Cc: Hans-Christian Egtvedt > Cc: Haavard Skinnemoen > --- > arch/avr32/include/asm/io.h | 1 + > 1 file changed, 1 insertion(+) You probably need to remove this one as the avr32 architecture will be removed in kernel 4.12: https://lkml.org/lkml/2017/3/27/422 Best regards, > diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h > index f855646..b2ff522 100644 > --- a/arch/avr32/include/asm/io.h > +++ b/arch/avr32/include/asm/io.h > @@ -298,6 +298,7 @@ extern void __iounmap(void __iomem *addr); > #define ioremap_wc ioremap_nocache > #define ioremap_wt ioremap_nocache > #define ioremap_uc ioremap_nocache > +#include > = > #define cached(addr) P1SEGADDR(addr) > #define uncached(addr) P2SEGADDR(addr) > = -- = Nicolas Ferre _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nicolas Ferre Subject: Re: [PATCH v3 06/32] avr32: include default ioremap_nopost() implementation Date: Tue, 11 Apr 2017 15:55:15 +0200 Message-ID: References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> <20170411122923.6285-7-lorenzo.pieralisi@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit Return-path: Received: from esa2.microchip.iphmx.com ([68.232.149.84]:32665 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751799AbdDKNzQ (ORCPT ); Tue, 11 Apr 2017 09:55:16 -0400 In-Reply-To: <20170411122923.6285-7-lorenzo.pieralisi@arm.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Lorenzo Pieralisi , linux-pci@vger.kernel.org Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , Haavard Skinnemoen , linux-arm-kernel@lists.infradead.org, Hans-Christian Egtvedt Le 11/04/2017 à 14:28, Lorenzo Pieralisi a écrit : > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > > Signed-off-by: Lorenzo Pieralisi > Cc: Bjorn Helgaas > Cc: Hans-Christian Egtvedt > Cc: Haavard Skinnemoen > --- > arch/avr32/include/asm/io.h | 1 + > 1 file changed, 1 insertion(+) You probably need to remove this one as the avr32 architecture will be removed in kernel 4.12: https://lkml.org/lkml/2017/3/27/422 Best regards, > diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h > index f855646..b2ff522 100644 > --- a/arch/avr32/include/asm/io.h > +++ b/arch/avr32/include/asm/io.h > @@ -298,6 +298,7 @@ extern void __iounmap(void __iomem *addr); > #define ioremap_wc ioremap_nocache > #define ioremap_wt ioremap_nocache > #define ioremap_uc ioremap_nocache > +#include > > #define cached(addr) P1SEGADDR(addr) > #define uncached(addr) P2SEGADDR(addr) > -- Nicolas Ferre From mboxrd@z Thu Jan 1 00:00:00 1970 From: nicolas.ferre@atmel.com (Nicolas Ferre) Date: Tue, 11 Apr 2017 15:55:15 +0200 Subject: [PATCH v3 06/32] avr32: include default ioremap_nopost() implementation In-Reply-To: <20170411122923.6285-7-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> <20170411122923.6285-7-lorenzo.pieralisi@arm.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Le 11/04/2017 ? 14:28, Lorenzo Pieralisi a ?crit : > The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") > mandate non-posted configuration transactions. As further highlighted in > the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the > Enhanced Configuration Access Mechanism"), through ECAM and > ECAM-derivative configuration mechanism, the memory mapped transactions > from the host CPU into Configuration Requests on the PCI express fabric > may create ordering problems for software because writes to memory > address are typically posted transactions (unless the architecture can > enforce through virtual address mapping non-posted write transactions > behaviour) but writes to Configuration Space are not posted on the PCI > express fabric. > > Include the asm-generic ioremap_nopost() implementation (currently > falling back to ioremap_nocache()) to provide a non-posted writes > ioremap interface to kernel subsystems. > > Signed-off-by: Lorenzo Pieralisi > Cc: Bjorn Helgaas > Cc: Hans-Christian Egtvedt > Cc: Haavard Skinnemoen > --- > arch/avr32/include/asm/io.h | 1 + > 1 file changed, 1 insertion(+) You probably need to remove this one as the avr32 architecture will be removed in kernel 4.12: https://lkml.org/lkml/2017/3/27/422 Best regards, > diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h > index f855646..b2ff522 100644 > --- a/arch/avr32/include/asm/io.h > +++ b/arch/avr32/include/asm/io.h > @@ -298,6 +298,7 @@ extern void __iounmap(void __iomem *addr); > #define ioremap_wc ioremap_nocache > #define ioremap_wt ioremap_nocache > #define ioremap_uc ioremap_nocache > +#include > > #define cached(addr) P1SEGADDR(addr) > #define uncached(addr) P2SEGADDR(addr) > -- Nicolas Ferre