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Mon, 17 Aug 2020 13:32:39 -0700 (PDT) Subject: Re: [Freedreno] [PATCH v10 3/5] drm/msm/dp: add support for DP PLL driver To: Rob Clark , Jonathan Marek Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , David Airlie , linux-arm-msm , Abhinav Kumar , Linux Kernel Mailing List , dri-devel , Stephen Boyd , khsieh@codeaurora.org, Sean Paul , Tanmay Shah , Daniel Vetter , Vara Reddy , aravindh@codeaurora.org, freedreno , Chandan Uddaraju References: <20200812044223.19279-1-tanmay@codeaurora.org> <20200812044223.19279-4-tanmay@codeaurora.org> <821b5cf9-5ca0-7026-fd99-9a32285ed030@linaro.org> <1ea81fa2-1dc8-a0b9-aa32-3127e9354be2@marek.ca> From: Dmitry Baryshkov Message-ID: Date: Mon, 17 Aug 2020 23:32:37 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 16/08/2020 01:45, Rob Clark wrote: > On Sat, Aug 15, 2020 at 2:21 PM Jonathan Marek wrote: >> >> On 8/15/20 4:20 PM, Rob Clark wrote: >>> On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov >>> wrote: >>>> >>>> >>>> On 12/08/2020 07:42, Tanmay Shah wrote: >>>> > From: Chandan Uddaraju >>>> > >>>> > Add the needed DP PLL specific files to support >>>> > display port interface on msm targets. >>>> >>>> [skipped] >>>> >>>> > diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h >>>> b/drivers/gpu/drm/msm/dp/dp_pll_private.h >>>> > new file mode 100644 >>>> > index 000000000000..475ba6ed59ab >>>> > --- /dev/null >>>> > +++ b/drivers/gpu/drm/msm/dp/dp_pll_private.h >>>> > @@ -0,0 +1,98 @@ >>>> > +/* SPDX-License-Identifier: GPL-2.0-only */ >>>> > +/* >>>> > + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. >>>> > + */ >>>> > + >>>> > +#ifndef __DP_PLL_10NM_H >>>> > +#define __DP_PLL_10NM_H >>>> > + >>>> > +#include "dp_pll.h" >>>> > +#include "dp_reg.h" >>>> > + >>>> > +#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL >>>> > +#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL >>>> > +#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL >>>> > +#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL >>>> > + >>>> > +#define NUM_DP_CLOCKS_MAX 6 >>>> > + >>>> > +#define DP_PHY_PLL_POLL_SLEEP_US 500 >>>> > +#define DP_PHY_PLL_POLL_TIMEOUT_US 10000 >>>> > + >>>> > +#define DP_VCO_RATE_8100MHZDIV1000 8100000UL >>>> > +#define DP_VCO_RATE_9720MHZDIV1000 9720000UL >>>> > +#define DP_VCO_RATE_10800MHZDIV1000 10800000UL >>>> > + >>>> > +struct dp_pll_vco_clk { >>>> > + struct clk_hw hw; >>>> > + unsigned long rate; /* current vco rate */ >>>> > + u64 min_rate; /* min vco rate */ >>>> > + u64 max_rate; /* max vco rate */ >>>> > + void *priv; >>>> > +}; >>>> > + >>>> > +struct dp_pll_db { >>>> >>>> This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for >>>> example, will use slightly different structure. >>> >>> Note that sboyd has a WIP series to move all of the pll code out to a >>> phy driver. If there is work already happening on 7nm support, it >>> might be better to go with the separate phy driver approach? I'm >>> still a bit undecided about whether to land the dp code initially with >>> the pll stuff in drm, and then continue refactoring to move to >>> separate phy driver upstream, or to strip out the pll code from the >>> beginning. If you/someone is working on 7nm support, then feedback >>> about which approach is easier is welcome. >>> >>> https://lore.kernel.org/dri-devel/20200611091919.108018-1-swboyd@chromium.org/ >>> >> >> I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and >> I have done something similar, with the PLL driver in the QMP phy, >> although not based on sboyd's series (along with some typec changes to >> negotiate the DP alt mode and get HPD events, etc.). I don't think >> having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need >> to be aware of the DP PLL/PHY driver, it only needs to set the >> link/pixel clock rates which are in dispcc (and those then have the PLL >> clocks as a parent). > > yeah, in the dp case, having phy split out makes a ton of sense.. it > would maybe be a nice cleanup in other cases (dsi, hdmi) but the > combination of usb+dp makes burying this in drm not so great.. > > It would be good if you could work w/ sboyd on this.. based on what > I've seen on previous gens, it is probably a different phy driver for > 7nm vs 10nm, but I think where we want to end up upstream is with phy > split out of drm. 7nm differs in registers programming, so it would end up with a separate set of tables in qmp phy driver. There is also a 14nm version of dp phy, but I don't know if it usable in any actual hardware design. -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E895C433DF for ; Tue, 18 Aug 2020 07:50:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C8942067C for ; Tue, 18 Aug 2020 07:50:56 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 17 Aug 2020 13:32:40 -0700 (PDT) Received: from [192.168.1.211] ([188.162.65.254]) by smtp.gmail.com with ESMTPSA id p1sm5278763lji.93.2020.08.17.13.32.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Aug 2020 13:32:39 -0700 (PDT) Subject: Re: [Freedreno] [PATCH v10 3/5] drm/msm/dp: add support for DP PLL driver To: Rob Clark , Jonathan Marek References: <20200812044223.19279-1-tanmay@codeaurora.org> <20200812044223.19279-4-tanmay@codeaurora.org> <821b5cf9-5ca0-7026-fd99-9a32285ed030@linaro.org> <1ea81fa2-1dc8-a0b9-aa32-3127e9354be2@marek.ca> From: Dmitry Baryshkov Message-ID: Date: Mon, 17 Aug 2020 23:32:37 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Mailman-Approved-At: Tue, 18 Aug 2020 07:50:42 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Tanmay Shah , David Airlie , linux-arm-msm , Linux Kernel Mailing List , dri-devel , Stephen Boyd , khsieh@codeaurora.org, Sean Paul , Abhinav Kumar , Vara Reddy , aravindh@codeaurora.org, freedreno , Chandan Uddaraju Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 16/08/2020 01:45, Rob Clark wrote: > On Sat, Aug 15, 2020 at 2:21 PM Jonathan Marek wrote: >> >> On 8/15/20 4:20 PM, Rob Clark wrote: >>> On Fri, Aug 14, 2020 at 10:05 AM Dmitry Baryshkov >>> wrote: >>>> >>>> >>>> On 12/08/2020 07:42, Tanmay Shah wrote: >>>> > From: Chandan Uddaraju >>>> > >>>> > Add the needed DP PLL specific files to support >>>> > display port interface on msm targets. >>>> >>>> [skipped] >>>> >>>> > diff --git a/drivers/gpu/drm/msm/dp/dp_pll_private.h >>>> b/drivers/gpu/drm/msm/dp/dp_pll_private.h >>>> > new file mode 100644 >>>> > index 000000000000..475ba6ed59ab >>>> > --- /dev/null >>>> > +++ b/drivers/gpu/drm/msm/dp/dp_pll_private.h >>>> > @@ -0,0 +1,98 @@ >>>> > +/* SPDX-License-Identifier: GPL-2.0-only */ >>>> > +/* >>>> > + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. >>>> > + */ >>>> > + >>>> > +#ifndef __DP_PLL_10NM_H >>>> > +#define __DP_PLL_10NM_H >>>> > + >>>> > +#include "dp_pll.h" >>>> > +#include "dp_reg.h" >>>> > + >>>> > +#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL >>>> > +#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL >>>> > +#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL >>>> > +#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL >>>> > + >>>> > +#define NUM_DP_CLOCKS_MAX 6 >>>> > + >>>> > +#define DP_PHY_PLL_POLL_SLEEP_US 500 >>>> > +#define DP_PHY_PLL_POLL_TIMEOUT_US 10000 >>>> > + >>>> > +#define DP_VCO_RATE_8100MHZDIV1000 8100000UL >>>> > +#define DP_VCO_RATE_9720MHZDIV1000 9720000UL >>>> > +#define DP_VCO_RATE_10800MHZDIV1000 10800000UL >>>> > + >>>> > +struct dp_pll_vco_clk { >>>> > + struct clk_hw hw; >>>> > + unsigned long rate; /* current vco rate */ >>>> > + u64 min_rate; /* min vco rate */ >>>> > + u64 max_rate; /* max vco rate */ >>>> > + void *priv; >>>> > +}; >>>> > + >>>> > +struct dp_pll_db { >>>> >>>> This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for >>>> example, will use slightly different structure. >>> >>> Note that sboyd has a WIP series to move all of the pll code out to a >>> phy driver. If there is work already happening on 7nm support, it >>> might be better to go with the separate phy driver approach? I'm >>> still a bit undecided about whether to land the dp code initially with >>> the pll stuff in drm, and then continue refactoring to move to >>> separate phy driver upstream, or to strip out the pll code from the >>> beginning. If you/someone is working on 7nm support, then feedback >>> about which approach is easier is welcome. >>> >>> https://lore.kernel.org/dri-devel/20200611091919.108018-1-swboyd@chromium.org/ >>> >> >> I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and >> I have done something similar, with the PLL driver in the QMP phy, >> although not based on sboyd's series (along with some typec changes to >> negotiate the DP alt mode and get HPD events, etc.). I don't think >> having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need >> to be aware of the DP PLL/PHY driver, it only needs to set the >> link/pixel clock rates which are in dispcc (and those then have the PLL >> clocks as a parent). > > yeah, in the dp case, having phy split out makes a ton of sense.. it > would maybe be a nice cleanup in other cases (dsi, hdmi) but the > combination of usb+dp makes burying this in drm not so great.. > > It would be good if you could work w/ sboyd on this.. based on what > I've seen on previous gens, it is probably a different phy driver for > 7nm vs 10nm, but I think where we want to end up upstream is with phy > split out of drm. 7nm differs in registers programming, so it would end up with a separate set of tables in qmp phy driver. There is also a 14nm version of dp phy, but I don't know if it usable in any actual hardware design. -- With best wishes Dmitry _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel