From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 378DCC433DB for ; Wed, 24 Mar 2021 02:02:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F362A619F3 for ; Wed, 24 Mar 2021 02:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231544AbhCXCCS (ORCPT ); Tue, 23 Mar 2021 22:02:18 -0400 Received: from mga03.intel.com ([134.134.136.65]:62317 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234715AbhCXCCL (ORCPT ); Tue, 23 Mar 2021 22:02:11 -0400 IronPort-SDR: JKMcKSSGqg3jvq4Jvn7EoU7n3T1FTwwc2d33pezYzhMIgLEKJMbme45kRNwr/5Ad5KoijoG1VQ Yklk5HezqoXA== X-IronPort-AV: E=McAfee;i="6000,8403,9932"; a="190637171" X-IronPort-AV: E=Sophos;i="5.81,272,1610438400"; d="scan'208";a="190637171" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2021 19:02:11 -0700 IronPort-SDR: uCMsn+di9fCqE477yigC9GyHvbFNBLBr+ae5WCYO3wOWgXJQtivfsTUzDZuOjlUyKfW4a8bCNn gcuXUQp2vN1A== X-IronPort-AV: E=Sophos;i="5.81,272,1610438400"; d="scan'208";a="513998532" Received: from likexu-mobl1.ccr.corp.intel.com (HELO [10.238.4.93]) ([10.238.4.93]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2021 19:02:07 -0700 Subject: Re: [PATCH v4 RESEND 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers To: Peter Zijlstra Cc: Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , Kan Liang , x86@kernel.org, linux-kernel@vger.kernel.org, Andi Kleen References: <20210322060635.821531-1-like.xu@linux.intel.com> <20210322060635.821531-3-like.xu@linux.intel.com> <20210323213854.GD4746@worktop.programming.kicks-ass.net> From: Like Xu Organization: Intel OTC Message-ID: Date: Wed, 24 Mar 2021 10:02:05 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210323213854.GD4746@worktop.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/3/24 5:38, Peter Zijlstra wrote: > On Mon, Mar 22, 2021 at 02:06:32PM +0800, Like Xu wrote: >> If the platform supports LBR_INFO register, the x86_pmu.lbr_info will >> be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO > > You mean: intel_pmu_lbr_*init*(). '?' is a single character glob and > you've got too many '_'s. > >> in the x86_perf_get_lbr() directly, instead of relying on lbr_format check. > > But, afaict, not every model calls one of those. CORE_YONAH for example > doesn't. > >> Also Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x >> to hold metadata for the operation, including mispredict, TSX, and >> elapsed cycle time information. > > Relevance? > > Wouldn't it be much simpler to simple say something like: > > "x86_pmu.lbr_info is 0 unless explicitly initialized, so there's no > point checking lbr_fmt" Yes, it is simpler and I will apply it in the next version. > >> Signed-off-by: Like Xu >> Reviewed-by: Kan Liang >> Reviewed-by: Andi Kleen >> --- >> arch/x86/events/intel/lbr.c | 4 +--- >> 1 file changed, 1 insertion(+), 3 deletions(-) >> >> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c >> index 21890dacfcfe..355ea70f1879 100644 >> --- a/arch/x86/events/intel/lbr.c >> +++ b/arch/x86/events/intel/lbr.c >> @@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void) >> */ >> int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) >> { >> - int lbr_fmt = x86_pmu.intel_cap.lbr_format; >> - >> lbr->nr = x86_pmu.lbr_nr; >> lbr->from = x86_pmu.lbr_from; >> lbr->to = x86_pmu.lbr_to; >> - lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; >> + lbr->info = x86_pmu.lbr_info; >> >> return 0; >> } >> -- >> 2.29.2 >>