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Tsirkin" Subject: RE: [RFC 2/2] pci-expender-bus:Add pcie-root-port to pxb-pcie under arm. Thread-Topic: [RFC 2/2] pci-expender-bus:Add pcie-root-port to pxb-pcie under arm. Thread-Index: AQHV4kI1fIh9lqS0F0yGLr3GCBTaKKgYYuQAgAHpLBA= Date: Fri, 14 Feb 2020 07:30:25 +0000 Message-ID: References: <20200213074952.544-1-miaoyubo@huawei.com> <20200213074952.544-3-miaoyubo@huawei.com> <20200213051310-mutt-send-email-mst@kernel.org> In-Reply-To: <20200213051310-mutt-send-email-mst@kernel.org> Accept-Language: en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.173.221.29] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.255 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "peter.maydell@linaro.org" , "imammedo@redhat.com" , "qemu-devel@nongnu.org" , Xiexiangyou , "shannon.zhaosl@gmail.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" > -----Original Message----- > From: Michael S. Tsirkin [mailto:mst@redhat.com] > Sent: Thursday, February 13, 2020 6:17 PM > To: miaoyubo > Cc: peter.maydell@linaro.org; shannon.zhaosl@gmail.com; Xiexiangyou > ; imammedo@redhat.com; qemu- > devel@nongnu.org > Subject: Re: [RFC 2/2] pci-expender-bus:Add pcie-root-port to pxb-pcie > under arm. >=20 > On Thu, Feb 13, 2020 at 03:49:52PM +0800, Yubo Miao wrote: > > From: miaoyubo > > > > Since devices could not directly plugged into pxb-pcie, >=20 > Hmm is this different from the root port? intergrated devices do exist fo= r > that actually. >=20 Thanks for replying The pxb-pcie is like a host bridge, you have to plug pcie-root-port or pci-bridge so devices could be plugged > > under arm, >=20 > how is arm special? >=20 Cureently, if u define a pxb-pcie device, one pcie-root-port or pci-bridge = or something=20 else have to be defined also, The patch just auto generate pcie-root-port f= or arm to=20 avoid affect other architecture > > one > > pcie-root port is plugged into pxb-pcie. Due to the bus for each > > pxb-pcie is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for > > pcie-root-port), only one device could be plugged into one pxb-pcie. >=20 > So why can't we have users specify any number of root ports using -device= ? > then make acpi tables match the # of ports created? >=20 >=20 Users could specify multiply pxb-devices, it is supported. But only one device could be plugged for each pxb-pcie, it is the same wit= h pxb-pci for piix. > > > > Signed-off-by: miaoyubo > > --- > > hw/pci-bridge/pci_expander_bridge.c | 9 +++++++++ > > include/hw/pci/pcie_port.h | 1 + > > 2 files changed, 10 insertions(+) > > > > diff --git a/hw/pci-bridge/pci_expander_bridge.c > > b/hw/pci-bridge/pci_expander_bridge.c > > index 47aaaf8fd1..3d896dd452 100644 > > --- a/hw/pci-bridge/pci_expander_bridge.c > > +++ b/hw/pci-bridge/pci_expander_bridge.c > > @@ -15,6 +15,7 @@ > > #include "hw/pci/pci.h" > > #include "hw/pci/pci_bus.h" > > #include "hw/pci/pci_host.h" > > +#include "hw/pci/pcie_port.h" > > #include "hw/qdev-properties.h" > > #include "hw/pci/pci_bridge.h" > > #include "qemu/range.h" > > @@ -233,7 +234,15 @@ static void pxb_dev_realize_common(PCIDevice > > *dev, bool pcie, Error **errp) > > > > ds =3D qdev_create(NULL, TYPE_PXB_HOST); > > if (pcie) { > > +#ifdef __aarch64__ > > + bus =3D pci_root_bus_new(ds, "pxb-pcie-internal", > > + NULL, NULL, 0, TYPE_PXB_PCIE_BUS); > > + bds =3D qdev_create(BUS(bus), "pcie-root-port"); > > + bds->id =3D dev_name; > > + qdev_prop_set_uint8(bds, PCIE_ROOT_PORT_PROP_CHASSIS, > > +pxb->bus_nr); #else > > bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, > > TYPE_PXB_PCIE_BUS); > > +#endif >=20 > What does all this have to do with building on aarch64? >=20 Based on the comments, this patch would be abandoned in patch V2,=20 PXB-PCIE would also be useful but pcie-root-port or pci-bridge have to Be d= efined by user. > > } else { > > bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, > TYPE_PXB_BUS); > > bds =3D qdev_create(BUS(bus), "pci-bridge"); diff --git > > a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index > > 4b3d254b08..b41d473220 100644 > > --- a/include/hw/pci/pcie_port.h > > +++ b/include/hw/pci/pcie_port.h > > @@ -64,6 +64,7 @@ int pcie_chassis_add_slot(struct PCIESlot *slot); > > void pcie_chassis_del_slot(PCIESlot *s); > > > > #define TYPE_PCIE_ROOT_PORT "pcie-root-port-base" > > +#define PCIE_ROOT_PORT_PROP_CHASSIS "chassis" >=20 > If you are going to do this, replace other instances of "chassis" > with the macro. >=20 Thanks for your replay, this patch would be abandoned. > > #define PCIE_ROOT_PORT_CLASS(klass) \ > > OBJECT_CLASS_CHECK(PCIERootPortClass, (klass), > > TYPE_PCIE_ROOT_PORT) #define PCIE_ROOT_PORT_GET_CLASS(obj) \ > > -- > > 2.19.1 > > Regards, Miao