From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v4 3/3] i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg Date: Thu, 16 Jun 2016 11:52:37 +0200 Message-ID: References: <20160616060621.30422-1-haozhong.zhang@intel.com> <20160616060621.30422-4-haozhong.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj , Laszlo Ersek To: Haozhong Zhang , qemu-devel@nongnu.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:36230 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751563AbcFPJwp (ORCPT ); Thu, 16 Jun 2016 05:52:45 -0400 In-Reply-To: <20160616060621.30422-4-haozhong.zhang@intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 16/06/2016 08:06, Haozhong Zhang wrote: > It's a prerequisite that certain bits of MSR_IA32_FEATURE_CONTROL should > be set before some features (e.g. VMX and LMCE) can be used, which is > usually done by the firmware. This patch adds a fw_cfg file > "etc/msr_feature_control" which contains the advised value of > MSR_IA32_FEATURE_CONTROL and can be used by guest firmware (e.g. SeaBIOS). > > Suggested-by: Paolo Bonzini > Signed-off-by: Haozhong Zhang > --- > hw/i386/pc.c | 28 ++++++++++++++++++++++++++++ > target-i386/cpu.h | 4 ++++ > 2 files changed, 32 insertions(+) > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 7198ed5..d8178a5 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -1147,6 +1147,33 @@ void pc_cpus_init(PCMachineState *pcms) > smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); > } > > +static void pc_build_feature_control_file(PCMachineState *pcms) > +{ > + X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu); > + CPUX86State *env = &cpu->env; > + uint32_t unused, ecx, edx, feature_control_bits = 0; > + uint32_t *val; > + > + cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); > + if (ecx & CPUID_EXT_VMX) { > + feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; > + } > + > + if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == > + (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && > + (env->mcg_cap & MCG_LMCE_P)) { > + feature_control_bits |= FEATURE_CONTROL_LMCE; > + } > + > + if (!feature_control_bits) { > + return; > + } > + > + val = g_malloc(sizeof(*val)); > + *val = feature_control_bits | FEATURE_CONTROL_LOCKED; > + fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); > +} > + > static > void pc_machine_done(Notifier *notifier, void *data) > { > @@ -1174,6 +1201,7 @@ void pc_machine_done(Notifier *notifier, void *data) > acpi_setup(); > if (pcms->fw_cfg) { > pc_build_smbios(pcms->fw_cfg); > + pc_build_feature_control_file(pcms); > } > } > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index f0cb04f..5e07c7a 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -332,6 +332,10 @@ > #define MSR_TSC_ADJUST 0x0000003b > #define MSR_IA32_TSCDEADLINE 0x6e0 > > +#define FEATURE_CONTROL_LOCKED (1<<0) > +#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) > +#define FEATURE_CONTROL_LMCE (1<<20) > + > #define MSR_P6_PERFCTR0 0xc1 > > #define MSR_IA32_SMBASE 0x9e > Reviewed-by: Paolo Bonzini Have you prepared a patch for SeaBIOS already? Thanks, Paolo From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36772) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDTyj-0001Bo-N8 for qemu-devel@nongnu.org; Thu, 16 Jun 2016 05:52:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDTyf-0001GQ-Dy for qemu-devel@nongnu.org; Thu, 16 Jun 2016 05:52:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44056) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDTyf-0001Eh-5V for qemu-devel@nongnu.org; Thu, 16 Jun 2016 05:52:45 -0400 References: <20160616060621.30422-1-haozhong.zhang@intel.com> <20160616060621.30422-4-haozhong.zhang@intel.com> From: Paolo Bonzini Message-ID: Date: Thu, 16 Jun 2016 11:52:37 +0200 MIME-Version: 1.0 In-Reply-To: <20160616060621.30422-4-haozhong.zhang@intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 3/3] i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Haozhong Zhang , qemu-devel@nongnu.org Cc: Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj , Laszlo Ersek On 16/06/2016 08:06, Haozhong Zhang wrote: > It's a prerequisite that certain bits of MSR_IA32_FEATURE_CONTROL should > be set before some features (e.g. VMX and LMCE) can be used, which is > usually done by the firmware. This patch adds a fw_cfg file > "etc/msr_feature_control" which contains the advised value of > MSR_IA32_FEATURE_CONTROL and can be used by guest firmware (e.g. SeaBIOS). > > Suggested-by: Paolo Bonzini > Signed-off-by: Haozhong Zhang > --- > hw/i386/pc.c | 28 ++++++++++++++++++++++++++++ > target-i386/cpu.h | 4 ++++ > 2 files changed, 32 insertions(+) > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 7198ed5..d8178a5 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -1147,6 +1147,33 @@ void pc_cpus_init(PCMachineState *pcms) > smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); > } > > +static void pc_build_feature_control_file(PCMachineState *pcms) > +{ > + X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu); > + CPUX86State *env = &cpu->env; > + uint32_t unused, ecx, edx, feature_control_bits = 0; > + uint32_t *val; > + > + cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); > + if (ecx & CPUID_EXT_VMX) { > + feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; > + } > + > + if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == > + (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && > + (env->mcg_cap & MCG_LMCE_P)) { > + feature_control_bits |= FEATURE_CONTROL_LMCE; > + } > + > + if (!feature_control_bits) { > + return; > + } > + > + val = g_malloc(sizeof(*val)); > + *val = feature_control_bits | FEATURE_CONTROL_LOCKED; > + fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); > +} > + > static > void pc_machine_done(Notifier *notifier, void *data) > { > @@ -1174,6 +1201,7 @@ void pc_machine_done(Notifier *notifier, void *data) > acpi_setup(); > if (pcms->fw_cfg) { > pc_build_smbios(pcms->fw_cfg); > + pc_build_feature_control_file(pcms); > } > } > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index f0cb04f..5e07c7a 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -332,6 +332,10 @@ > #define MSR_TSC_ADJUST 0x0000003b > #define MSR_IA32_TSCDEADLINE 0x6e0 > > +#define FEATURE_CONTROL_LOCKED (1<<0) > +#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) > +#define FEATURE_CONTROL_LMCE (1<<20) > + > #define MSR_P6_PERFCTR0 0xc1 > > #define MSR_IA32_SMBASE 0x9e > Reviewed-by: Paolo Bonzini Have you prepared a patch for SeaBIOS already? Thanks, Paolo