From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: Stop overwriting RING_IMR in rcs resume
Date: Thu, 18 Apr 2019 16:08:58 +0100 [thread overview]
Message-ID: <d80f798d-f0d3-3db8-d7e9-75f7742d73d8@linux.intel.com> (raw)
In-Reply-To: <155559954782.7644.12072686920658860496@skylake-alporthouse-com>
On 18/04/2019 15:59, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-04-18 15:34:09)
>>
>> On 18/04/2019 14:27, Chris Wilson wrote:
>>> We store the engine->imr mask and set up the RING_IMR register on
>>> restarting the engine. We do not then want to overwrite it with
>>> an incomplete mask later as we may then lose interrupts!
>>>
>>> Reported-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
>>> 1 file changed, 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index 029fd8ec1857..00bd9eeb053d 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -873,9 +873,6 @@ static int init_render_ring(struct intel_engine_cs *engine)
>>> if (IS_GEN_RANGE(dev_priv, 6, 7))
>>> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>>>
>>> - if (INTEL_GEN(dev_priv) >= 6)
>>> - ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
>>> -
>>> return 0;
>>> }
>>>
>>>
>>
>> Is it perhaps a way to enable L3_DPF on IVB and HSW when breadcrumbs are
>> off (no one listening)? Mind you, the same should be done in this case
>> under execlists for ctx switch irq. I just can't find the code there
>> which unmasks it unless a single engine->irq_enable/irq_disable cycle is
>> guaranteed on load indirectly. Is there a request_wait or wait_for_idle
>> hidden somewhere during init? Or I missed the ball completely?
>
> See intel_engine_reset_breadcrumbs(), we always re-emit the breadcrumb
> setup (IMR) for either the disabled or enabled state. That should make
> sure engine->irq_keep_mask is applied.
Ah.. thanks! Although it is a bit conceptually wrong that breadcrumbs
have to do the basic/unrelated engine setup. As such the legacy
submission indeed looks more correct, but still wrong that engine reset
can turn off user interrupts. Blah.. another pedestrian task for a rainy
day.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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next prev parent reply other threads:[~2019-04-18 15:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-18 13:27 [PATCH 1/2] drm/i915: Stop overwriting RING_IMR in rcs resume Chris Wilson
2019-04-18 13:27 ` [PATCH 2/2] drm/i915: Setup the RCS ring prior to execution Chris Wilson
2019-04-18 15:10 ` Tvrtko Ursulin
2019-04-18 14:34 ` [PATCH 1/2] drm/i915: Stop overwriting RING_IMR in rcs resume Tvrtko Ursulin
2019-04-18 14:59 ` Chris Wilson
2019-04-18 15:08 ` Tvrtko Ursulin [this message]
2019-04-18 15:14 ` Chris Wilson
2019-04-18 16:30 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2019-04-18 18:07 ` ✓ Fi.CI.IGT: " Patchwork
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