On Fri, Mar 10, 2023 at 07:03:36PM +0800, Song Shuai wrote:
> RISC-V now builds the sched domain based on the simple possible map.
> 
> Enable SCHED_MC to make the building based on cpu_coregroup_mask()
> which also takes care of the NUMA and cores with LLC.
> 
> Signed-off-by: Song Shuai <suagrfillet@gmail.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
>  arch/riscv/Kconfig | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index c5e42cc37604..5b9fdc1a619a 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -320,6 +320,14 @@ config SMP
>  
>  	  If you don't know what to do here, say N.
>  
> +config SCHED_MC
> +	bool "Multi-core scheduler support"
> +	depends on SMP
> +	help
> +	  Multi-core scheduler support improves the CPU scheduler's decision
> +	  making when dealing with multi-core CPU chips at a cost of slightly
> +	  increased overhead in some places. If unsure say N here.
> +
>  config NR_CPUS
>  	int "Maximum number of CPUs (2-512)"
>  	depends on SMP
> -- 
> 2.20.1
>