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Tue, 27 Dec 2022 15:04:26 -0800 (PST) Received: from [192.168.1.107] ([187.23.180.75]) by smtp.gmail.com with ESMTPSA id z36-20020a056870462400b00144e6ffe9e5sm6638168oao.47.2022.12.27.15.04.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Dec 2022 15:04:25 -0800 (PST) Message-ID: Date: Tue, 27 Dec 2022 20:04:20 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Cleber Rosa , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Beraldo Leal References: <20221221182300.307900-1-dbarboza@ventanamicro.com> <20221221182300.307900-2-dbarboza@ventanamicro.com> From: Wainer dos Santos Moschetta In-Reply-To: <20221221182300.307900-2-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=wainersm@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.147, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: wainersm@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Daniel, On 12/21/22 15:22, Daniel Henrique Barboza wrote: > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > Cc: Cleber Rosa > Cc: Philippe Mathieu-Daudé > Cc: Wainer dos Santos Moschetta > Cc: Beraldo Leal > Signed-off-by: Daniel Henrique Barboza > --- > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py It looks good to me. Thanks! Reviewed-by: Wainer dos Santos Moschetta > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > new file mode 100644 > index 0000000000..abc99ced30 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,65 @@ > +# opensbi boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=accel:tcg > + """ > + timeout = 5 > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_spike(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:spike > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_sifive_u(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_virt(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_sifive_u(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG')