From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WDj93-000167-Gl for qemu-devel@nongnu.org; Wed, 12 Feb 2014 18:23:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WDj8x-000148-Bh for qemu-devel@nongnu.org; Wed, 12 Feb 2014 18:23:09 -0500 Received: from mail-qc0-f172.google.com ([209.85.216.172]:37102) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WDj8x-000144-8Z for qemu-devel@nongnu.org; Wed, 12 Feb 2014 18:23:03 -0500 Received: by mail-qc0-f172.google.com with SMTP id c9so16833032qcz.31 for ; Wed, 12 Feb 2014 15:23:03 -0800 (PST) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Wed, 12 Feb 2014 15:22:30 -0800 Message-Id: In-Reply-To: References: Subject: [Qemu-devel] [PATCH microblaze/ppc v2 1/8] microblaze/s3adsp_1800: Define macros for irq map List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com Cc: agraf@suse.de Define macros for the interrupt map for the sake of self documentation. Signed-off-by: Peter Crosthwaite --- I haven't converted the xilinx_foo_create usages because they will be deleted in following patches hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index f500215..a4877a6 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -48,6 +48,10 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 +#define TIMER_IRQ 0 +#define ETHLITE_IRQ 1 +#define UARTLITE_IRQ 3 + static void machine_cpu_reset(MicroBlazeCPU *cpu) { CPUMBState *env = &cpu->env; @@ -99,7 +103,8 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) irq[i] = qdev_get_gpio_in(dev, i); } - sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]); + sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, + irq[UARTLITE_IRQ]); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); -- 1.8.5.4